Figure 15. Output Voltage Timing; Table 66. Turn On/Off Timing - Intel SHG2 DP Technical Product Specification

Intel® SHG2 DP Server Board Technical Product Specification
Vout
10% Vout
V1
V2
V3
V4
Table 66 shows the timing requirements for the power supply being turned on and off via the
AC input with PSON held low, and the power supply being turned on and off with the PSON
signal after AC input is applied.
Item
T Delay from AC being applied to 5VSB being
sb_on_delay
within regulation.
T Delay from AC being applied to all output
ac_on_delay
voltages being within regulation.
T Time all output voltages stay within regulation
vout_holdup
after loss of AC.
T Delay from loss of AC to deassertion of
pwok_holdup
PWOK
T Delay from PSON
pson_on_delay
within regulation limits.
T Delay from PSON
pson_pwok
deasserted.
T Delay from output voltages within regulation
pwok_on
limits to PWOK asserted at turn on.
Revision 1.0
T
vout rise
T
vout on

Figure 15. Output Voltage Timing

Table 66. Turn On/Off Timing

Description
#
active to output voltages
#
deactive to PWOK being
Intel Order Number C11343-001
General Specifications
T
vout_on
Min Max
1500
2500
21
20
5 400
50
100 1000
Units
msec
msec
msec
msec
msec
msec
msec
75