Cpu Architecture - Siemens C500 User Manual

2

CPU Architecture

The typical architecture of a C500 family microcontroller is shown in figure 2-1 . This block diagram
includes all main functional blocks of the C500 microcontrollers. The shaded blocks are basic
functional units which are mandatory for each C500 microcontroller. The other functional blocks
such as XRAM, peripheral units, and ROM/RAM sizes are specific to each C500 microcontroller
derivative.
Basic functional blocks
Figure 2-1
C500 Microcontroller Architecture Block Diagram
The core block represents the CPU (Central Processing Unit) of the C500 family microcontrollers.
The CPU consists of the instruction decoder, the arithmetic section, the CPU registers, and the
program control section. The housekeeper unit generates internal signals for controlling the
functions of the individual internal units within the microcontroller. Port 0 and port 2 are required for
accessing external code and data memory and for emulation purposes. The external control signals
and the clock generation are handled in the external control block. The access control unit is
responsible for the selection of the on-chip memory resources. The IRAM provides the internal RAM
which includes the general purpose registers. The interrupt requests from the peripheral units are
handled by an interrupt controller unit.
C500 device specific is the configuration of the on-chip peripheral units. Serial interfaces, timers,
capture/compare units, A/D converters, watchdog units, or a multiply/divide unit are typical
examples for on-chip peripheral units. The external signals of these peripheral units are available
at multifunctional parallel I/O ports or at dedicated pins.
Semiconductor Group
Interrupt
Controller
Serial
Port
Timers
A
D
MDU
WDU
IRAM
C500 Core
(1 or 8 Datapointer)
Control
Housekeeper
Port0/Port2
2-1
CPU Functions
C500 Family
XRAM
ROM
Access
Control
RST
EA
Ext.
PSEN
Control
ALE
XTAL
MCB02769
1998-04-01