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Siemens C500 User Manual

Siemens C500 User Manual

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C500
Microcontroller Family
Architecture and Instruction Set
UserÕs Manual 04.98

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Summary of Contents for Siemens C500

  • Page 1 C500 Microcontroller Family Architecture and Instruction Set UserÕs Manual 04.98...
  • Page 2 The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).

  • Page 3: Table Of Contents

    The Importance of Additional Datapointers ....... . 2-5 2.5.2 How the eight Datapointers of the C500 are realized ......2-5 2.5.3 Advantages of Multiple Datapointers .

  • Page 4: Fundamental Structure

    C500 microcontroller family. This includes the description of the architecture and the description of the complete instruction set. Detailed information about the different versions of the C500 microcontrollers are given in the specific User Manuals.

  • Page 5: Memory Organization

    C500 Family Memory Organization The memory resources of the C500 family microcontrollers are organized in different types of memories (data and program memory), which further can be located internally on the microcontroller chip or outside of the microcontroller. The memory partitioning of the C500 microcontrollers is typical for a Harvard architecture where data and program areas are held in separate memory areas.

  • Page 6: Internal Data Memory

    The content of the internal data memory (also XRAM) is not affected by a reset operation. After power-up the content is undefined, while it remains unchanged during and after a reset as long as the power supply is not turned off. The XRAM content is also maintained when the C500 microcontrollers are in power saving modes.
  • Page 7 Registerbank 2 Registerbank 1 08 H Internal SFR Area (direct addressable) Byte 1) This internal RAM area is optional. Some low-end C500 family microcontrollers don't provide this internal RAM area. MCD02767 Figure 1-2 Internal Data Memory Organization Semiconductor Group 1998-04-01...

  • Page 8: Internal Data Memory Xram

    Figure 1-3 XRAM Memory Mapping (256 Byte) Depending on the C500 derivative, the size of the XRAM area differs from 128 upto 3K byte. Further, the XRAM can be enabled or disabled. If an internal XRAM area is disabled, external data memory can be accessed in the address range of the internal XRAM.

  • Page 9: External Data Memory

    R0/R1 are used. 1.2.3 Special Function Register Area The registers of a C500 microcontroller, except the program counter and the four general purpose register banks, reside in the special function register (SFR) area. The special function register area typically provides 128 bytes of direct addressable SFRs.

  • Page 10: Cpu Architecture

    C500 Family CPU Architecture The typical architecture of a C500 family microcontroller is shown in figure 2-1 . This block diagram includes all main functional blocks of the C500 microcontrollers. The shaded blocks are basic functional units which are mandatory for each C500 microcontroller. The other functional blocks such as XRAM, peripheral units, and ROM/RAM sizes are specific to each C500 microcontroller derivative.

  • Page 11: Accumulator

    CPU Functions C500 Family The arithmetic section of the core performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. Further, it has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions.

  • Page 12: Stack Pointer

    CPU Functions C500 Family Special Function Register PSW (Address D0 H ) Reset Value : 00 H Bit No. D0 H Function Carry Flag Used by arithmetic and conditional branch instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations.

  • Page 13: Data Pointer

    DPTR as an 16-bit address register. Normally, the C500 family microcontrollers have one data pointer. But some members of the C500 family provide eight data pointers. The availability of eight data pointers especially supports the programming in high level languages which have a demand to store data in large external data memory portions.

  • Page 14: The Importance Of Additional Datapointers

    (DPTR, consisting of the two 8-bit SFRs DPH and DPL). To meet both of the above requirements (speed up external accesses, 100% compatibility to 8051 architecture) the C500 contains a set of eight 16-bit registers from which the actual datapointer can be selected.

  • Page 15: Advantages Of Multiple Datapointers

    CPU Functions C500 Family DPSEL(92 ) DPTR7 DPSEL Selected Data- pointer DPTR 0 DPTR0 DPTR 1 DPH(83 ) DPL(82 ) DPTR 2 DPTR 3 DPTR 4 External Data Memory DPTR 5 MCD00779 DPTR 6 DPTR 7 Figure 2-2 Accessing of External Data Memory via Multiple Datapointers 2.5.3 Advantages of Multiple Datapointers...
  • Page 16 CPU Functions C500 Family Example 1 : Using only One Datapointer (Code for a C501) Initialization Routine LOW(SRC_PTR), #0FFH ;Initialize shadow_variables with source_pointer HIGH(SRC_PTR), #1FH LOW(DES_PTR), #0A0H ;Initialize shadow_variables with destination_pointer HIGH(DES_PTR), #2FH Table Look-up Routine under Real Time Conditions...
  • Page 17 RAM and two additional stack bytes were spared, too. This means for some applications where all eight datapointers are employed that an C500 program has up to 24 byte (16 variables and 8 stack bytes) of the internal RAM free for other use.

  • Page 18: Enhanced Hooks Emulation Concept

    Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.

  • Page 19: Basic Interrupt Handling

    Figure 2-4 shows an example for the interrupt vector addresses of a C500 microcontroller (C501). Generally, interrupt vector addresses are located in the code memory area starting at address 0003 H . The minimum distance between two consecutive vector addresses is always 8 bytes.
  • Page 20 CPU Functions C500 Family Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to interrupt enable or interrupt priority registers, then at least one more instruction will be executed before any interrupt is vectored too;...

  • Page 21: Interrupt Response Time

    CPU Functions C500 Family Interrupt Response Time If an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. If the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be next instruction to be executed.

  • Page 22: Cpu Timing

    S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Depending on the C500 type of microcontroller, each state lasts either one or two periods of the oscillator clock. Typically, arithmetic and logical operations take place during phase 1 and internal register-to-register transfers take place during phase 2.
  • Page 23 CPU Timing C500 Family P1 P2 Read Read next Opcode Opcode (Discard) Read next Opcode again a) 1 Byte, 1-Cycle Instruction, e.g. INC A Read Read 2nd Opcode Byte Read next Opcode b) 2 Byte, 1-Cycle Instruction, e.g. ADD A, #Data...

  • Page 24: Accessing External Memory

    CPU Timing C500 Family Accessing External Memory There are two types of external memory accesses: accesses to external program memory and accesses to external data memory. Accesses to external program memory use the signal PSEN (program store enable) as the read strobe. Accesses to external data memory use the RD or WR (alternate functions of P3.7 and P3.6) to access the memory.

  • Page 25: Accessing External Data Memory

    CPU Timing C500 Family States P1 P2 PSEN Data Data Data Sampled Sampled Sampled PCH Out PCH Out PCH Out MCD02772 Figure 3-2 External Program Memory Fetches 3.2.2 Accessing External Data Memory The port 2 drivers use the strong pullups during the entire time that they are emitting address bits that are 1«s.
  • Page 26 CPU Timing C500 Family States P1 P2 PCL out if program memory Data Sampled is external Float Float DPL or Ri PCH or PCH or DPH or P2 SFR Out P2 SFR P2 SFR MCD02773 Figure 3-3 External Data Memory Read Cycle...

  • Page 27: Instruction Set

    Like all other members of the 8051-family, the C500 microcontrollers can be programmed with the same instruction set common to the basic member, the SAB 8051. Thus, the C500 family microcontrollers are 100% software compatible to the SAB 8051 and may be programmed with 8051 assembler or high-level languages.
  • Page 28 ACC. This mode facilitates look-up table accesses. Boolean Processor The Boolean processor is a bit processor integrated into the C500 family microcontrollers. It has its own instruction set, accumulator (the carry flag), bit-addressable RAM and l/O. The bit manipulation instructions allow: Ð...

  • Page 29: Introduction To The Instruction Set

    Instruction Set C500 Family Introduction to the Instruction Set The instruction set is divided into four functional groups: Ð data transfer Ð arithmetic Ð logic Ð control transfer 4.2.1 Data Transfer Instructions Data transfer operations are divided into three classes: Ð...

  • Page 30: Arithmetic Instructions

    4.2.2 Arithmetic Instructions The C500 family microcontrollers have four basic mathematical operations. Only 8-bit operations using unsigned arithmetic are supported directly. The overflow flag, however, permits the addition and subtraction operation to serve for both unsigned and signed binary integers. Arithmetic can also be performed directly on packed BCD representations.

  • Page 31: Logic Instructions

    C500 Family 4.2.3 Logic Instructions The C500 family microcontrollers perform basic logic operations on both bit and byte operands. Single-Operand Operations Ð CLR sets A or any directly addressable bit to zero (0). Ð SETB sets any directly bit-addressable bit to one (1).
  • Page 32 Instruction Set C500 Family Unconditional Calls, Returns and Jumps Unconditional calls, returns and jumps transfer control from the current value of the program counter to the target address. Both direct and indirect transfers are supported. Ð ACALL and LCALL push the address of the next instruction onto the stack and then transfer control to the target address.

  • Page 33: Instruction Definitions

    Instruction Set C500 Family Instruction Definitions All 111 instructions of the C500 family microcontrollers can essentially be condensed to 53 basic operations, in the following alphabetically ordered according to the operation mnemonic section. Table 4-2 PSW Flag Modification (CY,OV,AC) Instruction...
  • Page 34 Instruction Set C500 Family Notes on Data Addressing Modes: Working register R0-R7 direct 128 internal RAM locations, any l/O port, control or status register Indirect internal or external RAM location addressed by register R0 or R1 #data 8-bit constant included in instruction...
  • Page 35 Instruction Set C500 Family ACALL addr11 Function: Absolute call Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the stack pointer twice.
  • Page 36 Instruction Set C500 Family A, <src-byte> Function: Description: ADD adds the byte variable indicated to the accumulator, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.
  • Page 37 Instruction Set C500 Family A, @Ri Operation: (A) ¬ (A) + ((Ri)) Encoding: 0 0 1 0 0 1 1 i Bytes: Cycles: A, #data Operation: (A) ¬ (A) + #data Encoding: 0 0 1 0 0 1 0 0...
  • Page 38 Instruction Set C500 Family ADDC A, < src-byte> Function: Add with carry Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the accumulator contents, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise.
  • Page 39 Instruction Set C500 Family ADDC A, @Ri Operation: ADDC (A) ¬ (A) + (C) + ((Ri)) Encoding: 0 0 1 1 0 1 1 i Bytes: Cycles: ADDC A, #data Operation: ADDC (A) ¬ (A) + (C) + #data Encoding:...
  • Page 40 Instruction Set C500 Family AJMP addr11 Function: Absolute jump Description: AJMP transfers program execution to the indicated address, which is formed at run- time by concatenating the high-order five bits of the PC (after incrementing the PC twice), op code bits 7-5, and the second byte of the instruction. The destination must therefore be within the same 2K block of program memory as the first byte of the instruction following AJMP.
  • Page 41 Instruction Set C500 Family <dest-byte>, <src-byte> Function: Logical AND for byte variables Description: ANL performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable. No flags are affected (except P, if <dest-byte> = A).
  • Page 42 Instruction Set C500 Family A, @Ri Operation: (A) ¬ (A) Ù ((Ri)) Encoding: 0 1 0 1 0 1 1 i Bytes: Cycles: A, #data Operation: (A) ¬ (A) Ù #data Encoding: 0 1 0 1 0 1 0 0...
  • Page 43 Instruction Set C500 Family direct, #data Operation: (direct) ¬ (direct) Ù #data Encoding: 0 1 0 1 0 0 1 1 direct address immediate data Bytes: Cycles: Semiconductor Group 4-17 1998-04-01...
  • Page 44 Instruction Set C500 Family C, <src-bit> Function: Logical AND for bit variables Description: If the Boolean value of the source bit is a logic 0 then clear the carry flag; otherwise leave the carry flag in its current state. A slash (Ó/Ó preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected.
  • Page 45 Instruction Set C500 Family CJNE <dest-byte >, < src-byte >, rel Function: Compare and jump if not equal Description: CJNE compares the magnitudes of the tirst two operands, and branches if their values are not equal. The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction.
  • Page 46 Instruction Set C500 Family CJNE A,direct,rel (PC) ¬ (PC) + 3 Operation: if (A) < > (direct) then (PC) ¬ (PC) + relative offset if (A) < (direct) then (C) ¬1 else (C) ¬ 0 Encoding: 1 0 1 1...
  • Page 47 Instruction Set C500 Family CJNE @Ri, #data, rel (PC) ¬ (PC) + 3 Operation: if ((Ri)) < > data then (PC) ¬ (PC) + relative offset if ((Ri)) < data then (C) ¬ 1 else (C) ¬ 0 Encoding: 1 0 1 1...
  • Page 48 Instruction Set C500 Family Function: Clear accumulator Description: The accumulator is cleared (all bits set to zero). No flags are affected. Example: The accumulator contains 5C H (01011100 B ). The instruction will leave the accumulator set to 00 H (00000000 B ).
  • Page 49 Instruction Set C500 Family Function: Clear bit Description: The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit. Example: Port 1 has previously been written with 5D H (01011101 B ). The instruction P1.2...
  • Page 50 Instruction Set C500 Family Function: Complement accumulator Description: Each bit of the accumulator is logically complemented (oneÕs complement). Bits which previously contained a one are changed to zero and vice versa. No flags are affected. Example: The accumulator contains 5C H (01011100 B ). The instruction will leave the accumulator set to 0A3 H (10100011 B ).
  • Page 51 Instruction Set C500 Family Function: Complement bit Description: The bit variable specified is complemented. A bit which had been a one is changed to zero and vice versa. No other flags are affected. CPL can operate on the carry or any directly addressable bit.
  • Page 52 Instruction Set C500 Family Function: Decimal adjust accumulator for addition Description: DA A adjusts the eight-bit value in the accumulator resulting from the earlier addition of two variables (each in packed BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition.
  • Page 53 Instruction Set C500 Family BCD variables can be incremented or decremented by adding 01 H or 99 H . If the accumulator initially holds 30 H (representing the digits of 30 decimal), then the instruction sequence A, #99H will leave the carry set and 29 H in the accumulator, since 30 + 99 = 129. The low- order byte of the sum can be interpreted to mean 30 Ð...
  • Page 54 Instruction Set C500 Family byte Function: Decrement Description: The variable indicated is decremented by 1. An original value of 00 H will underflow to 0FF H . No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect.
  • Page 55 Instruction Set C500 Family direct Operation: (direct) ¬ (direct) Ð 1 Encoding: 0 0 0 1 0 1 0 1 direct address Bytes: Cycles: Operation: ((Ri)) ¬ ((Ri)) Ð 1 Encoding: 0 0 0 1 0 1 1 i Bytes:...
  • Page 56 Instruction Set C500 Family Function: Divide Description: DIV AB divides the unsigned eight-bit integer in the accumulator by the unsigned eight-bit integer in register B. The accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags will be cleared.
  • Page 57 Instruction Set C500 Family DJNZ <byte>, <rel-addr> Function: Decrement and jump if not zero Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00 H will underflow to 0FF H .
  • Page 58 Instruction Set C500 Family DJNZ Rn,rel Operation: DJNZ (PC) ¬ (PC) + 2 (Rn) ¬ (Rn) Ð 1 if (Rn) > 0 or (Rn) < 0 then (PC) ¬ (PC) + rel Encoding: 1 1 0 1 1 r r r rel.
  • Page 59 Instruction Set C500 Family <byte> Function: Increment Description: INC increments the indicated variable by 1. An original value of 0FF H will overflow to 00 H . No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect.
  • Page 60 Instruction Set C500 Family direct Operation: (direct) ¬ (direct) + 1 Encoding: 0 0 0 0 0 1 0 1 direct address Bytes: Cycles: Operation: ((Ri)) ¬ ((Ri)) + 1 Encoding: 0 0 0 0 0 1 1 i Bytes:...
  • Page 61 Instruction Set C500 Family DPTR Function: Increment data pointer Description: Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 ) is performed; an overflow of the low-order byte of the data pointer (DPL) from 0FF H to 00 H will increment the high-order byte (DPH).
  • Page 62 Instruction Set C500 Family bit,rel Function: Jump if bit is set Description: If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.
  • Page 63 Instruction Set C500 Family bit,rel Function: Jump if bit is set and clear bit Description: If the indicated bit is one, branch to the address indicated; otherwise proceed with the next instruction. In either case, clear the designated bit. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.
  • Page 64 Instruction Set C500 Family Function: Jump if carry is set Description: If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative- displacement in the second instruction byte to the PC, after incrementing the PC twice.
  • Page 65 Instruction Set C500 Family @A + DPTR Function: Jump indirect Description: Add the eight-bit unsigned contents of the accumulator with the sixteen-bit data pointer, and load the resulting sum to the program counter. This will be the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 2 ): a carry-out from the low-order eight bits propagates through the higher-order bits.
  • Page 66 Instruction Set C500 Family bit,rel Function: Jump if bit is not set Description: If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.
  • Page 67 Instruction Set C500 Family Function: Jump if carry is not set Description: If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction.
  • Page 68 Instruction Set C500 Family Function: Jump if accumulator is not zero Description: If any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice.
  • Page 69 Instruction Set C500 Family Function: Jump if accumulator is zero Description: If all bits of the accumulator are zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice.
  • Page 70 Instruction Set C500 Family LCALL addr16 Function: Long call Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the stack pointer by two.
  • Page 71 Instruction Set C500 Family LJMP addr16 Function: Long jump Description: LJMP causes an unconditional branch to the indicated address, by loading the high- order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space.
  • Page 72 Instruction Set C500 Family <dest-byte>, <src-byte> Function: Move byte variable Description: The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected.
  • Page 73 Instruction Set C500 Family A,@Ri Operation: (A) ¬ ((Ri)) Encoding: 1 1 1 0 0 1 1 i Bytes: Cycles: A, #data Operation: (A) ¬ #data Encoding: 0 1 1 1 0 1 0 0 immediate data Bytes: Cycles: Rn,A Operation: (Rn) ¬...
  • Page 74 Instruction Set C500 Family Rn, #data Operation: (Rn) ¬ #data Encoding: 0 1 1 1 1 r r r immediate data Bytes: Cycles: direct,A Operation: (direct) ¬ (A) Encoding: 1 1 1 1 0 1 0 1 direct address Bytes:...
  • Page 75 Instruction Set C500 Family direct, @ Ri Operation: (direct) ¬ ((Ri)) Encoding: 1 0 0 0 0 1 1 i direct address Bytes: Cycles: direct, #data Operation: (direct) ¬ #data Encoding: 0 1 1 1 0 1 0 1 direct address...
  • Page 76 Instruction Set C500 Family @ Ri,#data Operation: ((Ri)) ¬ #data Encoding: 0 1 1 1 0 1 1 i immediate data Bytes: Cycles: Semiconductor Group 4-50 1998-04-01...
  • Page 77 Instruction Set C500 Family <dest-bit>, <src-bit> Function: Move bit data Description: The Boolean variable indicated by the second operand is copied into the location specified by the first operand. One of the operands must be the carry flag; the other may be any directly addressable bit.
  • Page 78 Instruction Set C500 Family DPTR, #data16 Function: Load data pointer with a 16-bit constant Description: The data pointer is loaded with the 16-bit constant indicated. The 16 bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the low-order byte.
  • Page 79 Instruction Set C500 Family MOVC A, @A + <base-reg> Function: Move code byte Description: The MOVC instructions load the accumulator with a code byte, or constant from program memory. The address of the byte fetched is the sum of the original unsigned eight-bit accumulator contents and the contents of a sixteen-bit base register, which may be either the data pointer or the PC.
  • Page 80 Instruction Set C500 Family MOVC A, @A + PC Operation: MOVC (PC) ¬ (PC) + 1 (A) ¬ ((A) + (PC)) Encoding: 1 0 0 0 0 0 1 1 Bytes: Cycles: Semiconductor Group 4-54 1998-04-01...
  • Page 81 An external 256-byte RAM using multiplexed address/data lines is connected to the C500 port 0. Port 3 provides control lines for the external RAM. Ports 1 and 2 are used for normal l/O. Registers 0 and 1 contain 12 H and 34 H . Location 34 H of the external RAM holds the value 56 H .
  • Page 82 Instruction Set C500 Family MOVX A,@Ri Operation: MOVX (A) ¬ ((Ri)) Encoding: 1 1 1 0 0 0 1 i Bytes: Cycles: MOVX A,@DPTR Operation: MOVX (A) ¬ ((DPTR)) Encoding: 1 1 1 0 0 0 0 0 Bytes: Cycles:...
  • Page 83 Instruction Set C500 Family Function: Multiply Description: MUL AB multiplies the unsigned eight-bit integers in the accumulator and register B. The low-order byte of the sixteen-bit product is left in the accumulator, and the high-order byte in B. If the product is greater than 255 (0FF H ) the overflow flag is set;...
  • Page 84 Instruction Set C500 Family Function: No operation Description: Execution continues at the following instruction. Other than the PC, no registers or flags are affected. Example: It is desired to produce a low-going output pulse on bit 7 of port 2 lasting exactly 5 cycles.
  • Page 85 Instruction Set C500 Family <dest-byte>, <src-byte> Function: Logical OR for byte variables Description: ORL performs the bitwise logical OR operation between the indicated variables, storing the results in the destination byte. No flags are affected (except P, if <dest-byte> = A).
  • Page 86 Instruction Set C500 Family A,direct Operation: (A) ¬ (A) Ú (direct) Encoding: 0 1 0 0 0 1 0 1 direct address Bytes: Cycles: A,@Ri Operation: (A) ¬ (A) Ú ((Ri)) Encoding: 0 1 0 0 0 1 1 i...
  • Page 87 Instruction Set C500 Family direct, #data Operation: (direct) ¬ (direct) Ú #data Encoding: 0 1 0 0 0 0 1 1 direct address immediate data Bytes: Cycles: Semiconductor Group 4-61 1998-04-01...
  • Page 88 Instruction Set C500 Family C, <src-bit> Function: Logical OR for bit variables Description: Set the carry flag if the Boolean value is a logic 1; leave the carry in its current state otherwise. A slash (Ó/Ó) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected.
  • Page 89 Instruction Set C500 Family direct Function: Pop from stack Description: The contents of the internal RAM location addressed by the stack pointer is read, and the stack pointer is decremented by one. The value read is the transfer to the directly addressed byte indicated.
  • Page 90 Instruction Set C500 Family PUSH direct Function: Push onto stack Description: The stack pointer is incremented by one. The contents of the indicated variable is then copied into the internal RAM location addressed by the stack pointer. Otherwise no flags are affected.
  • Page 91 Instruction Set C500 Family Function: Return from subroutine Description: RET pops the high and low-order bytes of the PC successively from the stack, decrementing the stack pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL.
  • Page 92 Instruction Set C500 Family RETI Function: Return from interrupt Description: RETI pops the high and low-order bytes of the PC successively from the stack, and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The stack pointer is left decremented by two. No other registers are affected;...
  • Page 93 Instruction Set C500 Family Function: Rotate accumulator left Description: The eight bits in the accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected. Example: The accumulator holds the value 0C5 H (11000101 B ). The instruction leaves the accumulator holding the value 8B H (10001011 B ) with the carry unaffected.
  • Page 94 Instruction Set C500 Family Function: Rotate accumulator left through carry flag Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position.
  • Page 95 Instruction Set C500 Family Function: Rotate accumulator right Description: The eight bits in the accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected. Example: The accumulator holds the value 0C5 H (11000101 B ). The instruction leaves the accumulator holding the value 0E2 H (11100010 B ) with the carry unaffected.
  • Page 96 Instruction Set C500 Family Function: Rotate accumulator right through carry flag Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position.
  • Page 97 Instruction Set C500 Family SETB <bit> Function: Set bit Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directiy addressable bit. No other flags are affected. Example: The carry flag is cleared. Output port 1 has been written with the value 34 H (00110100 B ).
  • Page 98 Instruction Set C500 Family SJMP Function: Short jump Description: Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it.
  • Page 99 Instruction Set C500 Family SUBB A, <src-byte> Function: Subtract with borrow Description: SUBB subtracts the indicated variable and the carry flag together from the accumulator, leaving the result in the accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and clears C otherwise. (If C was set before...
  • Page 100 Instruction Set C500 Family SUBB A,direct Operation: SUBB (A) ¬ (A) Ð (C) Ð (direct) Encoding: 1 0 0 1 0 1 0 1 direct address Bytes: Cycles: SUBB A, @ Ri Operation: SUBB (A) ¬ (A) Ð (C) Ð ((Ri))
  • Page 101 Instruction Set C500 Family SWAP Function: Swap nibbles within the accumulator Description: SWAP A interchanges the low and high-order nibbles (four-bit fields) of the accumulator (bits 3-0 and bits 7-4). The operation can also be thought of as a four- bit rotate instruction.
  • Page 102 Instruction Set C500 Family A, <byte> Function: Exchange accumulator with byte variable Description: XCH loads the accumulator with the contents of the indicated variable, at the same time writing the original accumulator contents to the indicated variable. The source/ destination operand can use register, direct, or register-indirect addressing.
  • Page 103 Instruction Set C500 Family A, @ Ri Operation: ¬ ® ((Ri)) Encoding: 1 1 0 0 0 1 1 i Bytes: Cycles: Semiconductor Group 4-77 1998-04-01...
  • Page 104 Instruction Set C500 Family XCHD A,@Ri Function: Exchange digit Description: XCHD exchanges the low-order nibble of the accumulator (bits 3-0, generally representing a hexadecimal or BCD digit), with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected.
  • Page 105 Instruction Set C500 Family <dest-byte>, <src-byte> Function: Logical Exclusive OR for byte variables Description: XRL performs the bitwise logical Exclusive OR operation between the indicated variables, storing the results in the destination. No flags are affected (except P, if <dest-byte> = A).
  • Page 106 Instruction Set C500 Family A,direct Operation: (A) ¬ (A) (direct) Encoding: 0 1 1 0 0 1 0 1 direct address Bytes: Cycles: A, @ Ri Operation: (A) ¬ (A) ((Ri)) Encoding: 0 1 1 0 0 1 1 i...
  • Page 107 Instruction Set C500 Family direct, #data Operation: (direct) ¬ (direct) #data Encoding: 0 1 1 0 0 0 1 1 direct address immediate data Bytes: Cycles: Semiconductor Group 4-81 1998-04-01...

  • Page 108: Instruction Set Summary Tables

    C500 Family Instruction Set Summary Tables The following two tables give a survey about the instruction set of the C500 family microcontrollers. In table 4-3 the instructions are ordered in functional groups. In table 4-4 the instructions are ordered in the hexadecimal order of their opcode.
  • Page 109 Instruction Set C500 Family Table 4-3 : Instruction Set Summary (contÕd) Mnemonic Description Byte Cycle Logic Operations A,Rn AND register to accumulator A,direct AND direct byte to accumulator A,@Ri AND indirect RAM to accumulator A,#data AND immediate data to accumulator...
  • Page 110 Instruction Set C500 Family Table 4-3 : Instruction Set Summary (contÕd) Mnemonic Description Byte Cycle Data Transfer A,Rn Move register to accumulator A,direct Move direct byte to accumulator A,@Ri Move indirect RAM to accumulator A,#data Move immediate data to accumulator...
  • Page 111 Instruction Set C500 Family Table 4-3 : Instruction Set Summary (contÕd) Mnemonic Description Byte Cycle Boolean Variable Manipulation Clear carry flag Clear direct bit SETB Set carry flag SETB Set direct bit Complement carry flag Complement direct bit C,bit AND direct bit to carry flag...
  • Page 112 Instruction Set C500 Family Table 4-3 : Instruction Set Summary (contÕd) Mnemonic Description Byte Cycle Program and Machine Control (contÕd) CJNE A,#data,rel Compare immediate to A and jump if not equal CJNE Rn,#data rel Compare immed. to reg. and jump if not equal...

  • Page 113: Hexadecimal Ordered Instructions

    Instruction Set C500 Family 4.4.2 Hexadecimal Ordered Instructions Table 4-4 : Instruction List in Hexadecimal Order Mnemonic Mnemonic Mnemonic Code Code Code 00 H 20 H bit.rel 40 H 01 H AJMP addr11 21 H AJMP addr11 41 H AJMP...
  • Page 114 Instruction Set C500 Family Table 4-4 : Instruction List in Hexadecimal Order (contÕd) Mnemonic Mnemonic Mnemonic Code Code Code 60 H 80 H SJMP A0 H C,/bit 61 H AJMP addr11 81 H AJMP addr11 A1 H AJMP addr11 62 H...
  • Page 115 Instruction Set C500 Family Table 4-4 : Instruction List in Hexadecimal Order (contÕd) Mnemonic Mnemonic Mnemonic Code Code Code C0 H PUSH direct E0 H MOVX A,@DPTR C1 H AJMP addr11 E1 H AJMP addr11 C2 H E2 H MOVX A,@R0...

  • Page 116: Package Information

    This chapter shows typical package outlines of the packages which are actually used for the microcontrollers of the C500 family. The appropriate data sheet should always be regarded when the package of a specific C500 microcontroller has to be referenced.

  • Page 117: Plcc Packages

    Package Information C500 Family PLCC Packages P-LCC-44-2 (SMD) (Plastic Leaded Chip Carrier Package) GPL05102 SMD = Surface Mounted Device Dimensions in mm Figure 5-2 P-LCC-44-2 Package Outlines Semiconductor Group 1998-04-01...
  • Page 118 Package Information C500 Family P-LCC-68-4 (SMD) (Plastic Leaded Chip Carrier Package) 1.2 x 45° 1.27 0.81 max 23.3 ±0.3 0.38 0.43 ±0.1 24.21 ±0.07 0.18 25.28 -0.26 20.32 Index Marking 0.5 x 45° 1.1 x 45° 24.21 ±0.07 25.28 -0.26 GPL5099 1) Does not include plastic or metal protrusions of 0.15 max per side...
  • Page 119 Package Information C500 Family P-LCC-84-2 (SMD) (Plastic Leaded Chip Carrier Package) GPM05620 SMD = Surface Mounted Device Dimensions in mm Figure 5-4 P-LCC-84-2 Package Outline Semiconductor Group 1998-04-01...

  • Page 120: Mqfp Packages

    Package Information C500 Family MQFP Packages P-MQFP-44-2 (SMD) (Plastic Metric Quad Flat Package) GPM05622 SMD = Surface Mounted Device Dimensions in mm Figure 5-5 P-MQFP-44-2 Package Outline Semiconductor Group 1998-04-01...
  • Page 121 Package Information C500 Family P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Package) 0.65 0.88 ±0.08 12.35 0.12 17.2 D 80x Index Marking 0.6x45° 1) Does not include plastic or metal protrusions of 0.25 max per side GPM05249 SMD = Surface Mounted Device...
  • Page 122 Package Information C500 Family P-MQFP-100-2 (SMD) (Plastic Metric Quad Flat Package, rectangular) GPM05623 SMD = Surface Mounted Device Dimensions in mm Figure 5-7 P-MQFP-100-2 Package Outline Semiconductor Group 1998-04-01...

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