VIORE PDP4210EA Service Manual page 64

ESMT
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2; 2.5; 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
V = 2.375V ~ 2.75V, V
DD
Auto & Self refresh
7.8us refresh interval
SSTL-2 I/O interface
66pin TSOPII package
Operating Frequencies :
PRODUCT NO.
M13S128168A -5T
M13S128168A -6T
Elite Semiconductor Memory Technology Inc.
= 2.375V ~ 2.75V
DDQ
MAX FREQ VDD
200MHz
2.5V
166MHz
2M x 16 Bit x 4 Banks
Double Data Rate SDRAM
PACKAGE
TSOPII
M13S128168A
Publication Date : Mar. 2004
Revision : 1.3 2/48