VIORE PDP4210EA Service Manual page 59

SiI 169 HDCP PanelLink Receiver
Data Sheet
Table 1. One Pixel per Clock Mode Data Mapping ....................................................................................... 16
Table 2. Two Pixel per Clock Mode Data Mapping ....................................................................................... 16
Table 3. One Pixel per Clock Input/Output TFT Mode – VESA P&D and FPDI-2
Table 4. Two Pixels/Clock Input/Output TFT Mode ...................................................................................... 18
Table 5. 24-bit One Pixel per Clock Input with 24-bit Two Pixel per Clock Output TFT Mode...................... 19
Table 6. 18-bit One Pixel per Clock Input with 18-bit Two Pixel per Clock Output TFT Mode...................... 20
Table 7. Two Pixel per Clock Input with One Pixel per Clock Output TFT Mode.......................................... 21
Table 8. Power Management Functionality Table ......................................................................................... 22
2
Table 9. I C Register Mapping ...................................................................................................................... 26
2
Table 10. I C Register Definitions ................................................................................................................. 27
Table 11. Link Impedance vs EXT_RES Value (all values in Ohms) ............................................................ 29
Table 12. Power Consumption Characteristics ............................................................................................. 30
Table 13. Recommended Components ........................................................................................................ 32
Figure 1. SiI 169 Pin Diagram......................................................................................................................... 1
Figure 2. Functional Block Diagram................................................................................................................ 2
Figure 3. Channel-to-Channel Skew Timing ................................................................................................... 8
Figure 4. Digital Output Transition Times ....................................................................................................... 8
Figure 5. Receiver Clock Cycle/High/Low Times............................................................................................ 8
Figure 6. Output Signals Setup/Hold Times.................................................................................................... 9
Figure 7. Output Signals Disabled Timing from PD# Active ........................................................................... 9
Figure 8. Output Signals Disabled Timing from Input Clock Inactive.............................................................. 9
Figure 9. Input Clock Active to Output Active ................................................................................................ 9
Figure 10. SCDT Timing from DE Inactive/Active......................................................................................... 10
Figure 11. TFT Two Pixels per Clock Staggered Output Timing Diagram .................................................... 10
2
Figure 12. I C Data Valid Delay (driving Read Cycle data) ........................................................................... 10
Figure 13. Block Diagram for OCK_INV ....................................................................................................... 15
Figure 14. HDCP System Architecture ........................................................................................................ 23
2
Figure 15. I C Byte Read .............................................................................................................................. 24
2
Figure 16. I C Byte Write .............................................................................................................................. 24
Figure 17. Short Read Sequence ................................................................................................................. 25
Figure 18. Design Using SiI 161B or SiI 169 ................................................................................................ 29
Figure 19. DDC Bus Voltage Level-Shifting using Fairchild NDC7002N ...................................................... 30
Figure 20. Voltage Regulation using Texas Instruments TL431 ................................................................... 31
Figure 21. Voltage Regulation using National Semiconductor LM317.......................................................... 31
Figure 22. Decoupling and Bypass Schematic ............................................................................................. 32
Figure 23. Decoupling and Bypass Capacitor Placement ............................................................................ 32
Figure 24. DVI to Receiver Routing - Top View ............................................................................................ 33
Figure 25. Bottom View of Thermally Enhanced 100-pin TQFP Package.................................................... 34
Figure 26. TQFP Thermal Land Design on PCB .......................................................................................... 35
Figure 27. Thermal Pad Via Grid .................................................................................................................. 36
Figure 28. Recommended Stencil Design .................................................................................................... 37
Figure 29. Package Diagram ........................................................................................................................ 38
LIST OF TABLES
LIST OF FIGURES
iv
TM
Compliant.................... 17
SiI-DS-0049-B