VIORE PDP4210EA Service Manual page 52

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2D-Graphic/OSD processor
Two OSD planes. (For example, Teletext and V-Chip will occupy one planes)
Support alpha blending among these two planes and video
Support Text/Bitmap decoder
Support line/rectangle/gradient fill
Support bitblt
Support color Key function
Support Clip Mask
65535/256/16/4/2-color bitmap format OSD,
Automatic vertical scrolling of OSD image
Support OSD mirror and upside down
Host Micro controller
Turbo 8032 micro controller
Built-in internal 373 and 8-bit programmable lower address port
2048-bytes on-chip RAM
Up to 4M bytes FLASH-programming interface
Supports 5/3.3-Volt. FLASH interface
Supports power-down mode
Supports additional serial interface
IR control serial input
Support RS232 interface
Support single interface directly supporting SD/MS/MMC memory card
Support 2 PWM output
Support DDC2Bi/DDC2B/DDC1/DDCCI
Maximum 48 programmable GPIO pins
DRAM Controller
Supports up to 32M-byte SDR/DDR DRAM
Supports 16 bit DDR or 32 bit SDR/DDR bus interface
Build in a DRAM interface programmable clock to optimize the DRAM performance
Programmable DRAM access cycle and refresh cycle timings
Maximum DRAM clock rate is 166MHz
Support 3.3/2.5-Volt SDR/DDR Interface
Video Processor
Color Management
Flesh tone and multiple-color enhancement. (For skin, sky, and grass...)
Gamma/anti-Gamma correction
Color Transient Improvement (CTI)
Saturation/hue adjustment
Contrast/Brightness/Sharpness Management
Sharpness and DLTI/DCTI
Brightness and contrast adjustment
Black level extender
White peak level limiter
Adaptive Luma/Chroma management
De-interlacing
Automatic detect film or video source
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MT8205
MTK CONFIDENTIAL, NO DISCLOSURE
July, 2004