Dt And Gs-Board Block Diagram - Panasonic th-58px60u Service Manual

15.29. DT and GS-Board Block Diagram

DT ATSC INTERFACE
IC8206
AGC AMP(IF STRIP)
XF8200
OUT1
2 7
X9303P
3 6
OUT2
4 AGC CTL
IF_AGC
IC8205
7
IC8204
1
L/H CHECK
DIGITAL
RF AGC
2 1
O/I I/0
D_A_SW
CONT 4
D_A_SW
D_A_SW
H ON
OFF
L
D_A_SW
H DIGITAL
IC8203
L ANALOG
L/H CHECK
ANALOG Q8217
RF AGC
2 O/I I/0 1
CONT 4
TU8200
TUNER Q8218
IF_SW
OOB OUT
H ON
1
AGC L OFF
8
SCL_TUNER
SCL
10
SDA_TUNER
SDA
9
AFT
AFT
11
AGC OUT
12
VIDEO_OUT
VIDEO_OUT
13
L_OUT
16
R_OUT
15
IF_OUT
19
Q8219
IF_SW
20
30V
BTL
4
ANT_V
SUPPLY
2
5V_A
V_SUPPLY
7
BV
18
GS SD CARD SLOT
SD CARD 3.3V
3.3V
JK7701 GS52 DT10
SLOT
3.3V 4 1
3.3V
SDCMD DATA0
2 8
SDCLK 5 9 DATA1
SDDAT0 7 8 10 DATA2
DATA3
SDDAT3 9 1 11
5 SDCMD
D.SW
SDCLK
3
W.P .
7 SDCD
12 SDWP
TH-58PX60U
DT and GS-Board Block Diagram
IC8211
FRONT PROCESSOR
(TERRESTRIAL RECEIVER)
PSYNC0
MPEG_CLK 108
MPEG_ERR 93
ENABLE0
MPEG_DATA_EN 94
PSYNC0
MPEG_PKT_SYNC 91
SCHDATA0
SER_DATA 106
35 XO
TO FRONT
X8200
TDI 137
36 XI
TRST
FILTER TRST 136
FAT_P TMS
C8413,8414 TMS 135
39 JTAG
IBAINP
TCK
C8432-8436
FAT_N TCK 134
L8303-8305 40 IBAINN
176 AGC_CONT
INT 84
NRST 68
IC8229
AGC AMP
EEPROM
6 53 RF_AGC
SDA 87 5
SDA
54 IF_AGC
5 SCL 88 6 SCL
62 OBMSDA
3
63 OBMSCL
SCL1
2 SDA1
SCL_FE
MAIN_SW SDA_FE
H ANALOG
L DIGITAL
MAIN_SW
Q8220
IC8202
SERIAL SW
1
13
2
3
5 SDA_TV
4
SCL_TV
8
6
9
10
12
11
AFT/VIDEO_OUT
IC8254
L_ANALOG 128M FLASH ROM
ED16-ED31
R_ANALOG DQ0-DQ15
EA1-EA23
A0-A22
XRST
IC8201
AUDIO AMP
2
L_OUT
1
3
5 9V SUB
R_OUT
7
6
3.3V
1
DATA0
8
DATA1
9 TO
DT07
DATA2
HC06
10
DATA3
+5V 1
11
CMD
SBI0 2
5
CLK
SBO0 3
3
SDCD
7
SDWP
12
IC8246
5V_SUB DC-DC CONVERTER
9V 3.3V
5 VCC VIN 21
20 CB OUT-1 19
17 16
VDD OUT-2
G2 S2 G1
D2 D2 D1
LX 18
9V_POWER
-INC 13
9 CTL VO 23
FB 24
XIRQ1 FRONT
JTAG I/F
XFERST0 IC8240
Joint
PSYNC0
Test
PSYNC0
HDSL PEAKS_Lite Action
ENABLE0
ENABLE0
Group
SCHDATA0
TD2S
SCHDATA0
SCHCLK0
MCP2L
SCHCLK0
AM33(200MHz)
NTSC ENC.
VIDEO DAC
PERIPHERAL
SCL0 SCL0
SDA0 SDA0
SCL1 SCL1
SDA1 SDA1
XWP PEAKS_Lite(1/3)
ALE
CLE
PEAKS_Lite(3/3)
RE
WE
ED16
DATA BUS
ED31
EA1
ADDRESS BUS
NOR FLASH ROM I/F
EA23
XECS0L
CONTROL BUS
XEREL
XEWE2
FWP
IC8200
AUDIO DAC
PDN 5 DACRST
11 AOUTL MCLK 1 DACCK
BICK 2 SRCK
SDTI DMIX
10 AOUTR 3
LRCK 4 LRCK
DATA0
SD_DATA0
DATA1
SD_DATA1
DATA2
SD_DATA2
DATA3
SD_DATA3
CMD
SDCMD
CLK
SDCLK
SDCD PEAKS_Lite(1/3)
5V_SUB SDCD
SDWP
SDWP
SBI0
SBO0
SBO2
SBI2
PEAKS_Lite(2/3)
IR
VDD12 VDD33 AAVDD DAVDD MAVDD SVAVDD
1.2V 3.3V
99
9V_SUB 9V_POWER IC8247 9V_SUB 9V_POWER
5V_SUB DC-DC CONVERTER
9V 1.2V
21
5 VCC VIN
20
CB OUT-1 19
17 16
VDD OUT-2
S1 G2 S2 G1 S1
D1 D2 D2 D1 D1
LX 18
Q8229 3.3V 9V_POWER Q8230 1.2V
-INC 13
9 CTL VO 23
FB 24
IC8227
3.3V
RESET 2
XRST 4 OUT VDD 2
IC8228
SUB 9V
RESET
1 VOUT VDD 2
TCK
TMS
TD0
TRST
TDI
TMS
TMS
TCK
SCL1
TCK
POWER_DET SDA1
POWER_DET IC8022
SDA_TV
SD_BOOT
SD_BOOT
SCL_TV
XRST VCXO
XRST
AFT
133M 10
MAIN_SW
VC27 4 VIN X1 1
R_ANALOG
X8005
CLK74 7 74M
L_ANALOG
MCK27 9 27M X2 16
R_OUT
L_OUT
SBO1
VIDEO_OUT
SBO1
SBI1
SBI1
POWER_DET
ISOVAL
ISOVAL
SDBOOT
ISOCLK
ISOCLK IC8009,IC8010
XRST
ISOSYNC
ISOSYNC
SBO1
256M DDR SDRAM
SBI1
MMDQ0
DATA BUS
VSYNC
MMDQ31
CLK
MMA0
ADDRESS BUS
D8208
HSYNC
MMA13 DIGITAL
30V
3.3V AUDIO OUT
CONTROL BUS
9V_SUB
IEC_OUT
IC8244
5V_A
5V_SUB
16Bit AUDIO A/D
ADIN
9
ADIN SDTO
SLRCK
SLRCK 10 LRCK
MAIN_R
ADCCK 1
AINR
ADCCK 11 MCLK
MAIN_L
DSRCK
AINL 2
12
DSRCK SCLK
PDWN
PDWN 13 PDN
MVY0
MVY0 MVY7
MVY7
MVC0
MVC0 MVC7
MVC7
MHSYNC0
MVSYNC0
MVCLK0
Q8211
DC
Q8210
DY
XSRQ Q8209
FORMAT EDGE
2.5V IC8235
VDDQ
(DDR SDRAM)
MVAVDD AVDD 3.3V
AVR 2.5V
2.5V
1 6
VOUT VDD
TH-58PX60U
DT and GS-Board Block Diagram
TH-58PX60U
TO
DT12
DG22
26 TCK
27 TMS
30 TRST(JTAG_TRST)
32 SCL1(DTV_SCL0B)
33 SDA1(DTV_SDA0B)
SDA_TV
34
(SDA0B)
SCL_TV
35
(SCL0B)
37
AFT(AFT1)
MAIN_SW
36
62 ATV_SR
64 ATV_SL
43
R_OUT(BS_SR)
41 L_OUT(BS_SL)
13 VIDEO_OUT
POWER_DET
15
(SW_OFF)
16 SDBOOT
22 XRST(DTV_RST)
SBO1(RXD1)
18
19 SBI1(TXD1)
80 VSYNC
85 CLK
87 HSYNC
8 30V(BT30V)
SUB 9V
51
52 SUB 9V
53 SUB 9V
54 SUB 5V
57 SUB 5V
58 MAIN_R
60 MAIN_L
88 MVY0 (PEAKS_Y0)
96
MVY7 (PEAKS_Y7)
97 MVC0 (PEAKS_C0)
105 MVC7 (PEAKS_C7)
107 MHSYNC0(PEAKS_H)
106 MVSYNC0(PEAKS_V)
109 MVCLK0(PAEKS_CLK)
20 VOUTENB
DC(BS_C)
47
45 DY(BS_Y)
23 SRQ
FORMAT
24
EDGE