LG lg530g Service Manual page 39

3.5.6 Internal base band functions
3.5.6 Internal base band functions
Several baseband circuits within the QSC6270 device provide functions that are necessary only to
make the device operate properly — these functions are not generally used directly by other
handset circuits and functions.
PLLs and clock generation
Modes and resets
Security
Qfuse
JTAG/ETM
The clock block includes two PLLs, all phase-locked to the TCXO signal. These PLLs generate several
different stable, low-jitter clock signals that are distributed throughout the QSC device and to external
components as needed.
All the required WCDMA, GSM, GPS(only QSC6270), ARM, QDSP, and most peripheral clocks are derived in
some way from the TCXO (or XO) source for their operating modes, plus the 32.768 kHz
oscillator for their sleep modes
External clocks
TCXO
SLEEP_CLK
LGE Internal Use Only
PLL0
PLL1
Clocks block
Figure 3.5.6 Clock block basic architecture of QSC6270
Figure 3.5.6 Clock block basic architecture of QSC6270
Clock
source
select
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3. TECHNICAL BRIEF
Clock
generators
Only for training and service purposes
LG530G