Philips VAE8015 Service Manual page 42

EN 42 9. VAE8015 / 8020
reads three analogue signals (A1, A2 and CALF), representing
Max, Min, and Average values of the EFM signal respectively.
It also takes the Power (PW) signal from the laser controller
and then feeds an analogue signal (ALPHA0) out to control the
laser power. The conversion frequency is 88KHz per channel.
Basically, the OPC procedure tries to find out the optimum
laser power to be used on a specific disc. It consists of three
phases:
1. WRITE - Random EFM data is written to the test area of the
disc at increasing levels of laser power (controlled by
ALPHA0).
2. READ - The data on A1, A2, and CALF is read back from
the test area and stored in memory.
3. CALCULATION - the embedded 8051 then calculates the
setting of ALPHA0 where the least jitter is encountered.
Some pre-processing is carried out by the OPC logic to
reduce the processor's load.
This sequence is done twice - first a coarse calibration,
followed by a fine-tuning.
The microprocessor
MACE3
OPU64
2
I C
LADIC
DROPPI
EEPROM
Figure 9-5 Control path
The micro controller processes the S2B commands from the
DVD+RW interface (back-end), and controls the various
processes in the OPU via I2C. Communication with the
HDR65, SPIDRE, and memories is done via an eight bit
parallel bus.
Some features:
• Dedicated hardwired DSP.
• 8051-based microprocessor.
• External Flash ROM and SRAM memory.
9.5.3 HDR65
The HDR65 has the following functions:
• Encoder for DVD+RW. This part creates the EFM+ (16 bit)
signals from the I2S data stream.
• Decoder for DVD and CD. This part processes the HF-
signal from the SPIDRE. It converts the EFM(+) signals to
data, and performs error detection and error correction.
• Output to SPIDRE pre-processor for RF-AGC.
This IC decodes EFM or EFM+HF signals directly from the
laser pre-amplifier, including analogue front-end, PLL data
recovery, demodulation, and error correction.
The analogue front-end input converts the HF input to the
digital domain via an 8-bit ADC, preceded by an AGC circuit to
obtain the optimum performance from the converter. An
external resonator clocks this block. This subsystem recovers
the data from the channel stream. It corrects asymmetry,
performs noise filtering and equalisation, and finally recovers
the bit clock and data from the channel using a digital PLL.
Circuit Descriptions, Abbreviation List, and Data Sheets
S2B
to
Datapath
(5 lines)
8-bit parallel bus
Flash
ROM
HDR65
multi
fast serial bus
bus
AWESOME
fast serial bus
SPIDRE
CL 26532126_001.eps
081102
The demodulator part detects the frame synchronisation
signals and decodes the EFM (14 bit) and EFM+ (16 bit) data
and sub-code words into 8-bit symbols. Via the serial output
interface, the I2S data (audio and video) go to the DVD+RW
interface (back-end).
The spindle-motor interface provides both motor control signals
from the demodulator and, in addition, contains a tachometer
loop that accepts tachometer pulses from the motor unit. They
drive the motor IC (item 7301).
The SAA7831 has two independent microcontroller interfaces.
The first is a serial I2C-bus and the second is a standard 8-bit
multiplexed parallel interface. Both of these interfaces provide
access to 32 8-bit registers for control and status.
Some HDR65 features:
• Playback speeds up to 48 x CD and 8 x DVD; recording up
to 8 x CD and 4 x DVD
• Matched filter with digital equalizer, noise filter, and digital
PLL.
• EFM and EFM+ modulator and demodulator.
• Decoding, de-interleaving, and error correction according
to CD and DVD standards.
• Wobble processing for DVD-R(W) and CD.
• Motor control for CAV and CLV regulation on both recorded
and unrecorded discs.
• Automated encode start/stop mechanism, supporting bit-
accurate linking (only DVD).
• Write data/clock interface compatible with LADIC.
• Versatile serial input/output interface for different formats.
• 8 bit parallel data input/output interface.
9.5.4 AWESOME
The AWESOME gate array chip (uPD65882, item 7401) is a
fully digital DVD+RW add-on for the HDR65. A combination of
both ICs can do CD and DVD decoding and CD, DVD-R(W),
and DVD+RW encoding. It contains logic for:
• Wobble processing:
– Address detection,
– Write clock generation,
– Start and stop.
• ADIP decoding.
• Spindle motor control to do CLV on wobble.
• Link bits insertion (according to DVD+RW standard).
• Output to SPIDRE pre-processor for wobble-AGC
It also contains multiplexing logic for the motor signals and a
merge of the internal serial bus to the analogue pre-processor
(SPIDRE) with the serial bus of the HDR65.
Note: AWESOME stands for: Adip decoding, Wobble
processing, Error correction, Synchronous start/stop and
Occasionally Mend Errors.
Wobble
(Re)Writable Disk
Figure 9-6 Pre-groove wobble on (re)writable discs
empty
land
track
wobbled
pregroove
written
track
mark
(data)
laser
beam
CL 26532126_020.eps
251102