Main Logic Board (Parallel Interface); Circuit Diagram - Star Micronics SP500 Series Technical Manual

5.

Main Logic Board (Parallel Interface)

5-1. Circuit Diagram

Release Voltage
Delay time
Operating temperature
Built-in RAM
Operating temperature
OC
OC
OC
OC
D OC
D OC
D OC
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
CC CC
SS SS
CC CC
SS SS
CC CC
SS SS
SS SS
SS SS
CC CC
SS SS OC
SS SS OC
OC
OC
OC
OC
CS CS OC
OC
CS CS
CS CS
– 37 –
line
line
Operating temperature
O
O
O
O
O
O
O
O
O
O
O
O
O
O
D
D
D
D
D
D
D
D
O
O
O
O
O O
O
O
OD D
OD D
OD D
DD DD
OD D
DD DD
OD D
DD DD
OD D
SS SS
OD D
SS SS
OD D
SS SS
OD D
OD D
DD DD
DD DD S
DD DD S
SS SS OD S
SS SS S
SS SS S
D
S
D
DD DD S
D
DD DD
D
SS SS S
SS SS S
D
SS SS OD S
D
S
SS SS
D
S
D
DD DD S
S
SS SS
SS SS
SS SS
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
OD O
OD O
OD O
OD O
OD O
OD O
OD O
OD O
OD
D OD
OD
OD
Main Logic Board (Parallel Interface) 1/ 4
O
O
O
O
O
O
O
O
O
O
O
D
D
D
D
D
D
D
D
D
D
D
D
D
OD & Protection Timer
D
D
D
D
D
D
D
D
D
Protection Timer
Protection Timer
C
C
C
C
C
C
C
Protection Timer
C
C
C D
C D
& Protection Timer
OD & Protection Timer
D
D
OD
D
D
D
D