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8.2 ANALOG OUTPUT
D/A type
Resolution
Number of channels
Output Ranges
D/A pacing
Data transfer
Offset error
Gain error
Differential nonlinearity
Integral nonlinearity
Monotonicity
D/A Gain drift
D/A Bipolar offset drift
D/A Unipolar offset drift
Throughput
Settling time (to .01% of 10V step)
Slew Rate
Current Drive
Output short-circuit duration
Output Coupling
Amp Output Impedance
Miscellaneous
8.3 PARAELLEL DIGITAL INPUT/OUTPUT
Digital Type
Configuration
Number of channels
Output High
Output Low
Input High
Input Low
Power-up / reset state
Interrupts
Interrupt enable
Interrupt sources
AD7847AR
12 bits
2
±10V, ±5V, 0-5V, 0-10V. Each channel independently programmable.
Software
Programmed I/O.
±600µV max, all ranges (calibrated)
±0.02% FSR max (calibrated)
±1LSB max
±1LSB max
12 bits
±2 ppm/°C max
±5 ppm/°C max
±5 ppm/°C max
PC dependent
4µs typ
7V/µS
±5 mA min
25 mA indefinite
DC
0.1 Ohms max
Power up and reset, all DAC's cleared to 0 volts, ±200mV
82C55A
2 banks of 8, 2 banks of 4, programmable by bank as input or output
24 I/O
3.0 volts @ -2.5mA min
0.4volts @ 2.5 mA max
2.0 volts min, Vcc+0.5 volts absolute max
0.8 volts max, GND-0.5 volts absolute min
Input mode (high impedance)
INTA# - mapped to IRQn via PCI BIOS at boot-time
Programmable
Residual counter, End-of-channel-scan, AD-FIFO-not-empty,
AD-FIFO-half-full
33
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