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INT[1:0]
General Interrupt Source selection bits.
INTE
Enables interrupt source selected via the INT[1:0] bits.
1 = Selected interrupt Enabled
0 = Selected interrupt Disabled
EOAIE
Enables End-of-Acquisition interrupt. Used during FIFO'd ADC operations to indicate that the desired
sample size has been gathered.
1= Enable EOA interrupt
0 = Disable EOA interrupt
EOACL
A write-clear to reset EOA interrupt status.
1 = Clear EOA interrupt.
0 = No effect.
INTCL
A write-clear to reset INT[1:0] selected interrupt status.
1 = Clear INT[1:0] interrupt
0 = No effect.
ADFLCL
A write-clear to reset latched ADC FIFO Full status.
1 = Clear ADC FIFO Full latch.
0 = No Effect.
NOTE: It is not necessary to reset any write-clear bits after they are set.
READ
15
14
13
-
-
LADFUL
Read operations to this register allow the user to check status of the selected interrupts and ADC FIFO flags. The following
is a description of Interrupt / ADC FIFO Register Read bits:
EOAI
Status bit of ADC FIFO End-of-Acquisition interrupt
1 = Indicates an EOA interrupt has been latched.
0 = Indicates an EOA interrupt has not occurred.
INT
Status bit of General interrupt selected via INT[1:0] bits. This bit indicates that any one of
these interrupts has occurred.
1 = Indicates a General interrupt has been latched.
0 = Indicates a General interrupt has not occurred.
EOBI
Status bit ADC End-of-Burst interrupt. Only valid for ADC Burst Mode enabled.
1 = Indicates an EOB interrupt has been latched.
0 = Indicates an EOB interrupt has not occurred.
INT1
INT0
0
0
0
1
1
0
1
1
12
11
10
9
ADNE
ADNEI
ADHFI
EOBI
Source
Not Defined
End of Channel Scan
AD FIFO Half Full
AD FIFO Not Empty
8
7
6
5
-
INT
EOAI
-
18
4
3
2
1
-
-
-
-
0
-
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