Table of Contents
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Tables of Contents
1.
Introduction_________________________________________________________ 4
1.1
General Description __________________________________________________ 4
1.2
Features _____________________________________________________________ 4
1.3
Specifications _________________________________________________________ 5
1.3.1
Power Consumption : ________________________________________________________ 5
1.3.2
Analog Inputs ______________________________________________________________ 5
1.3.3
A/D Converter _____________________________________________________________ 5
1.3.4
DA Converter ______________________________________________________________ 6
1.3.5
Digital I/O_________________________________________________________________ 6
1.3.6
Interrupt Channel ___________________________________________________________ 6
1.3.7
Programmable Timer/Counter _________________________________________________ 7
1.3.8
Direct Memory Access Channel (DMA) _________________________________________ 7
1.4
Applications __________________________________________________________ 8
1.5
Product Check List ____________________________________________________ 8
2.
Hardware Configuration ______________________________________________ 9
2.1
Board Layout_________________________________________________________ 9
2.2
I/O Base Address Setting ______________________________________________ 10
2.3
Jumper Settings______________________________________________________ 11
2.3.1
JP1 : D/A Internal Reference Voltage Selection___________________________________ 11
2.3.2
JP2 : D/A Int/Ext Ref Voltage Selection ________________________________________ 12
2.3.3
JP3 : Single-ended/Differential Selection________________________________________ 12
2.3.4
JP4 : A/D Trigger Source Selection ____________________________________________ 13
2.3.5
JP5 : Interrupt Level Selection ________________________________________________ 13
2.3.6
JP6 : User Timer/Counter Clock Input Selection __________________________________ 14
2.3.7
2.4
I/O Register Address__________________________________________________ 16
2.4.1
8254 Counter _____________________________________________________________ 17
2.4.2
A/D Input Buffer Register ___________________________________________________ 17
2.4.3
D/A Output Latch Register ___________________________________________________ 18
2.4.4
D/I Input Buffer Register ____________________________________________________ 19
2.4.5
Clear Interrupt Request______________________________________________________ 19
2.4.6
A/D Gain Control Register ___________________________________________________ 20
2.4.7
A/D Multiplex Control Register _______________________________________________ 21
2.4.8
A/D Mode Control Register __________________________________________________ 22
JP8 : DMA DRQ Selection _____________________ 15
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