Philips ACT-300 Service Manual page 14

70 CVSS7 GND
71 BCLKX1 DSP ↔
72 DVSS4 GND
73 BFSX1 DSP →
74 BDX1 DSP → servo driver
75 DVDD4 +3.3V
76 DVSS5 GND
77 CLKMD1 → DSP
78 CLKMD2 → DSP
79 CLKMD3 → DSP
80 HPI16 → DSP
81 HD2 DSP ↔ CD10
82 TOUT DSP →
83 EMU0 DSP ↔
84 EMU1/OFF DSP ↔
85 TDO DSP →
86 TDI → DSP
87 TRST → DSP
88 TCK → DSP
89 TMS → DSP
90 CVSS8 GND
91 CVDD5 +core
92 HPIENA → DSP
93 DVSS6 GND
94 CLKOUT DSP → DRAM/FLASH
95 HD3 DSP ↔ CD10
96 X1 DSP →
97 X2/CLKIN CD10 → DSP
98 RS µP → DSP
99 D0 DSP ↔ DRAM/FLASH
100 D1 DSP ↔ DRAM/FLASH
101 D2 DSP ↔ DRAM/FLASH
102 D3 DSP ↔ DRAM/FLASH
103 D4 DSP ↔ DRAM/FLASH
104 D5 DSP ↔ DRAM/FLASH
105 A16 DSP ↔ DRAM/FLASH
106 DVSS7 GND
107 A17 DSP ↔ DRAM/FLASH
108 A18 DSP ↔ DRAM/FLASH
109 A19 DSP ↔ DRAM/FLASH
110 A20 DSP ↔ DRAM/FLASH
111 CVSS9 GND
112 DVDD5 +3.3V
113 D6 DSP ↔ DRAM/FLASH
114 D7 DSP ↔ DRAM/FLASH
115 D8 DSP ↔ DRAM/FLASH
116 D9 DSP ↔ DRAM/FLASH
117 D10 DSP ↔ DRAM/FLASH
118 D11 DSP ↔ DRAM/FLASH
119 D12 DSP ↔ DRAM/FLASH
120 HD4 DSP → servo driver
121 D13 DSP ↔ DRAM/FLASH
122 D14 DSP ↔ DRAM/FLASH
123 D15 DSP ↔ DRAM/FLASH
124 HD5 DSP ↔
125 CVDD6 +core
126 CVSS10 GND
127 HDS1 → DSP
128 DVSS8 GND
129 HDS1 → DSP
130 DVDD6 +3.3V
131 A0 DSP ↔ DRAM/FLASH
132 A1 DSP ↔ DRAM/FLASH
133 A2 DSP ↔ DRAM/FLASH
134 A3 DSP ↔ DRAM/FLASH
135 HD6 DSP ↔
136 A4 DSP ↔ DRAM/FLASH
137 A5 DSP ↔ DRAM/FLASH
138 A6 DSP ↔ DRAM/FLASH
139 A7 DSP ↔ DRAM/FLASH
140 A8 DSP ↔ DRAM/FLASH
141 A9 DSP ↔ DRAM/FLASH
142 CVDD7 +core
143 A21 DSP ↔ DRAM/FLASH
144 DVSS9 GND
3-4
ground for core CPU
transmit clock
ground for I/O pins
frame synchronization pulse for transmit input/output
serial data transmit output
power supply for I/O pins
ground for I/O pins
clock mode select signal input, allow selection of different clock modes
clock mode select signal input, allow selection of different clock modes
clock mode select signal input, allow selection of different clock modes
HPI16 mode selection
parallel bidirectional data bus
timer output, signals a pulse when the on-chip timer counts down past zero
emulator 0 pin
emulator 1 pin / disable all outputs, used as an interrupt to or from the
emulator system
IEEE standard 1149.1 test data output
IEEE standard 1149.1 test data input
IEEE standard 1149.1 test reset
IEEE standard 1149.1 test clock
IEEE standard 1149.1 test mode select
ground for core CPU
power supply for core CPU
HPI module select
ground for I/O pins
clock output signal
parallel bidirectional data bus
output pin from an internal oscillator for the crystal
clock/oscillator input
reset input
parallel data bus
parallel data bus
parallel data bus
parallel data bus
parallel data bus
parallel data bus
parallel address bus
ground for I/O pins
parallel address bus
parallel address bus
parallel address bus
parallel address bus
ground for core CPU
power supply for I/O pins
parallel data bus
parallel data bus
parallel data bus
parallel data bus
parallel data bus
parallel data bus
parallel data bus
parallel bidirectional data bus
parallel data bus
parallel data bus
parallel data bus
parallel bidirectional data bus
power supply for core CPU
ground for I/O pins
data strobe input
ground for I/O pins
data strobe input
power supply for I/O pins
parallel address bus
parallel address bus
parallel address bus
parallel address bus
parallel bidirectional data bus
parallel address bus
parallel address bus
parallel address bus
parallel address bus
parallel address bus
parallel address bus
power supply for core CPU
parallel address bus
ground for I/O pins