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TMS320DA150PGE160 – DIGITAL SIGNAL PROCESSOR DSP
Pin
Name
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
1
CVSS1
2
A22
3
CVSS2
4
DVDD1
5
A10
6
HD7
7
A11
8
A12
9
A13
10
A14
11
A15
12
CVDD1
13
HAS
14
DVSS1
15
CVSS3
16
CVDD2
17
HCS
18
HR/W
19
READY
20
PS
21
DS
22
IS
23
R/W
24
MSTRB
25
IOSTRB
26
MSC
27
XF
28
HOLDA
29
IAQ
30
HOLD
31
BIO
32
MP/MC
33
DVDD2
34
CVSS4
35
BDR1
36
BFSR1
37
CVSS5
38
BCLKR1
39
HCNTL0
40
DVSS2
41
BCLKR0
42
BCLKR2
43
BFSR0
44
BFSR2
45
BDR0
46
HCNTL1
47
BDR2
48
BCLKX0
49
BCLKX2
50
CVSS6
51
HINT
52
CVDD3
53
BFSX0
54
BFSX2
55
HRDY
56
DVDD3
57
DVSS3
58
HD0
59
BDX0
60
BDX2
61
IACK
62
HBIL
63
NMI
64
INT0
65
INT1
66
INT2
67
INT3
68
CVDD4
69
HD1
Direction
GND
DSP ↔
GND
+3.3V
DSP ↔
CD10 → MUTE
DSP ↔
DSP ↔
DSP ↔
DSP ↔
DSP ↔
+core
→ DSP
GND
GND
+core
→ DSP
→ DSP
→ DSP
DSP → EPROM
DSP →
DSP →
DSP → DRAM
DSP →
DSP →
DSP →
DSP → CD10
DSP →
DSP →
→ DSP
→ DSP
→ DSP
+3.3V
GND
CD10 →
CD10 → DSP
GND
→ DSP
→ DSP
GND
CD10 → DSP
µP → DSP
CD10 → DSP
CD10 → DSP
CD10 → DSP
→ DSP
µP → DSP
DSP → CD10
µP → CD10
GND
DSP →
+core
DSP → CD10
µP → DSP
DSP →
+3.3V
GND
DSP ↔ CD10
DSP → CD10
DSP → µP
DSP →
→ DSP
→ DSP
CD10 → DSP
CD10 → DSP
CD10 → DSP
µP → DSP
+core
DSP ↔ CD10
3-3
Description
ground for core CPU
parallel address bus
ground for core CPU
power supply for I/O pins
parallel address bus
reference current output pin
parallel address bus
parallel address bus
parallel address bus
parallel address bus
parallel address bus
power supply for core CPU
address strobe input
ground for I/O pins
ground for core CPU
power supply for core CPU
chip select input
read/write input
data ready input, indicates that an external device is prepared for a bus
transaction to be completed
program space select output, always high unless driven low for
communicating to a particular external space
data space select output, always high unless driven low for communicating
to a particular external space
I/O space select output, always high unless driven low for communicating to
a particular external space
read/write signal output, indicates transfer direction during communication to
an external device
memory strobe signal output
I/O strobe signal output
microstate complete output, indicates completion of all software wait states
external flag output, latched software programmable signal
Hold acknowledge, indicates that the processor is in a hold state
instruction acquisition signal output
hold input, asserted to request control of address, data and control lines
branch control input
microprocessor/microcomputer mode select
power supply for I/O pins
ground for core CPU
serial data receive input
frame synchronization pulse for receive input
ground for core CPU
serial shift clock
control input
ground for I/O pins
serial shift clock
serial shift clock
frame synchronization pulse for receive input
frame synchronization pulse for receive input
serial data receive input
control input
serial data receive input
transmit clock
transmit clock
ground for core CPU
interrupt output, used to interrupt the host
power supply for core CPU
frame synchronization pulse for transmit input/output
frame synchronization pulse for transmit input/output
ready output, informs the host when the HPI is ready for the next transfer
power supply for I/O pins
ground for I/O pins
parallel bidirectional data bus
serial data transmit output
serial data transmit output
interrupt acknowledge signal output
byte identification, identifies the first or second byte of transfer
nonmaskable interrupt input
external user interrupt input
external user interrupt input
external user interrupt input
external user interrupt input
power supply for core CPU
parallel bidirectional data bus
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