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SAA7324 – DECODER, DIGITAL SERVO IC AND D/A-CONVERTER CD10 (low voltage version)
Pin
Name
Direction
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
1
HFREF
→ CD10
2
HFIN
→ CD10
3
ISLICE
CD10 →
4
VSSA1
GND
5
VDDA1
+2.6V
6
IREF
CD10 →
7
VRIN
CD10 →
8
D1
CD-drive → CD10
9
D2
CD-drive → CD10
10
D3
CD-drive → CD10
11
D4
CD-drive → CD10
12
R1
CD-drive → CD10
13
R2
CD-drive → CD10
14
VSSA2
GND
15
CROUT
CD10 → X-TAL
16
CRIN
X-TAL → CD10
17
VDDA2
+2.6V
18
LN
CD10 →
19
LP
CD10 →
20
VNEG
GND
21
VPOS
+2.6V
22
RN
CD10 →
23
RP
CD10 →
24
SELPLL
CD10 →
25
TEST1
GND
26
CL16
CD10 →
27
DATA
CD10 → DSP
28
WCLK
CD10 → DSP
29
SCLK
CD10 → DSP
30
EF
CD10 → DSP
31
TEST2
GND
32
KILL
CD10 →
33
VSSD1
GND
34
V2/V3
CD10 →
35
WCLI
DSP → CD10
36
SDI
DSP → CD10
37
SCLI
DSP → CD10
38
RESETn
µP → CD10
39
SDA
µP ↔ CD10
40
SCL
µP → CD10
41
RAB
µP → CD10
42
SILD
µP → CD10
43
STATUS
CD10 →
44
TEST3
GND
45
RCK
DSP → CD10
46
SUB
CD10 → DSP
47
SFSY
CD10 → DSP
48
SBSY
CD10 → DSP
49
CL11/4
CD10 →
50
VSSD2
GND
51
DOBM
CD10 →
52
VDDD1P
+2.6V (+VR)
53
CFLG
CD10 →
54
RA
CD10 → servo driver
55
FO
CD10 → servo driver
56
SL
CD10 → servo driver
57
VDDD2C
+2.6V
58
VSSD3
GND
59
MOTO1
CD10 → servo driver
60
MOTO2
CD10 →
61
V4
CD10 → HF-preamp
62
V5
CD10 → HF-preamp
63
V1
innerswitch → CD10
64
LDON
CD10 → HF-preamp
3-2
Description
comparator common mode input
comparator signal input
current feedback from data slicer
analog ground 1
analog supply voltage 1
reference current output pin
reference voltage for servo ADC's
unipolar current input (central diode signal input)
unipolar current input (central diode signal input)
unipolar current input (central diode signal input)
unipolar current input (central diode signal input)
unipolar current input (satellite diode signal input)
unipolar current input (satellite diode signal input)
analog ground 2
crystal/resonator output
crystal/resonator input
analog supply voltage 2
DAC left channel differential output - negative
DAC left channel differential output - positive
DAC negative reference input
DAC positive reference input
DAC right channel differential output - negative
DAC right channel differential output - positive
selects whether internal clock multiplier PLL is used
test control input 1; this pin should be tied low
16.9344 MHz system clock output
serial data output (3-state)
word clock output (3-state)
serial bit clock output (3-state)
C2 error flag output (3-state)
test control input 2; this pin should be tied low
kill output (programmable; open-drain)
digital ground 2
versatile I/O: input versatile pin 2 or output versatile pin 3 (open-drain)
word clock input (for data loopback to DAC)
serial data input (for data loopback to DAC)
serial bit clock input (for data loopback to DAC)
power-on reset input (active low)
microcontroller interface data I/O line (open-drain output)
microcontroller interface clock line input
microcontroller interface R/W and load control line input (4-wire bus mode)
microcontroller interface R/W and load control line input (4-wire bus mode)
servo interrupt request line/decoder status register output (open-drain)
test control input 3; this pin should be tied low
subcode clock input
P-to-W subcode bits output (3-state)
subcode frame sync output (3-state)
subcode block sync output (3-state)
11.2896 MHz or 4.2336 MHz (for microcontroller) clock output
digital ground 3
bi-phase mark output (externally buffered; 3-state)
digital supply voltage 2 for periphery
correction flag output (open-drain)
radial actuator output
focus actuator output
slide control output
digital supply voltage 3 for core
digital ground 4
motor output 1; versatile (3-state)
motor output 2; versatile (3-state)
versatile output pin 4
versatile output pin 5
versatile input pin 1
laser drive on output (open-drain)
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