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Read Only Memory (ROM)
LAPD Data Link/Asynchronous Controller
Counter/Timer controller
Software interface circuit
DPNSS/DCHI Port
553-3011-100
Standard 14.00
NTAK93 D-channel handler interface
A total of 32K bytes of ROM space for each pair of ports is reserved as a code
section of the DCH-PORT firmware.
One chip controls each pair of independent communication ports. It performs
the functions of serial-to-parallel and parallel-to-serial conversions, error
detection, frame recognition (in HDLC) function. The parameters of these
functions are supplied by the DCH-PORT firmware.
Two chips are used as real-time timers and baud-rate generators for each pair
of communication ports.
This portion of the circuit handles address/data bus multiplexing, the
interchange of data, commands, and status between the on board processors
and software. It includes transmit buffer, receive buffer, command register,
and status register for each communication channel.
The mode of operation of the DCH-PORT is controlled by a switch setting on
the NTAK09/NTBK50. For DPNSS the switch is ON; for DCHI it is OFF.
The port will operate at:
Data Rate
Duplex
Clock
Interface
The address of ports is selected by hardwired backplane card address.
Port characteristics and LAPD parameters are downloaded from
software.
January 2002
56kbps, 64kbps
Full
Internal / External
RS422
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