Onkyo TX-8522 Service Manual page 35

IC BLOCK DIAGRAMS AND DESCRIPTIONS
AK4384(106dB 192kHz 24-Bit 2ch DAC )
P/S
SMUTE/CSN
µP
ACKS/CCLK
Interface
DIF0/CDTI
LRCK
Audio
Data
BICK
Interface
SDTI
PDN
No. Pin Name
1 MCLK
2 BICK
3 SDTI
4 LRCK
5 PDN
6 SMUTE
CSN
7 ACKS
CCLK
8 DIF0
CDTI
9 P/S
10 AOUTR
11 AOUTL
12 VCOM
13 VSS
14 VDD
15 DZFR
16 DZFL
MCLK
Clock
De-emphasis
Control Divider
8X
ATT
Modulator
Interpolator
8X
ATT
Interpolator Modulator
I/O Function
I Master Clock Input Pin
An external TTL clock should be input on this pin.
I Audio Serial Data Clock Pin
I Audio Serial Data Input Pin
I L/R Clock Pin
I Power -Down Mode Pin
When at " L" , the AK4384 is i n the power - down mode and is held in reset.
The AK4384 should always be reset upon power - up.
I Soft Mute Pin in parallel mode
" H" : Enable, " L" : Disable
I Chip Select Pin in serial mode
I Auto Setting Mode Pin in parallel mode
" L" : Manual Setting Mode, " H" : Auto Setting Mode
I Control Data Clock Pin in serial mode
I Audio Data Interface Format Pin in parallel mode
I Control Data Input Pin in serial mode
I
Parallel/Serial Select Pin
" L" : Serial control mode, " H" : Parallel control mode
O Rch Analog Output Pin
O Lch Analog Output Pin
O Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1mF c eramic capacitor in parallel with
a 10 m F electrolytic cap.
- Ground Pin
- Power Supply Pin
O Rch Data Zero Input Detect Pin
O Lch Data Zero Input Detect Pin
VDD
MCLK
VSS
BICK
VCOM
SDTI
DZFL
LRCK
DZFR
SCF
PDN
AOUTL
LPF
SMUTE/CSN
ACKS/CCLK
SCF
AOUTR
LPF
DIF0/CDTI
TX-8522
DZFL
1 16
2 15 DZFR
VDD
3 14
4 13 VSS
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View
5 12
VCOM
6 11 AOUTL
AOUTR
7 10
8 9 P/S
(Internal pull - up pin)