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IC BLOCK DIAGRAMS AND DESCIRPIONS
CS5333(24-Bit, 96 kHz Stereo A/D Converter)
Interface Power
Master Clock
MCLK
Serial Clock
SCLK
Serial Data Output
SDATA
Analog Power
Ground
Left Right Clock
LRCK
MCLK Divide
VA VL RST
AINL
S/H
AINR
S/H
TE
L 13942296513
TST
uPD4721GS (RS-232C Driver/ Receiver)
Block diagram
1
V
DD
C
2
1
V
3
CC
C
4
1
C
5
S
C
6
S
D
7
IN1
D
8
IN2
R
9
OUT1
R
10
OUT2
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VL
16
1
RST
15
2
VQ
14
3
AINL
13
4
AINR
VA
12
5
REF-GND
GND
11
6
FILT+
10
7
TST
DIV
9
8
DIF
LP Filter
Comparator
DAC
LP Filter
Comparator
DAC
GND
VQ
MCLK
Truth table
Driver
20
C
4
STBY
L
19
GND
H
18
C
4
H
17
V
SS
Receiver
STBY
16
STBY
L
15
V
CHA
H
300 ohm
14
D
OUT1
H
300 ohm
13
D
OUT2
3 V/5 V switching
V
CHA
12
R
IN1
5.5k ohm
L
11
R
IN2
H
5.5k ohm
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8
Reset
Quiescent Voltage
Left Channel Analog Input
Right Channel Analog Input
Reference Ground
Positive Voltage Reference
Test Input
Digital Interface Format
Digital Decimation
HPF
Filter
Digital Decimation
HPF
Filter
Q Q
3
6 7
1 3
FILT+
REF-GND
Remarks
D
D
IN
OUT
X
Z
Standby mode (DC/DC converter is stopped)
L
H
Space level output
H
L
Mark level output
R
Remarks
R
IN
OUT
X
H
Standby mode (DC/DC converter is stopped)
L
H
Space level input
H
L
Space level input
Operating mode
5 V mode (double step-up)
3 V mode (3 times step-up)
u163
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2 9
9 4
2 8
SDATA
LRCK
SCLK
1 5
0 5
8
2 9
9 4
DIV
DIF
m
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DTR-6.4
9 9
2 8
9 9
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