Yamaha dsp-ax3800 Service Manual page 76

RX-V3800/DSP-AX3800
No. Port Name
1 TXD4
2 CLK4
3 DA1
4 TB3in/DA0
5 SDA3/TXD3/TB2in
6 SCL3/RXD3/TB1in
7 TB0in
8 P146
9 P145
10 P144
11 P143
12 P142
13 P141
14 P140
15 BYTE
16 CNVss
17 P87
18 P86
19 RESET
20 Xout
21 Vss
22 Xin
23 Vcc
24 NMI
25 INT2
26 INT1
27 INT0
28 TA4in
29 P80
30 TA3in/P77
31 P76
32 TA2in
33 P74/TA2out
34 TA1in
35 P72/CLK2/TA1out
36 P71/RxD2/SCO2
37 P70/TXD2/SDA2
38 P67/TxD1
39 Vcc
40 P66/RxD1
41 Vss
42 P65/CLK1
43 P64/CTS1/RTS1/
44 P63/TxD0
45 P62/RxD0
46 P61/CLK0
47 P60/CTS0/RTS0
48 P137
49 P136
50 P135
51 P134
52 P57/RDY
53 P56/RAS
54 P55/HOLD
55 P54/HLDA
56 P133
57 Vss
58 P132
76
Function Name
I/O
(P.C.B.)
TXDH SO
CLKH SO
LIMIT DA
HDMINT TMR
TXDi SO
RXDi SI
/VSYNC TMR
RSELDT0 O
RSELCK0 O
ISELDT0 O
ISELCK0 O
/CSDAC2 O
/CSDAC1 O
/CSY O
BYTE MCU
CNVSS MCU
/ICD O
/ICTI I
/RES MCU
XOUT MCU
VSS MCU
XIN MCU
VCC MCU
NMI IRQ
REM1 IRQ
PDET IRQ
RXDR IRQ
iPDET TMR
/CSTI O
/ICXM O
(RDSCE) O
XMPWR O
/ITNTI TMR
/CSSIR O
/INTDIR TMR
/SPIRDY I
DRXM SI
DTXM SO
TXDR SO
VCC MCU
RXDR SI
VSS MCU
RTS SO
CTS I
TXDD (SDM) SO
RXDD (SDD) SI
CLKD (SCK) SO
DMT O
DIRSDO I
TUDA O
TUCK O
PLLR I
/TMUTE O
TUNED I
TUCE O
/ST I
CKZEV O
VSS MCU
DTZEV O
Detail of Function
Data transmission to VIDEO_CPU
Clock transmission to VIDEO_CPU
Limiter control output
HDMI MUTE input
iPod asynchronous serial data input
iPod asynchronous serial data output
Vertical sync pulse INT
Rec out SW1 control (ROHM) data (U, C, R, T, A, B, G, E, L models)
Rec out SW1 control (ROHM) clock (U, C, R, T, A, B, G, E, L models)
Rec out SW1 control (ROHM) data
Rec out SW1 control (ROHM) clock
Tl#1 initial clear
2sh DAC (PCM1791A) *6 chip enable
TI#1 chip enable
External data bus width change: 16bit
Processor mode select: Single chip mode
DIR initial clear
TI#1 SPI READY
Remote control pulse input 1
Power detect
RS232C • YDC signal reception detect
iPod detect
TI#0 (IC534 DSP P.C.B.) chip enable
DABIC IC reset (U model)
RDS enable (G model)
XM Radio power control (U, C models)
TI#0/#1 (DA70Y) interrupt
DIR chip enable
DIR interrupt
TI DA70Y serial ready / DIR WCK input (WCK input for CDDA writing)
DABIC IC RxD (XM data reception) (U, C models)
DABIC IC TxD (U, C models)
Usually RS-232C asynchronous communication data output / Data transmission terminal for AF220
Usually RS-232C asynchronous communication data input / Data reception terminal for AF220
Usually RS-232C asynchronous RTS output
Usually RS-232C asynchronous CTS input
Serial data output to DIR, TI, DAC
Serial data reception to DIR, TI, DAC
Serial clock output to DIR, TI, DAC
Digital full mute (Hi=Mute)
Usable for both CDDA write data input/XM LINK ACTIVE
PLL data output for tuner
PLL clock output for tuner
PLL reception for tuner
TUNER mute output
TUNER TUNED input
PLL chip select for TUNER
TUNER STEREO detect input
ZONE tone control IC serial transmission clock (U, C, R, T, K, A, B, G, E, L
models)
ZONE tone control IC serial transmission data (U, C, R, T, K, A, B, G, E, L models)