Samsung Geneva NP-R700 Series Service Manual page 161

4
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
C
P3.3V_MICOM
PRTC_BAT
R522
C544
1000nF
R521 20K 1%
C545
HDR-2P-SMD
1000nF
J506
B
R520 1K 1%
2
1
A
4
COM-22C-015(1996.6.5) REV. 3
3
CHP3_INTRUDER#
Y1
0.032768MHz
1 4
CHP3_LAN100_SLP
2 3
C180 C189
0.007nF 0.007nF
P1.5V
R194 33
AUD3_BCLK
R158 33
40-C4
MDC3_BCLK
R198
33
65-C1
AUD3_SYNC
R159 33
40-C4
MDC3_SYNC AUD3_RST#
65-C2
MDC3_RST#
P3.3V
AUD3_SDI0
MDC3_SDI1
R202
NO_STUFF
1K
MDC3_SDO
1M 1% 1%
CHP3_INTRUDER# AUD3_SDO
20-D3
P3.3V
CHP3_SATALED#
SAT1_RXN0
CHP3_RTCRST# SAT1_RXP0
20-D3
SAT1_TXN0
SAT1_TXP0
R523
NO_STUFF
1M
1%
For RTC Reset
SATA Cap. Place ment :
Distance b/w the ICH8-M & cap on the "P" signal should be identical
distance b/w the ICH8-M & cap on the "N" signal same pair.
3
U33-1
NH82801HBM
1 / 5
AG25
RTCX1
AF24
RTCX2
AF23
CHP3_RTCRST# RTCRST*
20-B4
AD22
INTRUDER*
20-B4 25-D3 AF25
CHP3_INTVRMEN INTVRMEN
AD21
25-D3
LAN100_SLP
B24
GLAN_CLK
D22
LAN_RSTSYNC
C21
LAN_RXD0
B21
LAN_RXD1
C22
LAN_RXD2
D21
LAN_TXD0
E20
LAN_TXD1
C20
LAN_TXD2
AH21
GLAN_DOCK*_GPIO13
D25
GLAN_COMPI
R269 24.9 1% C25
GLAN_COMPO
1608
AJ16
HDA_BIT_CLK
AJ15
HDA_SYNC
R196 33
TP19110
40-C4 R200 33 AE14
HDA_RST*
65-C2
AJ17
HDA_SDIN0
AH17
65-C2
HDA_SDIN1
65-C2 AH15
HDA_SDIN2
AD13
HDA_SDIN3
R205 33
40-C4 65-D2 R204 33 AE13
HDA_SDOUT
71-B3
AE10
HDA_DOCK_EN*_GPIO33
AG14
HDA_DOCK_RST*_GPIO34
AF10
SATALED*
63-B2
C987 4.7nF 25V AF6
SATA0RXN
63-B3 C988 4.7nF 25V AF5
SATA0RXP
C944
63-B3 4.7nF 25V AH5
SATA0TXN
C943 4.7nF 25V AH6
63-B3
SATA0TXP
63-B3
AG3
SATA1RXN
AG4
SATA1RXP
AJ4
SATA1TXN
AJ3
SATA1TXP
AF2
SATA2RXN
AF1
SATA2RXP
AE4
SATA2TXN
AE3
SATA2TXP
AB7
CLK1_SATA# SATA_CLKN
AC6
8-B1
CLK1_SATA SATA_CLKP
8-B1
TP19112
AG1
SATARBIAS*
AG2
SATARBIAS
R219
24.9
1% 1608
Place within 500 mils of ICH8-M
2
LPC3_LAD(3:0)
E5
0 51-C3 50-C2
FWH0_LAD0
F5 66-A3 65-C3
1
FWH1_LAD1
G8 2
FWH2_LAD2
F6
3
FWH3_LAD3
C4
FWH4_LFRAME* LPC3_LFRAME#
66-A3 65-C3 51-C3 50-C2
G9
LDRQ0* CHP3_LDRQ0#
E6
LDRQ1*_GPIO23 CHP3_LDRQ1#
AF13
A20GATE KBC3_A20G
AG26
51-B3 21-B3
A20M* CPU1_A20M#
10-C3
AF26
CPU1_DPRSTP#
DPRSTP*
AE26
60-C4 14-B1 11-D4
DPSLP* CPU1_DPSLP#
11-D4
AD24
FERR*
AG29
CPUPWRGD_GPIO49 CPU1_PWRGDCPU
11-C4
AF27
CPU1_IGNNE#
IGNNE*
10-C3
AE24
INIT* CPU1_INIT#
AC20 10-C3
INTR CPU1_INTR
AH14 10-B3
KBC3_CPURST#
RCIN*
51-B3 21-B3
AD23
NMI CPU1_NMI
AG28 10-B3
CPU1_SMI#
SMI*
10-B3
AA24
STPCLK* CPU1_STPCLK#
10-B3
R173
AE27 24.9 1%
THRMTRIP*
TP19114
AA23
TP8
IDE5_D(0:15)
V1 0 64-C4 64-C2
DD0
63-C3 63-B3
U2 1
DD1
V3 2
DD2
T1 3
Place 56 ohm resistor within 2" of ICH7-M
DD3
V4 4
DD4
Place PU resistor within 2" of 56ohm res.
T5 5
DD5
AB2 6
DD6
T6 7
DD7
T3 8
DD8
R2 9
DD9
T4 10
DD10
V6 11
DD11
V5 12
DD12
U1 13
DD13
V2 14
DD14
U6 15
DD15
AA4
DA0 IDE5_A0
AA1
64-C3 63-C3
DA1 IDE5_A1
AB3
64-C3 63-C3
DA2 IDE5_A2
64-C3 63-C3
Y6
DCS1* IDE5_CS1#
Y5
64-C3 63-C3
DCS3* IDE5_CS3#
64-C3 63-C3
W4
DIOR* IDE5_IOR#
W3
64-C3 63-C3
DIOW* IDE5_IOW#
Y2
64-C3 63-C3
DDACK* IDE5_DACK#
Y3 64-C3 63-C3 63-C3
IDEIRQ IDE5_IDEIRQ
21-B3
Y1 64-C3
IORDY IDE5_IORDY
W5
64-C3 63-C3
DDREQ IDE5_DREQ
64-C3 63-C3
DRAW DATE TITLE
SUN XIAO 6/26/2007
CHECK DEV. STEP
WUSHIJIANG PV2
APPROVAL REV
KEVIN LEE 1.0
MODULE CODE LAST EDIT
October 23, 2007 10:38:02 AM
2
1
D
VCCP_CORE
R178
56.2
1%
CPU1_FERR#
10-C3
VCCP_CORE
C
R176
56.2
1%
CPU1_THRMTRIP#
11-C4
14-B1
B
A
SAMSUNG
Gevena
ELECTRONICS
ICH8-M
PART NO.
ICH8-M (1/5)
BA41-XXXXX
20 58
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1
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