Samsung Geneva NP-R700 Series Service Manual page 148

4
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
P0.8V
FS(2:0)
CLK_3.3V_M
D
CLK3_PWRGD*
ITP_EN
CPU_STP*
Main PLL
SSC
C SS(96/100) SEL
PLL3
SSC
48MHz PLL
B
33 MHz
PCI_STP*
Buffer
14 MHz
A
OSC
14.318 MHz
2801-003730 Page 8
4
3
200 MHz CLK0_HOST_CPU/CPU*
EXP3_CLKREQ*
100 MHz
EXPRESS CARD
200 MHz CLK0_HOST_GMCH/GMCH*
100 MHz CLK1_PEG/PEG*
PCI Express Gfx
MCH3_CLKREQ*
100 MHz CLK1_MCH3GPLL/3GPLL*
CLK1_DREFCLK/CLK*
96 MHz
100 MHz
CLK1_DREFSSC/SSC*
Option For External GFX
CLK3_GFX_27M/SSC
100 MHz
100 MHz
100 MHz
100 MHz
CLK1_PCIEICH/ICH*
48 MHz CLK3_USB48
CHP3_SATACLKREQ*
100 MHz CLK1_SATA/SATA*
14.318 MHz CLK3_ICH14
33 MHz CLK3_PCLKICH
CLK3_SIO14
SIO
33 MHz CLK3_PCLKSIO
33 MHz CLK3_TPMLPC
TPM 1.2 32.768 KHz
33 MHz CLK3_PCLKMICOM
KBC
10 MHz
1394 Clock
33 MHz CLK3_PCLKCB
CARDBUS 24.576 MHz
2801-003898
33 MHz CLK3_PCLKMIN
MINI PCI
33 MHz CLK3_PCLKPORT80
PORT 80
3
2
CLOCK DISTRIBUTION
CPU BSEL
FSB
333/266/200 MHz
HPLL
333/266/200 MHz
MPLL
Crestline
333/266/200 MHz
PEG
GMCH
333/266/200 MHz
PCIE PLL
DPLLA
DPLLB
DMI
100 MHz
100 MHz PEX3_CLKREQ* (TBD)
100 MHz PEX3_CLKREQ* (TBD)
100 MHz PEX3_CLKREQ* (TBD)
PCIEPLL ICH8-M
USBPLL
SATAPLL
AUD3_BCLK
HD 24 MHz
32.768 KHz
OSC
MDC3_BCLK
17.86 MHz
RTC Clock
SPI3_CLK
32.768 KHz
2801-003856
LAN3_PHYCLK
LCI LAN
(Intel)
25 MHz
2801-003892
DRAW
CHECK
APPROVAL
MODULE CODE
2
667/533/400 MHz
CLK1_MCLK0/0*
SODIMM #0
CLK1_MCLK1/1*
CLK1_MCLK3/3*
SODIMM #1
CLK1_MCLK4/4*
CLK1_DCKLAN*
DCK LAN
CLK1_MINIPCIE/PCIE*
MINI PCIE CARD
CLK1_WIPCIE*
HDSPA
CLK1_NF*
ROBSON
100 MHz
LAN (3rd Vender)
HD Audio
MDC
SPI
DATE TITLE
SUN XIAO 6/26/2007
Gevena
DEV. STEP
WUSHIJIANG PV2
REV
CLOCK DIAGRAM
KEVIN LEE 1.0
LAST EDIT
October 23, 2007 10:38:02 AM
1
Rev. 0.8
D
C
B
A
SAMSUNG
ELECTRONICS
PART NO.
BA41-XXXXX
7 58
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