Pioneer VSX-55TXi Service Manual page 161

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5
QQ
Pin Function
3 7 63 1515 0
No.
Pin Name
1
12VTRIGGER
2
3
1394 RST
4
1394 CS
5
1394 DO
6
1394 DI
7
1394 CK
8
GND
9
CNVSS
10
11
12
XRESET
13
XOUT
14
GND
15
XIN
16
5V
17
NMI
18
WAKEUP
19
1394 INT
20
1W WUP
21
22
DISP EN
23
OSD RST
24
OSD CS
25
OSD CONT.
26
DISP RST
TE
L 13942296513
27
DISP RDY
28
OSD/DISP CLK
29
DISP DO
30
OSD/DISP DI
31
232C RXD
32
232C TXD
33
CLK
34
232C CTS
35
DSP DI
36
DSP DO
37
DSP CLK
38
DSP1 RST
39
DSP2 RST
40
DSP1 SS
41
DSP2 SS
42
DSP MODE1
43
DSP MODE2
44
DIR DI
45
DIR DO
46
DIR CS
47
DIR CK
48
DIR ERR
49
DIR RST
50
DECO MUTE
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6
I/O
O
"H" at ON
O
NC
"L" fixed.
O
Reset for 1394
O
Standby for 1394 (Not used)
O
DO for 1394
I
DI for 1394
O
CK for 1394
Ground
5.1kΩ pulldown
O
L" fixed
O
L" fixed
Reset
Oscillator
Ground
Oscillator
5V power supply
I
Cannot use it as usual input port
I
Wakeup
I
INT for 1394
I
Wakeup signal at standby (from the display microcomputer)
O
L" fixed
O
Communication enabling signal to the display microcomputer
O
OSD-IC reset signal
O
OSD-IC chip select signal
O
At data transfer to the OSD-IC: "H"
O
Display microcomputer reset signal
I
Communication enabling signal from the display microcomputer
O
Communication clock signal with the OSD-IC/display microcomputer
I
Communication data in signal with the display microcomputer (N ch open drain)
O
Communication data out signal with the OSD-IC/display microcomputer (N ch open drain: pullup)
O
For 232C rewriting (data output)
I
For 232C rewriting (data input)
O
Not used
O
For 232C rewriting (communication permission)
O
Communication data out signal with the DSP1 microcomputer
I
Communication data in signal with the DSP2 microcomputer
O
Communication clock signal with the DSP microcomputer
O
DSP1 microcomputer reset signal
O
DSP2 microcomputer reset signal
O
Slave select signal to DSP1 microcomputer
O
Slave select signal to DSP2 microcomputer
O
Mode selection of DSP1 microcomputer (ROM/RAM) H: ROM mode, L: RAM (PPP) mode
O
Mode selection of DSP2 microcomputer (ROM/RAM) H: ROM mode, L: RAM (PPP) mode
O
Communication data out signal with the DIR
I
Communication data in signal with the DIR/DAC
O
Communication chip select signal with the DIR/DAC
O
Communication clock signal with the DIR/DAC
I
Lock/Unlock signal
O
DIR reset signal
I
Boot success detecting port of 1st DSP
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2 9
8
Pin Function
"L" fixed.
(100kΩ pullup)
L: reset, H: release reset
L: reset, H: release reset (pulldown)
Q Q
3
6 7
1 3
1 5
L: reset, H: release reset
L: reset, H: release reset
co
.
VSX-55TXi
7
9 4
2 8
(pulldown)
0 5
8
2 9
9 4
2 8
m
7
8
9 9
Active
A
B
H
H
H
C
H
9 9
H
D
L
L
H
H
E
F
161
8

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