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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-27
Q2002 : AK4384 (192kHz 24-Bit 2ch DAC)
BLOCK DIAGRAM
P/S
SM UTE/CSN
ACKS/CCLK
Interface
DIF0/CDTI
LRCK
Audio
Data
BICK
Interface
SDTI
TERMINAL DESCRIPTION
No.
Pin Name
1
MCLK
TE
L 13942296513
2
BICK
3
SDTI
4
LRCK
5
PDN
6
SMUTE/
CSN
7
ACKS/
CCLK
8
DIF0/
CDTI
9
P/S
10
AOUTR
11
AOUTL
12
VCOM
13
VSS
14
VDD
www
15
DZFR
16
DZFL
.
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De-emphasis
µP
Control
8X
ATT
Interpolator
8X
ATT
Interpolator
PDN
I/O
Function
Master Clock Input Pin
I
An external TTL clock should be input on this pin.
I
Audio Serial Data Clock Pin
I
Audio Serial Data Input Pin
I
L/R Clock Pin
Power-Down Mode Pin
I
When at "L", the AK4384 is in the power-down mode and is held in reset.
The AK4384 should always be reset upon power-up.
I
Soft Mute Pin in parallel mode
"H": Enable, "L": Disable
Chip Select Pin in serial mode
I
I
Auto Setting Mode Pin in parallel mode
"L": Manual Setting Mode, "H": Auto Setting Mode
Control Data Clock Pin in serial mode
I
I
Audio Data Interface Format Pin in parallel mode
Control Data Input Pin in serial mode
I
I
Parallel/Serial Select Pin
"L": Serial control mode, "H": Parallel control mode
O
Rch Analog Output Pin
O
Lch Analog Output Pin
O
Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1mF ceramic capacitor in parallel with
a 10mF electrolytic cap.
-
Ground Pin
-
Power Supply Pin
O
Rch Data Zero Input Detect Pin
x
ao
y
O
Lch Data Zero Input Detect Pin
i
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8
MCLK
VDD
VSS
Clock
Divider
VCOM
DZFL
DZFR
SCF
AOUTL
Modulator
LPF
SCF
AOUTR
Modulator
LPF
Q Q
3
6 7
1 3
(Internal pull-up pin)
u163
.
TX-SR504/504E/8450
2 9
9 4
2 8
PIN CONFIGURATION
MCLK
1
BICK
2
SDTI
3
LRCK
4
Top
View
PDN
5
SMUTE/CSN
6
ACKS/CCLK
7
DIF0/CDTI
8
1 5
0 5
8
2 9
9 4
m
co
9 9
DZFL
16
DZFR
15
14
VDD
13
VSS
12
VCOM
11
AOUTL
10
AOUTR
P/S
9
2 8
9 9
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