Block Diagram - Md Section - Sony HCD-J300 Service Manual

HCD-J300
Q Q
BLOCK DIAGRAM – MD SECTION –
3 7 6 3 1 5 1 5 0
HR901
OVER WRITE HEAD
48
OPTICAL PICK-UP
(KMS-260B)
I
I
1
RF AMP
J J
2
VC 3 VC
D101
TEMP
F
SENSOR
B 15 TEMPR
C B
14 TEMPI
I J
D A
A A
4
B
5 I-V
C
E
AMP
6
D
DETECTOR
7
C
D
E E
T E 8
L 1 3 9 4 2 2 9 6 5 1 3 I-V
F
F
AMP
9
LD+3V
Q121, 122
ILCC APC
LD/PD
AUTOMATIC 11
AMP
POWER CONTROL
PD LD
LASER DIODE
Q101
PD PD
LASER ON 10
SWITCH
IC141
FOCUS/TRACKING COIL DRIVER,
SPINDLE/SLED MOTOR DRIVER
16
PSB
SPFD
6 OUT4F IN4R 3
M101
M M
SPRD
(SPINDLE)
OUT4R
8 IN4F 4
27 OUT2F IN2F 29
M102
M
(SLED)
25 OUT2R IN2R 30
2-AXIS
DEVICE
FCS+
21 OUT1F IN1F 19
23 OUT1R IN1R 18
w w w
FCS–
TRK+
12 OUT3F IN3F 14
TRK–
10 OUT3R IN3R 15
MOD
HF MODULE
IC181, Q181 182
OVER WRITE
HEAD DRIVE
SCTX
IC151 (1/2)
DIGITAL SIGNAL PROCESSOR,
EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER,
ATRAC ENCODER/DECODER
47 IC101
RF AMP,
FOCUS/TRACKING ERROR AMP
RFO AGCI RF AGC RF
46 40 38
& EQ
EQ
WBL
B.P.F.
AUX
33
3T PEAK
37
TEMP PEAK &
BOTM
BOTTOM
36
WBL
ADFM ADIN ADFG
AT
B.P.F. 29 30 32
AMP
ABCD
ABCD
35
AMP
FE
FOCUS
34
ERROR AMP
TE
26
TRACKING
SE
ERROR AMP
28
COMMAND
SERIAL/PARALLEL
V-I F0CNT
CONVERTER, 20
CONVERTER
DECODER
12 16 17 18
MD BACKUP
(3.3V)
83 10 13 67 65 66 75 74 63 64
RECP
XRST
AUTOMATIC
POWER
CONTROL
SFDR
92
ANALOG MUX
SRDR
91
A/D CONVERTER
DIGITAL SERVO
SIGNAL
FROM CPU
FFDR
PROCESS
88
INTERFACE
FRDR
89
XLRF XLAT
80
CKRF SCLK
AUTO
81
SEQUENCER DTRF SWDT
82
TFDR
x a o
86
IC151 (2/2)
TRDR
85
DIGITAL SERVO
SIGNAL PROCESSOR
. i
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15 68
TX VC
EFMO
100
FILI SAMPLING
60
PCO
CONVERTER
59
PLL
CLTV
62
FILO
61
DIGITAL
ASYO
53
INTERFACE
ASYI
54
COMPA-
RFI
RATOR
57
SUBCODE
PROCESSOR
ADIP
78 DEMODULATOR/
DECODER
CPU
INTERFACE
F0CNT
SPINDLE
79
SERVO
Q Q
3 7
94 93 12 11 14 9 8 5 6 7
Q333
MD RESET
SWITCH
25 27 32 48 40 38 42 50
IC308
RESET
5 3
19 RESET
29 LDON
47
DIG-RST
35 WRPWR
14 MOD
12 13
6 5
VCC 7
IC1004
LOADING
VREF
MOTOR DRIVE 4
VOLTAGE SWITCH
2 10
M
(LIMIT IN)
M103
(LOADING)
3 4
-A
IC102
u 1 6 3 WAVEFORM
y
Q131 - 134 SHAPPER
HF MODULE
LD+3.3V
SWITCH
44 44
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2 4
8 9 9
IC151 (1/2)
ADDT
25
DADTI
DADTI
22
RATE
XBCKI XBCKI
24
LRCKI LRCKI
23
DIN
DIN0
19
DIN1
AUDIO
20
DOUT
DOUT
21
DADT
26
XBCK
28
LRCK
27
FS256
29
X171
90MHz
OSCI
16
CLOCK
IC152
OSCO
GENERATOR
17
D-RAM
INTERNAL BUS
MONITOR
CONTROL
6 3 1 5 1 5 0 8 9
1 2 3 4 XOE
43 22 OE
XWE
47 4 WE
XRAS
46 5 RAS
XCAS
44 23 CAS
P.DOWN
58 56 26
SWITCH
22
XIN
X1001
10MHz
20
XOUT
118
IC1001 ADPWN
IC195
MASTER CONTROLLER
EEPROM
60 7 WP
EEP-WP
M+7V
66 6 SCL
SCL
61 5 SDA
SDA(EEP)
Q1001, 1002
REFERENCE
15
11 LD-LOW
S101
30
LIMIT-IN
Q1004
S103
(OUT)
51 MUTE
OUT-SW 8 SWITCH 12
MUTE
S104
(PLAY)
49 PLAY-SW SLICER-SEL
10 13
SLICERSEL
S105
9 1
(REC) DARST RESET
43 REC-SW
LOCK
116 21
DALOCK
S102 67
REFLECT
68 PROTECT
I2C-CLK
36
IOP I2CCLK
133
OP-LEVEL I2C-DATA
I2CDAT 37 m
SPDIF-CUT 123
+3.3V
c o
IC190
.
+3.3V
LD+3.3 V 3 1 +5V
REG
2
8 9 9
• Signal Path
: PLAY (MD)
: REC (MD)
: CD (DIGITAL)
: CD (ANALOG)
DIN
A
CD
SECTION
(Page 42)
2 4 9 8 2 9 9
MD RESET , P.DOWN , DA MUTE
B
MAIN
IC1005 SECTION
A/D (Page 43)
CONVERTER
13 11 12
Q1003
1
VINL REC-L
VINR 3 R-CH
7 PW ON
8
C
MAIN
SECTION
(Page 43)
16 33 37 29
MD-L
VOUTL 18
IC1006 VOUTR 22 R-CH
D/A
CONVERTER
VDDPLL 32
I2C-DATA,I2C-CLK
D
Q2001,2002
PANEL
+B
SECTION
SWITCH
(Page 45)