Block Diagram; Pin Configuration - Integra DTR-7.9 Service Manual

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -4
Q1324 : CS42516-CQZ (192 kHz, 6-Ch Codec with S/PDIF Receiver)

BLOCK DIAGRAM

RXP0
RXP1/GPO1
RXP2/GPO2
RXP3/GPO3
RXP4/GPO4
RXP5/GPO5
RXP6/GPO6
RXP7/GPO7
MUTEC
FILT+
VQ
REFGND
VA
AGND
AINL+
AINL-
AINR+
AINR-
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
TE AOUTB2-
L 13942296513
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-

PIN CONFIGURATION

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TXP VARX AGND LPFLT
Clock/Data
Rx
Recovery
GPO
MUTE
Ref
ADC#1
Digital Filter
ADC#2
Digital Filter
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
1
CX_SDIN1
CX_SCLK 2
CX_LRCK 3
VD 4
DGND 5
6
VLC
7
SCL/CCLK
8
SDA/CDOUT
9
AD1/CDIN
10
AD0/CS
11
INT
12
RST
13
AINR-
14
AINR+
15
AINL+
16
AINL-
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2 9
8
DGND DGND VD VD
C&U Bit
Data Buffer
S/PDIF
Decoder
Format
Detector
Internal MCLK
DEM
Gain & Clip ADC
Serial
Data
Gain & Clip
Q Q
3 6 7 1 3 1 5
48
47
46
45
44
43
42
CS42516
41
40
39
38
37
36
35
34
33
co
.
TX-SR806/SA806
9 4 2 8
INT
RST
Control
AD0/CS
Port
AD1/CDIN
SDA/CDOUT
SCL/CCLK
VLC
OMCK
Mult/Div RMCK
Serial
SAI_LRCK
Audio
SAI_SCLK
Interface
SAI_SDOUT
Port
VLS
ADCIN1
ADCIN2
CX_SDOUT
CX_LRCK
CX_SCLK
CX_SDIN1
CX_SDIN2
CX_SDIN3
0 5 8 2 9 9 4 2 8
RXP1/GPO1
RXP2/GPO2
RXP3/GPO3
RXP4/GPO4
RXP5/GPO5
RXP6/GPO6
RXP7/GPO7
VARX
AGND
LPFLT
MUTEC
AOUTA1-
AOUTA1+
AOUTB1+
m
AOUTB1-
AOUTA2-
9 9
9 9