Sony MDS-DRE1 Service Manual page 61

• DIGITAL BOARD IC701 DSP56004FJ66 (DSP)
Pin No. Pin Name
1 GNDA
2 MCS0
3 to 5 MA15 to MA13
6 VCCA
7 MA12
8 GNDA
9 VCCQ
10 GNDQ
11, 12 MA11, MA10
13, 14 MA09, MA08
15 GNDA
16 MA07
17 VCCA
MA06 to MA04
18 to 20
21 GNDA
22 to 25 MA03 to MA00
26 SCL
27 EXTAL
28 VCCQ
29 GNDQ
30 PINIT
31 GNDP
32 PCAP
33 VCCP
34 GNDS
35 SDA
36 RESET
37 MODA/IRQA
38 MODB/IRQB
39 MODC/NMI
40 VCCS
41, 42 HA0, HA2
43 HREQ
44 GNDS
45 SDO2
46 SDO1
47 SDO0
48 VCCS
49 SCKT
50 WST
51 SCKR
52 GNDQ
53 VCCQ
54 GNDS
55 WSR
56 SDI1
I/O
— Ground terminal (for EMI control output buffer)
O
Chip select signal output terminal Not used (open)
O
Address signal output terminal Not used (open)
—
Power supply terminal (+5V) (for EMI address output buffer and EMI control output buffer)
O Address signal output terminal Not used (open)
—
Ground terminal (for EMI address output buffer)
—
Power supply terminal (+5V) (for internal logic)
— Ground terminal (for internal logic)
O
Address signal output terminal Not used (open)
O
Address signal output to the D-RAM (IC702)
—
Ground terminal (for EMI address output buffer)
O Address signal output to the D-RAM (IC702)
—
Power supply terminal (+5V) (for EMI address output buffer and EMI control output buffer)
O
Address signal output to the D-RAM (IC702)
—
Ground terminal (for EMI address output buffer)
O
Address signal output to the D-RAM (IC702)
I
Serial clock signal input from the system controller (IC101)
I
System clock signal input terminal Bit clock signal input in this set
— Power supply terminal (+5V) (for internal logic)
—
Ground terminal (for internal logic)
I
PLL initialize terminal Not used (fixed at "L")
—
Ground terminal (for PLL system)
—
Connected to capacitor (for PLL filter)
—
Power supply terminal (+5V) (for PLL system)
—
Ground terminal (for SAI, SHI and ONCE output buffer)
I/O Two-way data bus with the system controller (IC101)
I
System reset signal input from the system controller (IC101) "L": reset
I
I
Mode selection terminal Fixed at "H" in this set
I
—
Power supply terminal (+5V) (for SAI, SHI and ONCE output buffer)
I
Not used (fixed at "L")
I
Not used (fixed at "H")
—
Ground terminal (for SAI, SHI and ONCE output buffer)
O
Enable control signal output to the shift register and latch (IC256, 257)
O
Serial data output to the shift register and latch (IC256, 257)
O Playback serial data output to the CXD8517Q (IC751)
—
Power supply terminal (+5V) (for SAI, SHI and ONCE output buffer)
O
Bit clock signal output to the CXD8517Q (IC751)
O
L/R sampling clock signal output to the CXD8517Q (IC751)
I
Bit clock signal input from the CXD2537R (IC601)
—
Ground terminal (for internal logic)
—
Power supply terminal (+5V) (for internal logic)
— Ground terminal (for SAI, SHI and ONCE output buffer)
I
L/R sampling clock signal input from the CXD2537R (IC601)
I
Serial data input from the system controller (IC101)
Function
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