Sony MDS-DRE1 Service Manual page 58

• DIGITAL BOARD IC101 M30610MC-TTX1057M (SYSTEM CONTROLLER)
Pin No. Pin Name
1, 2 TEST
3, 4 TEST
5 SQSY
6 —
7 PDOWN
8 BYTE
9 CNVSS
10 XCIN
11 XCOUT
12 RESET
13 XOUT
14 VSS
15 XIN
16 VCC
17 NMI
18
—
19 DQSY
20 INT-CDSP
21 F86-DEC
22 —
23
XINT-DEC
24
XINT-ENC
25
F86-ENC
26 to 30
—
31 SWDT
32 SRDT
33 SCLK
34 DTCS
35
DTOUT
36 DTIN
37 DTCK
38 PMCU-RET
39 XLAT-DEC
40 XLAT-ENC
41 RST-DSP
42 DEEMP-ADA
43 LAT-KEY
44 XWO-KEY
I/O
O Not used (pull up)
I
Not used (fixed at "H")
Subcode Q sync (SCOR) input from the CXD2535CR (IC121)
I
"L" is input every 13.3 msec Almost all, "H" is input
O Not used (pull up)
I Power down detection signal input terminal "L": power down, normally: "H"
I External data bus line byte selection signal input "L": 16 bit, "H": 8 bit (fixed at "L")
— Ground terminal
I Sub system clock input terminal (32.768 kHz) Not used (fixed at "H")
O Sub system clock output terminal (32.768 kHz) Not used (pull up)
System reset signal input from the reset signal generator (IC451) "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
O Main system clock output terminal (10 MHz)
— Ground terminal
I Main system clock input terminal (10 MHz)
— Power supply terminal (+5V)
I Non-maskable interrupt input terminal (fixed at "H" in this set)
O Not used (pull down)
Digital In U-bit CD format subcode Q sync (SCOR) input from the digital audio interface receiver
I
(IC401) "L" is input every 13.3 msec Almost all, "H" is input
I Not used (fixed at "L")
O Not used (pull down)
O Not used (pull down)
I Interrupt status input from the ATRAC decoder (IC601)
I Interrupt status input from the ATRAC encoder (IC501)
O Not used (pull down)
O Not used (pull down)
Writing data output to the CXA1981AR (IC101), CXD2535CR (IC121), digital audio interface
O receiver (IC401), sampling rate converter (IC451, 751), ATRAC encoder (IC501), ATRAC
decoder (IC601) and CXD2720Q (IC801)
Reading data input from the CXD2535CR (IC121), digital audio interface receiver (IC401),
I
ATRAC decoder (IC601) and CXD2720Q (IC801)
Serial data transfer clock signal output to the CXA1981AR (IC101), CXD2535CR (IC121),
O
digital audio interface receiver (IC401), sampling rate converter (IC451, 751), ATRAC encoder
(IC501), ATRAC decoder (IC601) and CXD2720Q (IC801)
O Chip select signal output to the fluorescent indicator tube drive controller (IC201)
O Serial data output to the fluorescent indicator tube drive controller (IC201)
I Serial data input from the fluorescent indicator tube drive controller (IC201)
O Serial data transfer clock signal output to the fluorescent indicator tube drive controller (IC201)
I CTS (clear to send) input from the fluorescent indicator tube drive controller (IC201)
Serial data latch pulse output to the CXA1981AR (IC101), CXD2535CR (IC121), digital audio
O
interface receiver (IC401), sampling rate converter (IC451, 751) and ATRAC decoder (IC601)
O Serial data latch pulse output to the ATRAC encoder (IC501)
O Reset signal output to the DSP (IC701) "L": reset
O Emphasis control signal output to the A/D, D/A converter (IC301)
O Serial data latch pulse output to the CXD2720Q (IC801)
O XWO output to the CXD2720Q (IC801)
Function
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