Sony MDS-DRE1 Service Manual page 54

Pin No. Pin Name
36 MCLK
37 XBCK
38 DVDD0
39 WDCK
40 RFCK
41 WFCK
42 GTOP
43 GFS
44 XPLCK
45 EFMO
46 RAOF
47 MVCI
48
TEST2
49 DIPD
50 DVSS1
51 DICV
52 DIFI
53 DIFO
54 AVDD1
55 ASYO
56 ASYI
57 BIAS
58 RFI
59 AVSS1
60 CLTV
61 PCO
62 FILI
63 FILO
64 PEAK
65 BOTM
66 ABCD
67 FE
68 AUX1
69 VC
70 ADIO
71
TEST3
72 AVDD2
73 ADRT
74 ADRB
75 AVSS2
76 SE
* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
I/O
O MCLK clock signal (22.5792 MHz) output terminal Not used (open)
Invert output of the BCK (pin #™) Not used (open)
O
— Power supply terminal (+5V) (digital system)
O Word clock signal (88.2 kHz) output terminal (MCLK system) Not used (open)
O Read frame clock signal (7.35 kHz) output terminal (MCLK system) Not used (open)
Write frame clock signal (7.35 kHz) output terminal (EFM decoder PLL system when playback
O
mode, EFM encoder PLL system when recording mode) Not used (open)
GTOP signal output terminal
O
Open the playback EFM sync protection window when "H" output Not used (open)
Guard frame sync signal output terminal The GFS signal becomes "H" when the playback EFM
O frame sync and interpolation protection timing match "L": NG, "H": OK
Not used (open)
EFM decoder PLL clock signal (98Fs=4.3218 MHz) output terminal
O PLL is made for XPLCK so that changes in the reversion and falling edge of the EFM PLL clock
and the EFM signal match Not used (open)
O EFM signal output terminal when recording mode
Internal RAM overflow detect signal output terminal (monitor output of decoder)
O
RAOF is a signal generated when the RAM exceeds the ±4 jitter margin Not used (open)
I
Oscillation input of the digital in PLL Not used (fixed at "L")
I Input terminal for the test (fixed at "L")
Phase comparison output of the digital in PLL
O (3)
Internal VCO (frequency: low → "H"), External VCO (frequency low → "L")
— Ground terminal (digital system)
I (A) Internal VCO control voltage input of the digital in PLL
I (A) Internal VCO filter input of the digital in PLL
O (A) Internal VCO filter output of the digital in PLL
— Power supply terminal (+5V) (analog system)
O Playback EFM full-swing output terminal ("L"=VSS, "H"=VDD)
I (A) Playback EFM asymmetry comparator voltage input terminal
I (A) Playback EFM asymmetry circuit constant current input terminal
I (A) Playback EFM RF signal input from the CXA1981AR (IC101)
— Ground terminal (analog system)
I (A) Internal VCO control voltage input for master clock of the decoder PLL
O (3) Phase comparison output for master clock of the decoder PLL
I (A) Filter input for master clock of the decoder PLL
O (3) Filter output for master clock of the decoder PLL
I (A) Light amount signal (RF/ABCD) peak hold input from the CXA1981AR (IC101)
I (A) Light amount signal (RF/ABCD) bottom hold input from the CXA1981AR (IC101)
I (A) Light amount signal (ABCD) input from the CXA1981AR (IC101)
I (A) Focus error signal input from the CXA1981AR (IC101)
I (A) Auxiliary signal (I signal/temperature signal) input from the CXA1981AR (IC101)
3
I (A) Middle point voltage (+2.5V) input from the CXA1981AR (IC101)
O (A) Monitor output of the A/D converter input signal Not used (open)
Input terminal for the test (fixed at "L")
I (A)
— Power supply terminal (+5V) (analog system)
I (A) A/D converter operational range upper limit voltage input terminal (fixed at "H" in this set)
I (A) A/D converter operational range lower limit voltage input terminal (fixed at "L" in this set)
— Ground terminal (analog system)
I (A) Sled error signal input from the CXA1981AR (IC101)
Function
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