Block Diagram - Main Section - Sony MXD-D4 Service Manual

MXD-D4
6-2. BLOCK DIAGRAM – MAIN Section –
ADDT
A
(Page 45)
DOUT
B
(Page 45)
DIN0
F
(Page 45)
LRCK, BCK
C
(Page 45)
CD BLOCK
(BU-21BD53)
OP ASSY (A-MAX. 2)
1 2 6 7 3 11 19 25 42 43 45 100 27 24
LEVEL L
LEVEL R
S1
(IN/OUT)
75 OUT SW
IIC DATA
OUT
77 IN SW IICCLK
IN
ON: When tray is
open/close.
XOUT
OUT1
IN1
7 3 74 LOAD NEG
M702 MOTOR
M M
(LOADING) OUT2 DRIVE IN2
2 6 73 LOAD POS
MD RST
LOADING MOTOR DRIVE
CD MECHANISM CONTROLLER
IC401
IC800 (1/2)
05
DATAO
13
WS
LRCK DIGITAL
12
INTERFACE
BCK
BCK
11
RESET
PWON
7
SWITCH
CLOCK
Q301
SCLK
CONTROL
8
CLKOUT
CLOCK AND
29
TIMING CIRCUIT
SPDIFO
15
CD/MD
SELECTOR
IEC 958
SPDIFI
IC307
16
DECODER
13
SLICER
SEL
1 RESET
21
123 9 10 116
94 3 LVL L
95 4 LVL R
37 36
30
29
13
X800
16MHz
XIN 15
26
VINL
1
DC- A/D
DECIMATION
CANCELLATION CONVERTER
FILTER
FILTER BLOCK
VINR
3
A/D CONVERTER
IC301
D/A CONVERTER
IC300
VOUTL
18
DATA D/A
IN/OUT CONVERTER
INTERFACE BLOCK
VOUTR
22
33 37 12
MUTING
Q300
D302 D300
8 26
SYSTEM CONTROLLER
(MD MECHANISM CONTROLLER)
IC801 (2/2)
D0 – D15 A1 – A19
122 – 119, 113 – 102 100 – 94, 92, 85 – 77, 75, 73 69 63 65 90
A0 – 18
29, 31, 33, 35, 38, 40, 42, 44,
25 – 18, 8 – 1, 48, 17, 16 26 28 11 14
30, 32, 34, 36, 39, 41, 43, 45
A0 – A18
DQ0 – DQ15
FLASH MEMORY
IC802
46 46
LINE
AMP
IC305
LINE LOW-PASS
HEADPHONE
AMP FILTER
AMP
IC100 (1/2), IC100 (2/2),
IC304
IC200 (1/2) IC200 (2/2)
MUTING MUTING
Q100, 200 Q101, 201
MUTING CONTROL
SWITCH
Q302
D303
117
RESET 19
RESET
SWITCH
20 22
Q501
X801
10MHz
J300
L
IN
R
ANALOG
L
OUT
R
RV301
PHONE
J301
LEVEL
PHONES
–1
–2
PDOWN
D
(Page 47)
RESET
E
(Page 47)
• SIGNAL PATH
: CD PLAY
: MD PLAY (ANALOG OUT)
: MD REC (ANALOG IN)