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5-2.
BLOCK DIAGRAM – MAIN Section (1/2) –
RF_AC
A
(Page 28)
D-RAM
IC706
WE
17
OE
33
RAS
18
UCAS
34
LCAS
35
D0 – D7
(Page 30)
I
DATA BUS
A0 – A7
J
(Page 30)
ADDRESS BUS
K
(Page 30)
D
(Page 28)
IC708(2/2)
5
MDP
7
IC708(1/2)
SPIN
1
2
E
(Page 28)
B
(Page 28)
IC703(1/2)
L
(Page 30)
3
1
JIT
+
–
2
APDO
M
(Page 30)
117
RFIN
MA0 – 9
XHWR
48
5
XHRD
49
4
BD0 – F
XHRQ
46
3
HDB8
26
2
76
XMWR
XHAC
53
94
XMOE
78
XRAS
95
XCAS
SACD DECODER
IC701
D0 – 7
A0 – 7
MA11
93
XRST_DVD
164
XRST
XHRD
17
XRD
XHWR
18
XWR
XCS1882
19
XCS
XINIT0
20
XINT0
XINIT1
XINT1
21
SCOR
150
SCOR
MDIN
137
MDIN2
SPO
135
GSCOR
146
GSCOR
EXCK
147
EXCK
SBSO
SBIN
148
WFCK
151
WFCK
C2PO
155
C2PO
BCLK
XTAL
167
158
BCLK
MDAT
160
MDAT
XTL2
169
LRCK
LRCK
163
GFS_V
107
GFS
170
XTL1
109
APEO
768FS
IC503 (2/2)
1
126
WARFI
WAVRV
127
DSAL
64
BUFFER
DSAR
66
IC812
DSAC
69
DSALFE
71
15
166
SDCK
74
DSALS
BUFFER
16
165
XSHD
IC813
17
167
XSAK
DSARS
76
18
168 SDEF
61
PHREFI
LEVEL
164
SHIFT
XSRQ
BCKAI
59
IC814
DSD DECODER
IC801
123
WCK
XWE
143
XCAS
144
XRAS
145
DCLK
141
DCKE
142
XRST_ZDSD
XRST_DSD
9
XRST
SHRMUT
10
SMUTE
XMSLAT
2
XMSLAT
MSCK
3
MSCK
MSDATI
MSDATI
4
MSDATO
6
MSDATO
SHRRDY
7
MSREADY
ISBTEST
115
TEST1
768FS
MCKI
11
29
29
D+5V
3
32
DSI1
DSAL
56
34
DSI2
DSAR
58
36
DSI3
DSAC
64
38
DSI4
DSASW
66
40
DSI5
DSALS
60
42
DSI6
DSARS
62
30
FS64
28
FS128
DSD
IC808
DIGITAL
D-RAM
SIGNAL
PROCESSOR
IC803
15
WE
16
CAS
17
RAS
35
CLK
34 CKE
MDAT
96
CDDATAL
92
CDDATAI
LRCK
95
LRCKI
90
LRCKO
BCLK
94
BCKI
XRST_ZDSD
99
XRST
SHRMUT
98
SMUTE
XZLAT
7
XMSLAT
MSCK
6
MSCK
MSDATI
MSDATI
5
MSDATO
4
MSDATO
SHRRDY
3
MSREADY
CDDATASL
93
CDDATASL
A1
81
768FS
88
MCKI
A2
78
768FS
12
CLOCK
768FS
10
BUFFER
1
768FS
IC811
8
SCD-XA333ES
DSAL
N
(Page 31)
DSAR
DSAC
DSASW
DSALS
DSARS
CDDATA
LRCK
128FSI
64FSI
• Signal Path
: SACD PLAY
256FS
: CD PLAY
BCLK
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