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signs to support layout with longer trace length or
slower DRAM. The DRAM write burst timing are
controlled by register.]
: X3 33( default)
System BZOS &cZzeabZe[DeIinc whether system BIOS area cacheable or not.]
video BIOS ~ucZzeubZe[Dcfine whether video BIOS area cacheable or not.]
Memory Hole AT ISM-ZdMTThis tield enable a memory hole in main memory
space. CPIJ cycles matching an enabled hole are
passed on to PCI. Note that a selected can not be
changed while the L2 cache is enabled.]
THE DLiFAIJl,'I' VALUE IS 1.
l/O.
Z6 BIT Z/r) RECOVERY TIME:
TO DEFINII 'I'tIli RI<COVERY TIME FROM 1 TO 4 FOR 16-BIT I/O.
PAGE 16
CHAPTER 3. BIOS SETUP
.
3-5.
INTEGRATED PERIPHERALS
ROM PC1 BIOS
INTEGRATED PERIPHERALS
AWARD SOFTWARE. INC.
IDE HDD Block Mode
: Enabled
IDE Primary Master PI0
IDE Primary Slave PI0
IDE Secondary Master PI0
IDE Secondary Slave PI0
On-Chip Primary PC1 IDE
On-Chip Secondary PC1 IDE
ECP ti=?i%&--
multi sector transfer, instead of one sector per transfer,
Most of IDE drivers, except very early designs can use
this feature.]
On-Chip Primary PCZ IDE [Select use Chip support Primary PC1 IDE.]
PAGE 17
CHAPTER 3. BIOS SETUP
ESC : Quit
F2 : Color
F6 : Load Bios Defaults
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