Antenna Switch; Harmonic Filter; Power Control - Motorola GM1200E Service Manual

9.4

Antenna Switch

The antenna switch is switched synchronously with the K9V1 voltage and feeds either the antenna
signal coming through the harmonic filter to the receiver or the transmitter signal coming from the PA
to the antenna via the harmonic filter.
In transmit mode, this K9V1 voltage is high and biases Q5520 and along with the RF signal from
Q5510 allows a collector current to be drawn. The collector current of Q5520 drawn from A+ flows
via L5542, L5541, directional coupler, D5551, L5551, D5631, L5631, R5616, R5617 and L5611 and
switches the PIN diodes D5551 and D5631 to the low impedance state. D5551 leads the RF signal
from the directional coupler to the harmonic filter. The low impedance of D5631 is transformed to a
high impedance at the input of the harmonic filter by the resonant circuit formed by L5551, C5633
and the input capacitance of the harmonic filter.
In receive mode the low K9V1 and no RF signal present from Q5510 turn off the collector current of
Q5520. With no current drawn by Q5520 and resistor R5615 pulling the voltage at PIN diode D5631
to A+ both PIN diodes are switched to the high impedance state. The antenna signal, coming
through the harmonic filter, is channelled to the receiver via L5551, C5634 and line PA RX.
A high impedance resonant circuit formed by D5551 in off state and L5554, C5559 prevents an
influence of the receive signal by the PA stages. The high impedance of D5631 in off state doesn´t
influence the receiver signal.
9.5

Harmonic Filter

The transmitter signal from the antenna switch is channelled through the harmonic filter to the
antenna connector J5501.The harmonic filter is formed by inductors L5552, L5553, and capacitors
C5557, C5552 through C5555. This network forms a low-pass filter to attenuate harmonic energy of
the transmitter to specifications level. R5550 is used for electro - static protection.
9.6

Power Control

The power control loop regulates transmitter power with an automatic level control (ALC) loop and
provides protection features against excessive control voltage and high operating temperatures.
MOS FET device bias, power and control voltage limit are adjusted under microprocessor control
using a Digital to Analogue (D/A) converter (U0731). The microprocessor writes the data into the D/
A converter via serial interface (SRL) composed of the lines SPI CLCK SRC (clock), SPI DATA SRC
(data) and DAC CE (chip enable). The D/A adjustable control voltage limit increases transmitter rise
time and reduces adjacent channel splatter as it is adjusted closer to the actual operating control
voltage.
The microprocessor controls K9V1 ENABLE (U0101-3) to switch on the first and the second PA
stage via transistors Q0741, Q0742 and signal K9V1. The antenna switch is turned on by the
collector current of the second PA stage. PA DISABLE, also microprocessor controlled (U0101-34),
sets BIAS VLTG (U0731-4) and VLTG LIMIT SET (U0731-13) via Q0731, D0731 in receive mode to
low to switch off the bias of the MOS FET device Q5530 and to switch off the power control voltage
(PWR CNTL).
Through an Analogue to Digital (A/D) input (VLTG LIMIT) the microprocessor can read the PA
control voltage (PWR CNTL) during the tuning process.
Introduction/Theory of Operation
Transmitter Power Amplifier (PA) 5-25W
3.1-21