Only For Training And Service Purposes - LG GD580 Service Manual

3. Technical brief
F. System Control Subsystem
The SYSCON resides at the top level of the circuit architecture and is responsible for clock
generation and clock and reset distribution within the digital baseband controller, as well as to
external devices.
The block is a slave peripheral under control of the ARM processor. The programming of the
SYSCON controls the fundamental modes of operation within the digital baseband controller.
Individual blocks can also be reset and their clocks held inactive by accessing the appropriate
control registers.
3.1.4 RF Interface
A. GSM Radio Link Interface
DB3150 controls GSM RF part using these signals through GSM RF chip-RF3000.
RF_DATA_A
RF_DATA_B
RF_DATA_C
RF_DATA_STRB
B. WCDMA Radio Link Interface
RF_WCDMA_PA_0_EN
RF_WCDMA_PA_1_EN
RF_WCDMA_DCDC_EN
RF_WCDMA_PWRDET_EN
Figure 3-1-6. Schematic of WCDMA RF Interface
LGE Internal Use Only
Y4
RF_DATA_A
AA2
RF_DATA_B
Y3
RF_DATA_C
Y2
RF_DATA_STRB
Figure 3-1-5. Schematic of GSM RF Interface
Y4
RF_DATA_A
AA2
RF_DATA_B
Y3
RF_DATA_C
Y2
RF_DATA_STRB
AB8
RF_WCDMA_PA_0_EN
V7
RF_WCDMA_PA_1_EN
AB5
RF_WCDMA_DCDC_EN
AB6
RF_WCDMA_PWRDET_EN
Y10
ADC_I_NEG
W10
ADC_I_POS
W9
ADC_Q_NEG
Y9
ADC_Q_POS
Y8
DAC_I_NEG
W8
DAC_I_POS
W7
DAC_Q_NEG
Y7
DAC_Q_POS
AB7
TX_POW
QDATA_AMP_MSB
IDATA_FREQ_MSB
AMP_LSB_FREQ_LSB
DCLK_DATSTR
QDATA_AMP_MSB
IDATA_FREQ_MSB
AMP_LSB_FREQ_LSB
DCLK_DATSTR
WTX_BAND_1_EN
WDCDC_EN
WPOW_DET_EN
WRX_I_N
WRX_I_P
WRX_Q_N
WRX_Q_P
WTX_I_N
WTX_I_P
WTX_Q_N
WTX_Q_P
WPOW_DET
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Only for training and service purposes