Toshiba SD-1200 Service Manual page 88

Main ICs Function
Ref. No. IC Name
IC601 S24C04BFJ-TB
IC303 ADV7170
IC301 MD36710X
IC401 TC9489F
IC502 TA1313T
IC503 KA3032
IC906 PCM1716E
IC604 TMP94CS40AF
IC202 TC203G08F0103
IC506 MBM29F800TB-55
Table 3-5-2 PCM1716E-T
Pin
Name
No.
1 LRCIN Left and Right Clock Input. This clock is
equal to the sampling rate - l
2 DIN Serial Audio Data Input.
3 BCKIN Bit Clock Input for Serial Audio Data.
4 CLKO Buffered Output of Oscillator. Equivalent to
System Clock.
5 XTI Oscillator Input (External Clock Input)
6 XTO Oscillator Output
7 DGND Digital Ground
8 V Digital Power +5V
DD
9 V 2R Analog Power +5V
CC
10 AGND2R Analog Ground
11 EXTR Rch, Common Pin of Analog Output Amp
12 NC No Connection
13 V R Rch, Analog Voltage Output of Audio Signal
OUT
14 AGND1 Analog Ground
15 V 1 Analog Power +5V
CC
16 V L Lch, Analog Voltage Output of Audio Signal
OUT
17 NC No Connection
18 EXTL Lch, Common Pin of Analog Output Amp
19 AGND2L Analog Ground
20 V 2L Analog Power +5V
CC
21 ZERO Zero Data Flag
22 RST Reset. When this pin is low, the DF and
modulators are held in reset.
23 CS/IWO Chip Select/Input Format Selection. When
this pin is low, the Mode Control is
effective.
24 MODE Mode Control Select. (H: Software, L:
Hardware)
25 MUTE Mute Control.
26 MD/DM0 Mode Control, DATA/De-emphasis
Selection 1
27 MC/DM1 Mode Control, BCK/De-emphasis Selection
(2)
2
2
28 ML/I S Mode Control, WDCK/Input Format
Selection
Notes: (1) Pins 1,2,3; Schmitt Trigger input
(2) Pins 22,24,25,26,27,28; Schmitt Trigger input with
pull-up resistor.
(3) Pin 23; Schmitt Trigger input with pull-down
resistor.
Function
EE-PROM
Video Encorder
AV Decorder
SERVO & Data Processor
RF Signal processing IC
5-CH Motor Driver
DA Converter
Main Micro Processor
Track Buffer
Flash ROM
Function
(1)
.
s
(1)
(1)
(2)
(3)
(2)
(2)
(2)
Table 3-5-1
Setup default, memorization of specification setting.
Built-in D/A converter. Encodes digital video signal to analog video
signal of NTSC/PAL system.
Decryption, MPEG-2 Decode, Audio Decode, Sub Picture Decode,
OSD.
Performs servo control of DVD or CD, and performs demodulation
and correction of RF signal.
Equalizes of playback RF signal and generates error detection signal
required for each servo operation.
5ch driver for motor driving.
Stereo audio DA converter with a dual PPL built-in.
Performs system control for all circuits.
Rate control and Buffer control.
Memorization for firmware.
Table 3-5-3 PLL1700E-T
Pin
Name
No.
1 ML/SR0
2 MODE
3 V
DD
4 GND
5 XT2
6 XT1
7 GNDP
8 V
DDP
9 RSV
10 MCKO
11 MCKO
12 SCKO1
13 SCKO4
14 SCKO2
15 GNDB
16 V
DC8
17 SCKO3
18 RST
19 MD/FS0
20 MC/FS1
Note:(1) Schmitt-trigger input with internal pull-down resistors.
Detail
Function
Latch Enable for Software Mode/Sampling
Rate Selection for Hardware Mode. When
MODE pin is LOW, ML is selected.
Mode Control Select. When this pin is
HIGH, device is operated in hardware
mode using SR0 (pin 1), FS0 (pin 19), and
FS1 (pin 20). When this pin is LOW, device
is operated in software mode by three-wire
interface using ML (pin 1), MD (pin 19) and
(1)
MC (pin 20).
Digital Power Supply. +5V.
Digital Ground.
27MHz Crystal. When an external 27MHz
clock is applied to XT1 (pin 6), this pin
must be connected to GND.
27MHz Oscillator Input/External 27MHz
input.
Ground for PLL.
Power Supply for PLL +5V.
Reserved. Must be left open.
27MHz Output.
Inverted 27MHz Output.
Fixed 33.8688MHz Clock Output.
768/ Clock Output.
s
256/ Clock Output.
s
Digital Ground for V
DC8
Digital Power Supply for Clock Output
Buffers. +3.3V.
3841 Output. This output has been
s
optimized for the lowest jitter and should
be connected to the audio DAC(s).
Reset. When this pin is LOW, device is
(1)
held in reset.
Serial Data Input for Software Mode/
Sampling Frequency Selection for
Hardware Mode. When MODE pin is LOW.
(1)
MD is selected.
Shift Clock Input for Software Mode/
Sampling Frequency Selection for
Hardware Mode. When MODE pin is LOW.
(1)
MC is selected.
(1)