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Manuals and User Guides for SMSC FlexPWR MII 10/100. We have
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SMSC FlexPWR MII 10/100 manual available for free PDF download: Specification Sheet
SMSC FlexPWR MII 10/100 Specification Sheet (79 pages)
MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR technology in a small footprint
Brand:
SMSC
| Category:
Transceiver
| Size: 1 MB
Table of Contents
Product Features
1
Table of Contents
3
Chapter 1 Introduction
9
General Terms and Conventions
9
General Description
9
Architectural Overview
10
Configuration
10
Figure 1.1 Lan8710/Lan8710I System Block Diagram
10
Figure 1.2 Lan8710/Lan8710I Architectural Overview
11
Chapter 2 Pin Configuration
12
Package Pin-Out Diagram and Signal Table
12
Figure 2.1 Lan8710/Lan8710I 32-QFN Pin Assignments (TOP VIEW)
12
Table 2.1 Lan8710/Lan8710I 32-PIN QFN Pinout
13
Chapter 3 Pin Description
14
MAC Interface Signals
14
Table 3.1 Buffer Types
14
Table 3.2 MII/RMII Signals 32-QFN
14
LED Signals
16
Table 3.3 LED Signals 32-QFN
16
Management Signals
17
General Signals
17
10/100 Line Interface Signals
17
Table 3.4 Management Signals 32-QFN
17
Table 3.5 General Signals 32-QFN
17
Table 3.6 10/100 Line Interface Signals 32-QFN
17
Analog Reference
18
Power Signals
18
Table 3.7 Analog References 32-QFN
18
Table 3.8 Power Signals 32-QFN
18
Chapter 4 Architecture Details
19
Top Level Functional Architecture
19
100Base-TX Transmit
19
100M Transmit Data Across the MII/RMII Interface
19
Figure 4.1 100Base-TX Data Path
19
5B Encoding
20
Table 4.1 4B/5B Code Table
20
Scrambling
21
NRZI and MLT3 Encoding
21
100M Transmit Driver
21
100M Phase Lock Loop (PLL)
22
100Base-TX Receive
22
100M Receive Input
22
Equalizer, Baseline Wander Correction and Clock and Data Recovery
22
Figure 4.2 Receive Data Path
22
NRZI and MLT-3 Decoding
23
Descrambling
23
Alignment
23
4B Decoding
23
Receive Data Valid Signal
23
Receiver Errors
24
100M Receive Data Across the MII/RMII Interface
24
10Base-T Transmit
24
10M Transmit Data Across the MII/RMII Interface
24
Figure 4.3 Relationship between Received Data and Specific MII Signals
24
Manchester Encoding
25
Transmit Drivers
25
10Base-T Receive
25
Receive Input and Squelch
25
Manchester Decoding
25
10M Receive Data Across the MII/RMII Interface
26
Jabber Detection
26
MAC Interface
26
MII
26
Rmii
26
MII Vs. RMII Configuration
27
Table 4.2 MII/RMII Signal Mapping
27
Auto-Negotiation
28
Parallel Detection
30
Re-Starting Auto-Negotiation
30
Disabling Auto-Negotiation
30
Half Vs. Full Duplex
30
HP Auto-MDIX Support
30
Internal +1.2V Regulator Disable
31
Disable the Internal +1.2V Regulator
31
Enable the Internal +1.2V Regulator
31
Figure 4.4 Direct Cable Connection Vs. Cross-Over Cable Connection
31
Nintsel Strapping and LED Polarity Selection
32
REGOFF and LED Polarity Selection
32
Figure 4.5 Nintsel Strapping on LED2
32
Table 4.3 Configuration
32
PHY Address Strapping
33
Variable Voltage I/O
33
Transceiver Management Control
33
Serial Management Interface (SMI)
33
Figure 4.6 REGOFF Configuration on LED1
33
Figure 4.7 MDIO Timing and Frame Structure - READ Cycle
34
Figure 4.8 MDIO Timing and Frame Structure - WRITE Cycle
34
Chapter 5 SMI Register Mapping
35
Table 5.1 Control Register: Register 0 (Basic)
35
Table 5.2 Status Register: Register 1 (Basic)
35
Table 5.3 PHY ID 1 Register: Register 2 (Extended)
35
Table 5.4 PHY ID 2 Register: Register 3 (Extended)
35
Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended)
36
Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended)
36
Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended)
36
Table 5.8 Register 15 (Extended)
36
Table 5.9 Silicon Revision Register 16: Vendor-Specific
36
Table 5.10 Mode Control/ Status Register 17: Vendor-Specific
37
Table 5.11 Special Modes Register 18: Vendor-Specific
37
Table 5.12 Register 24: Vendor-Specific
37
Table 5.13 Register 25: Vendor-Specific
37
Table 5.14 Symbol Error Counter Register 26: Vendor-Specific
37
Table 5.15 Special Control/Status Indications Register 27: Vendor-Specific
38
Table 5.16 Special Internal Testability Control Register 28: Vendor-Specific
38
Table 5.17 Interrupt Source Flags Register 29: Vendor-Specific
38
Table 5.18 Interrupt Mask Register 30: Vendor-Specific
38
Table 5.19 PHY Special Control/Status Register 31: Vendor-Specific
38
SMI Register Format
39
Table 5.20 SMI Register Mapping
39
Table 5.21 Register 0 - Basic Control
40
Table 5.22 Register 1 - Basic Status
40
Table 5.23 Register 2 - PHY Identifier 1
41
Table 5.24 Register 3 - PHY Identifier 2
41
Table 5.25 Register 4 - Auto Negotiation Advertisement
41
Table 5.26 Register 5 - Auto Negotiation Link Partner Ability
42
Table 5.27 Register 6 - Auto Negotiation Expansion
43
Table 5.28 Register 16 - Silicon Revision
43
Table 5.29 Register 17 - Mode Control/Status
43
Table 5.30 Register 18 - Special Modes
44
Table 5.31 Register 26 - Symbol Error Counter
44
Table 5.33 Register 28 - Special Internal Testability Controls
45
Table 5.34 Register 29 - Interrupt Source Flags
45
Table 5.32 Register 27 - Special Control/Status Indications
45
Table 5.35 Register 30 - Interrupt Mask
46
Table 5.36 Register 31 - PHY Special Control/Status
46
Interrupt Management
47
Primary Interrupt System
47
Table 5.37 Interrupt Management Table
47
Alternate Interrupt System
48
Miscellaneous Functions
48
Carrier Sense
48
Table 5.38 Alternative Interrupt System Management Table
48
Collision Detect
49
Isolate Mode
49
Link Integrity Test
49
Power-Down Modes
49
Reset
50
LED Description
50
Loopback Operation
50
Figure 5.1 Near-End Loopback Block Diagram
51
Figure 5.2 Far Loopback Block Diagram
51
Configuration Signals
52
Figure 5.3 Connector Loopback Block Diagram
52
Table 5.39 Pin Names for Address Bits
52
Table 5.40 MODE[2:0] Bus
53
Table 5.41 Pin Names for Mode Bits
53
Chapter 6 AC Electrical Characteristics
55
Serial Management Interface (SMI) Timing
55
Figure 6.1 SMI Timing Diagram
55
Table 6.1 SMI Timing Values
55
MII 10/100Base-TX/RX Timings
56
MII 100Base-T TX/RX Timings
56
Figure 6.2 100M MII Receive Timing Diagram
56
Table 6.2 100M MII Receive Timing Values
56
Clock out
57
Figure 6.3 100M MII Transmit Timing Diagram
57
Table 6.3 100M MII Transmit Timing Values
57
MII 10Base-T TX/RX Timings
58
Figure 6.4 10M MII Receive Timing Diagram
58
Table 6.4 10M MII Receive Timing Values
58
Figure 6.5 10M MII Transmit Timing Diagrams
59
Table 6.5 10M MII Transmit Timing Values
59
RMII 10/100Base-TX/RX Timings (50Mhz REF_CLK IN)
60
RMII 100Base-T TX/RX Timings (50Mhz REF_CLK IN)
60
Figure 6.6 100M RMII Receive Timing Diagram (50Mhz REF_CLK IN)
60
Table 6.6 100M RMII Receive Timing Values (50Mhz REF_CLK IN)
60
Figure 6.7 100M RMII Transmit Timing Diagram (50Mhz REF_CLK IN)
61
Table 6.7 100M RMII Transmit Timing Values (50Mhz REF_CLK IN)
61
RMII 10Base-T TX/RX Timings (50Mhz REF_CLK IN)
62
Figure 6.8 10M RMII Receive Timing Diagram (50Mhz REF_CLK IN)
62
Table 6.8 10M RMII Receive Timing Values (50Mhz REF_CLK IN)
62
Figure 6.9 10M RMII Transmit Timing Diagram (50Mhz REF_CLK IN)
63
Table 6.9 10M RMII Transmit Timing Values (50Mhz REF_CLK IN)
63
RMII CLKIN Requirements
64
Reset Timing
64
Figure 6.10 Reset Timing Diagram
64
Table 6.10 RMII CLKIN (REF_CLK) Timing Values
64
Table 6.11 Reset Timing Values
64
Clock Circuit
65
Table 6.12 Lan8710/Lan8710I Crystal Specifications
65
Chapter 7 DC Electrical Characteristics
66
DC Characteristics
66
Maximum Guaranteed Ratings
66
Table 7.1 Maximum Conditions
66
Table 7.2 ESD and LATCH-UP Performance
66
Operating Conditions
67
Table 7.3 Recommended Operating Conditions
67
Power Consumption
68
Table 7.4 Power Consumption Device Only
68
DC Characteristics - Input and Output Buffers
69
Table 7.5 MII Bus Interface Signals
69
Table 7.6 LAN Interface Signals
70
Table 7.7 LED Signals
70
Table 7.8 Configuration Inputs
70
Table 7.9 General Signals
70
Table 7.10 Internal Pull-Up / Pull-Down Configurations
71
Table 7.11 100Base-TX Transceiver Characteristics
71
Table 7.12 10BASE-T Transceiver Characteristics
72
Chapter 8 Application Notes
73
Application Diagram
73
MII Diagram
73
Figure 8.1 Simplified Application Diagram
73
Twisted-Pair Interface Diagram
74
Power Supply Diagram
74
Figure 8.2 High-Level System Diagram for Power
74
Figure 8.3 High-Level System Diagram for Power
74
Figure 8.4 Copper Interface Diagram
74
Figure 8.5 Copper Interface Diagram
74
Magnetics Selection
75
Chapter 9 Package Outline
76
Figure 9.1 Lan8710/Lan8710I-EZK 32 Pin QFN Package Outline, 5 X 5 X 0.9 MM Body (Lead-Free)
76
Table 9.1 32 Terminal QFN Package Parameters
76
Figure 9.1 QFN, 5X5 Taping Dimensions and Part Orientation
77
Figure 9.2 Reel Dimensions for 12Mm Carrier Tape
78
Figure 9.3 Tape Length and Part Quantity
79
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