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SBE HighWire HW400c/2 Manuals
Manuals and User Guides for SBE HighWire HW400c/2. We have
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SBE HighWire HW400c/2 manual available for free PDF download: User Reference Manual
SBE HighWire HW400c/2 User Reference Manual (104 pages)
SBE User Computer Board User Reference Guide
Brand:
SBE
| Category:
Computer Hardware
| Size: 1.75 MB
Table of Contents
Revision History
3
Table of Contents
5
Conventions
12
1 About this Manual
13
2 Introduction
14
Product Description
14
Unpacking Instructions
15
Figure 1. Hw400C/2 Block Diagram
15
Handling Procedures
16
Hardware Installation of the Hw400C/2
16
Returns/Service
17
Operating Environment
17
Table 1. Hw400C/2 Operating Environment
17
Mean Time between Failures (MTBF)
18
Regulatory Agency Certifications
19
Safety
19
US and Canadian Emissions
19
European Emissions and Immunity
19
Agency Compliance
19
Physical Properties
20
Figure 2. the Hw400C/2 PTMC Processing Platform
20
Table 2. Hw400C/2 Physical Dimensions
20
Figure 3. Hw400C/2 Front Panel
21
Hw400C/2 Front Panel
21
Bus Keying
22
Compact PCI
22
Part Number and Serial Number
22
PTMC Site
22
Power Requirements
23
Table 3. Hw400C/2 Power Requirements VIO = 5.0V
23
Table 4. Hw400C/2 Power Requirements VIO = 3.3V
23
Product Configurations
24
Switches
24
Table 5. Hw400C/2 Order Time Options
24
3 Functional Blocks
25
Powerpc Processor
25
MPC744X Development/Debug Support
25
Table 6. Hw400C/2 Processor Options
25
Console Port
26
Pushbutton Reset / Interrupt
26
Figure 4. Console Port Pin out
26
Figure 5. J8, J9 Reset/Nmi Header
26
Figure 6. J8 and J9 with Optional Reset/Nmi Cable
27
Table 7. J8 and J9 Pin out
27
COP/JTAG Port
28
Special Purpose Jumper Block
28
Figure 7. Optional Reset/Nmi Switch
28
Figure 8. COP/JTAG Pinout
28
Figure 9. J7 Special Purpose Jumper Block
28
Jumper Pins
29
MV64462 System Controller
29
System Bus
29
Dual Data Rate (DDR) SDRAM
29
Table 8. J7 Pin Functions
29
Host PCI Bus
30
Operation Without Compactpci Bus
30
Local PCI Bus
30
Serial EEPROM
31
Table 9. Microwire EEPROM Contents, Factory Area
32
Table 10. Microwire EEPROM Contents, Uboot Area
33
MV64462 Ethernet Interface
34
MV64462 Device Interface
34
SRAM Device
34
Boot PROM
34
Disk-On-Chip
34
CT Bus Controller
35
Cpld
35
Watchdog Timer
35
Reset
35
Multi-Purpose Port (MPP) Usage
36
Table 11. MV64462 Multi-Purpose Port Assignments
36
Computer Telephony Bus Controller
37
Interface (T8110L)
37
T8110L Clocking Interface (T8110L)
37
Table 12. LSC Assignments
37
Figure 10. Local CT Bus Clocking Block Diagram
38
Figure 11. Local CT Bus Clock Generation
38
Operation in Non-H.110 Backplane
39
Layer 2 Ethernet Switch
39
Table 13. LREF [3:2] Assignments
39
Table 14. Layer 2 Switch Port Assignments
39
Figure 12. Front Panel Ethernet RJ-45 Leds
40
Front Panel (RJ-45) Ethernet Interface
40
MV64462 System Controller Ethernet Interface
40
Switch Registers Initialization and Monitoring
40
Compactpci Connector J3, Power and Ground
41
Compactpci Packet Switch Backplane (Cpsb) Ports
41
PT5MC Ethernet Ports
41
On-Board Ethernet Indicator Leds
42
Table 15. Compact PCI Connector J3 Pin out
42
Mezzanine Card Sites
44
PT5MC Type Mezzanine Cards
44
PT2MC Type Mezzanine Cards
44
PMC Type Mezzanine Cards
44
Mezzanine Card Power
45
PTMC/PMC Connector Summary
45
Table 16. Mezzanine Card Power Budget
45
Table 17. PTMC/PMC Connector Summary
45
PTMC Jn1 and Jn2 PCI Connectors
46
Table 18. PTMC Jn1 and Jn2 Connector Pin Assignments
46
PTMC Jn3 CT Bus Connector
47
Table 19. PTMC Configuration #2/#5 Pn3 Connector Pin Assignment
47
PTMC Jn4 Lan/User I/O Connector
48
PTMC Site a Jn4
48
Table 20. PTMC Site a Configuration #2/#5 Pn4 Connector Pin Assignment
49
PTMC Site B Pn4
50
Table 21. PTMC Site B Configuration #2/#5 Pn4 Connector Pin Assignment
50
PTMC Site Voltage Keying
51
IPMI System Management
51
IPMI Controller
51
Temperature and Voltage Monitor
52
Figure 13. IPMI Block Diagram
52
Table 22. GPIO Port Assignments for IPMI
52
Hot Swap Ejector Latch Detection
53
Blue (Hot Swap) LED Control
53
Boot Status Monitor
53
Table 23. Voltage Monitor A/D Port Assignments for IPMI
53
Table 24. Hw400C/2 Temperature Sensor Locations
53
Board Reset Via IPMI
54
IPMI System Power Supply
54
IPMI Firmware Eeproms
54
Table 25. Firmware EEPROM Addresses
54
Zircon PM Reset
55
IMPI Get Device ID
55
Table 26. Product ID Number
55
Hot Swap Support
56
Hot Swap on J1 and J2
56
Hot Swap on J3
56
Hot Swap on J4
56
Hot Swap on J5
56
Hot Swap Sequence
57
Table 27. Overview of Hot Swap Insertion/Extraction Sequences
57
4 Programming Information
58
Hw400C/2 Memory Map
58
Table 28. Hw400C/2 Memory Map
58
CPLD Registers
59
Table 29. CPLD Registers
59
Clock Select Register (CSR)
60
Table 30. Clock Select Register (CSR) Offset Address 0X04
60
Board Status Register (BSR)
61
LED Register a (LEDA)
61
Table 31. Board Select Register (BSR) Offset Address 0X05
61
Table 32. LED Register a (LEDA) Offset Address 0X06
61
Geographic Addressing Register (GAR)
62
Memory Option Register (MOR)
62
Table 33. Memory Option Register (MOR) Offset Address 0X07
62
Table 34. Geographic Addressing Register (CSR) Offset Address 0X08
62
PTMC Control Register (PCR)
63
PTMC Reset Register (PRR)
63
Table 35. PTMC Reset Register (PRR) Offset Address 0X09
63
Table 36. PTMC Control Register (PCR) Offset Address 0X0A
63
Board Option Register (BOR)
64
General Purpose Register (GPR)
64
Table 37. Board Option Register (BOR) Offset Address 0X0D
64
Table 38. General Purpose Register (GPR) Offset Address 0X0E
64
Extended Type Register (ETR)
65
PCI Status Register (PSR)
65
Table 39. PCI Status Register (PSR) Offset Address 0X0F
65
Table 40. Extended Type Register (ETR) Offset Address 0X10
65
Hardware Revision Register (HRR)
66
PLL Configuration Register a (PLLA)
66
Table 41. Hardware Revision Register (HRR) Offset Address
66
Table 42. PLL Configuration Register a (PLLA) Offset Address 0X12
66
PLL Configuration Register B (PLLB)
67
Table 43. PLL Configuration Register B (PLLB) Offset Address 0X13
67
LED Register B (LEDB)
68
Table 44. LED Register B (LEDB) Offset Address 0X14
68
Table 45. On-Board LED Functions as Determined by LEDB [1:0]
68
CPU Timer Register (CTR)
69
Device Control Register (DCR)
69
Table 46. Device Control Register (CSR) Offset Address 0X15
69
Table 47. CPU Timer Register (CTR) Offset Address 0X16
69
SPI Address Register (SAR)
70
SPI Page Register (SPR)
70
Table 48. Warm Reset Register (WRR) Offset Address 0X17
70
Table 49. SPI Page Register (SPR) Offset Address 0X1A
70
Table 50. SPI Address Register (SAR) Offset Address 0X1B
70
Warm Reset Register (WRR)
70
Read Byte Count Register (RBC)
71
SPI Read Byte Offset Register (SOR)
71
Table 51. SPI Read Byte Offset Select Register (SOR) Offset Address 0X1C
71
Table 52. Read Byte Count Register (RBC) Offset Address 0X1D
71
SPI Data Registers (SDR0 - SDR7)
72
Table 53. Write Byte Count Register (WBC) Offset Address 0X1E
72
Table 54. SPI Data Registers (Sdrn) Offset Address 0X20-0X27
72
Write Byte Count Register (WBC)
72
EEPROM Address Register (EAR)
73
SPI Error and Status Register (SESR)
73
Table 55. SPI Error and Status Register (SESR) Offset Address 0X1F
73
Table 56. EEPROM Address Register (EAR) Offset Address 0X28
73
EEPROM Operation/Status Register (EOSR)
74
Table 57. EEPROM Operation/Status Register (EOSR) Offset Address 0X29
74
EEPROM Data Registers (EDR0 - EDR1)
75
Accessing the Serial EEPROM
75
Reading an EEPROM Address
75
Table 58. EEPROM Data Registers (Edrn) Offset Address 0X2A-0X2B
75
Writing an EEPROM Address
76
Accessing the SPI Interface
76
Registers in the CPLD
76
BCM5388 Registers Access Rules
76
Reading BCM5388 Register
77
Writing a BCM5388 Register
77
5 Linux on the Hw400C/2 and Host System
79
Host Hardware and Software Requirements
79
Figure 14. Hw400C/2 Network and System Environment
79
Network and System Configuration
80
Installing Linux on Your Host System
80
Configuring the Host System
81
Modifying the Host Path
81
Configuring the Host NFS Server
81
Configuring Host Tftp Services
82
Configuring Tftp with Inetd
83
Configuring Tftp with Xinetd
85
Configuring a Bootp Server
86
Booting the Hw400C/2
87
U-Boot, Universal Bootloader
88
U-Boot Commands
88
U-Boot Environment Variables
89
Power up Call Trace
91
Booting with Tftp
92
U-Boot Parameters for Tftp with Bootp
92
U-Boot Parameters for Tftp with Static IP Address
93
Boot Console
93
Booting with Disk on Chip
96
Loading the Disk on Chip
96
Creating a Uramdisk Image
97
Booting from Doc
97
Compiling the Kernel (Uimage)
98
Gentoo Application Packages Management
99
Emerge
99
Enable Remote Login with Ssh
100
Starting Network Services; Xinetd
100
Starting Ftp Services; Vsftpd
100
Linux Device Drivers
101
Appendix Aipmi Getdeviceid
102
U-Boot Environment Variables
103
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