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SBE HighWire HW400c/2 User Reference Manual

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HighWire HW400c/2 User Reference Guide Rev 1.0
HW400c/2
___________________HighWire
User Reference Guide
M8275, Rev 1.0
October 10, 2006
Copyright 2006, SBE, Inc.
Page
i

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Summary of Contents for SBE HighWire HW400c/2

  • Page 1 HighWire HW400c/2 User Reference Guide Rev 1.0 HW400c/2 ___________________HighWire User Reference Guide M8275, Rev 1.0 October 10, 2006 Copyright 2006, SBE, Inc. Page...
  • Page 2 SBE, Inc., except that the purchaser may copy necessary portions for internal use only. While every effort has been made to ensure the accuracy of this manual, SBE cannot be held responsible for damage resulting from information herein. All specifications are subject to change without notice.

  • Page 3: Revision History

    HighWire HW400c/2 User Reference Guide Rev 1.0 Revision History Revision October 10, 2006 Date Changes October 10, 2006 Initial Release Copyright 2006, SBE, Inc. Page...
  • Page 4 HighWire HW400c/2 User Reference Guide Rev 1.0 THIS PAGE IS INTENTIONALLY LEFT BLANK October 10, 2006 Copyright 2006, SBE, Inc. Page...

  • Page 5: Table Of Contents

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table of Contents Revision History...iii Table of Contents ... v List of Figures ...ix List of Tables...ix Conventions ...xii About This Manual... 1 Introduction ... 2 2.1 Product Description... 2 2.2 Unpacking Instructions ... 3 2.3 Handling Procedures ...
  • Page 6 HighWire HW400c/2 User Reference Guide Rev 1.0 3.2 MV64462 System Controller ... 17 3.2.1 System Bus ... 17 3.2.2 Dual Data Rate (DDR) SDRAM ... 17 3.2.3 Host PCI Bus ... 18 3.2.3.1 Operation Without CompactPCI Bus ... 18 3.2.4 Local PCI Bus... 18 3.2.5 Serial EEPROM...
  • Page 7 HighWire HW400c/2 User Reference Guide Rev 1.0 3.6.7 IPMI System Power Supply ... 42 3.6.8 IPMI Firmware EEPROMs ... 42 3.6.9 Zircon PM Reset... 43 3.6.10 IMPI Get Device ID ... 43 3.7 Hot Swap Support ... 44 3.7.1 Hot Swap on J1 and J2 ... 44 3.7.2 Hot Swap on J3...
  • Page 8 HighWire HW400c/2 User Reference Guide Rev 1.0 4.4.3 Reading BCM5388 Register... 65 4.4.4 Writing a BCM5388 Register... 65 Linux on the HW400c/2 and Host system... 67 5.1 Host Hardware and Software Requirements ... 67 5.2 Network and System Configuration... 68 5.3 Installing Linux on your host system ...
  • Page 9 HighWire HW400c/2 User Reference Guide Rev 1.0 List of Figures Figure 1. HW400c/2 Block Diagram ... 3 Figure 2. The HW400c/2 PTMC Processing Platform ... 8 Figure 3. HW400c/2 Front Panel ... 9 Figure 4. Console port pin out ... 14 Figure 5.
  • Page 10 HighWire HW400c/2 User Reference Guide Rev 1.0 Table 14. Layer 2 Switch Port Assignments... 27 Table 15. Compact PCI connector J3 pin out ... 30 Table 16. Mezzanine Card Power Budget ... 33 Table 17. PTMC/PMC Connector Summary ... 33 Table 18.
  • Page 11 HighWire HW400c/2 User Reference Guide Rev 1.0 Table 48. Warm Reset Register (WRR) Offset address 0x17... 58 Table 49. SPI Page Register (SPR) Offset Address 0x1A ... 58 Table 50. SPI Address Register (SAR) Offset Address 0x1B ... 58 Table 51. SPI Read Byte Offset Select Register (SOR) Offset Address 0x1C... 59 Table 52.

  • Page 12: Conventions

    HighWire HW400c/2 User Reference Guide Rev 1.0 Conventions The following conventions are used in this document: A # following a signal name, e.g., INTA#, represents an active low signal. A / preceding a signal name, e.g., /INTA represents an active low signal.

  • Page 13: About This Manual

    HighWire HW400c/2 User Reference Guide Rev 1.0 ABOUT THIS MANUAL This manual is technical reference for the HighWire HW400c/2 Gigabit Switched PTMC Processing Platform for CompactPCI. This manual is intended for those who are installing the HW400c/2 into a system.

  • Page 14: Introduction

    H.110 CT Bus and rear I/O support. 2.1 Product Description The HW400c/2 is built on SBE’s advanced HighWire core architecture, and features the MPC7447A PowerPC processor, Marvell Discovery III system controller, up to 1GB DDR SDRAM and Disk-on-Chip flash file system storage to meet the demanding needs of today’s telecom and datacom applications.

  • Page 15: Unpacking Instructions

    • Save all packing material for storage or return shipment of the equipment. • For repairs or replacement of equipment damaged during shipment, contact SBE, Inc. to obtain a Return Materials Authorization (RMA) number and further shipping instructions. October 10, 2006...

  • Page 16: Handling Procedures

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.3 Handling Procedures The HW400c/2 board uses CMOS components that can be easily damaged by static electrical discharge. To avoid damage, familiarize yourself with electrostatic discharge (ESD) procedures, which include the following precautions: •...

  • Page 17: Returns/Service

    SBE, Inc. 4000 Executive Parkway, Suite 200 San Ramon, CA 94583 SBE’s Technical Support Department can be reached at 800-444-0990. 2.6 Operating Environment The HW400c/2 is designed to function within the environment shown in Table 1. Table 1. HW400c/2 Operating Environment Storage temperature -40 to +85 C (-40 to +185 °F)

  • Page 18: Mean Time Between Failures (Mtbf)

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.7 Mean Time Between Failures (MTBF) The Mean Time Between Failure (MTBF) of SBE, Inc’s HW400c/2 was calculated per Telcordia Technical Reference TR-332 Issue 6, December 1997. The following specific parameters were used:...

  • Page 19: Regulatory Agency Certifications

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.8 Regulatory Agency Certifications The HW400c/2 complies with the requirements listed below. 2.8.1 Safety • IEC60950 • IEC60950 • UL60950 • Certified Body (CB) Report 2.8.2 US and Canadian Emissions • FCC Part 15 Class B •...

  • Page 20: Physical Properties

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.10 Physical Properties The Highwire 400c/2 is compliant with the mechanical specifications of PCMIG 2.0. Table 2 lists the physical dimensions of the HW400c/2 product. Figure 2 shows the physical profile of the HW400c/2 board.

  • Page 21: Hw400C/2 Front Panel

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.10.1 HW400c/2 Front Panel The HW400c/2 CompactPCI front panel has custom cut outs with the appropriate thickness to accommodate two PTMC bezels (with EMC gaskets), two RJ-45 connectors, blue Hot Swap LED, green power LED, and status LEDs. Figure 3 below shows an illustration of the front panel.

  • Page 22: Part Number And Serial Number

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.10.2 Part number and serial number All b oards are marked with the manufacturing part number and assembly revision. This is marked on a label and affixed to the top of the board.

  • Page 23: Power Requirements

    HighWire HW400c/2 User Reference Guide Rev 1.0 2.10.4 Power Requirements The power requirements of the HW400c/2 are defined for two environments: • CompactPCI VIO of 5.0v (see Table 3) • CompactPCI VIO set 3.3v (see Table 4). 1. All voltages are required.

  • Page 24: Switches

    Table 5. HW400c/2 Order time options CPU Speed DDR RAM H.110 CT bus CompactPCI bus Options or modifications are available upon request. Please call SBE Sales for option availability, and/or modification requests. Build options have significant impact on power consumption. October 10, 2006 Standard Configuration Options 1.0 GHz...

  • Page 25: Functional Blocks

    HighWire HW400c/2 User Reference Guide Rev 1.0 FUNCTIONAL BLOCKS The HW400c/2 has six major functional blocks – the PowerPC processor, system controller, CT Bus interface, Ethernet switch, PTMC expansion sites, and the IPMI controller. The following sections describe these functional blocks in greater detail.

  • Page 26: Console Port

    An optional external pushbutton reset is provided as a 6-pin header (part of J8, J9, see Figure 2, Figure 5, and Table 7) on the board that accepts the standard SBE developer’s debug cable with toggle switch. Contact SBE Technical Support for additional details on obtaining a developer’s debug cable.

  • Page 27: Figure 6. J8 And J9 With Optional Reset/Nmi Cable

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table 7 describes the pin out of J8 and J9. Some of the pins listed are for Factory use only. Header Pin Label none none none I2C2 I2C2 Figure 6. J8 and J9 with optional Reset/NMI cable October 10, 2006 Table 7.

  • Page 28: Cop/Jtag Port

    HighWire HW400c/2 User Reference Guide Rev 1.0 Figure 7. Optional Reset/NMI switch 3.1.4 COP/JTAG Port A 16-pin header (J6, see Figure 2, and Figure 8) and a 6-pin header (JX6) are provided on the HW400c/2 board for connecting to the processor’s COP (Common On-chip Processor) port for factory development purpose e used to access the JTAG chain for the entire board.

  • Page 29: Jumper Pins

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.1.5 .1 Jumper Pins 9-10 11-12 13-14 15-16 3.2 MV64462 Sy stem Controller The HW400c/2 uses the Marvell Discovery III (MV64462) PowerPC System ontroller, which acts as the evice busses (see Figure 1). This section outlines the devices and functions inte rfaced to the MV64462.

  • Page 30: Host Pci Bus

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.2.3 Host PCI B The Marvell Discovery III (MV64462) host PCI bus (PCI bus 0) provides an interface between the process ites and the CompactPCI host. The MV64462 device acts as a PCI-to-PCI bridge between the two PCI buses.

  • Page 31: Serial Eeprom

    Table 9 and Table 10 summarize the contents of the EEPROM. The first 16 addresses (0x00-0x0F) are written by SBE when the boards are manufactured, and must not be modified. Space is reserved in the next 32 addresses (0x10-0x2F) for a total of 16 IP Addresses, beginning with the board IP address and the Gateway I ddress.

  • Page 32: Table 9. Microwire Eeprom Contents, Factory Area

    Reserved 0x0C Reserved 0x0D Reserved 0x0E Reserved 0x0F Reserved Shaded areas indicate addresses reserved for programming by SBE at the time the boards are manufactured. October 10, 2006 Typical Value Bits 7-0 (LSB) 0x20 Format 0xCC CRC32 for address 0x00...

  • Page 33: Table 10. Microwire Eeprom Contents, Uboot Area

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table 10. Microwire EEPROM Contents, Uboot Area Word Address Bits 15-8 (MSB) 0x10 Board IP Address byte 1 0x11 Board IP Address byte 3 0x12 Gateway IP Address byte 1 0x13 Gateway IP Address byte 3...

  • Page 34: Mv64462 Ethernet Interface

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.2.6 MV64462 Ethernet Interface The MV64462 contains an Ethernet MAC, which provides a MAC-to-MAC connection to port 7 of the on-board Broadcom BMC5388 layer 2 Ethernet switch (see Table 14). The connection is made via the RGMII ports on each device. The operating speed of the RGMII port is 125 MHz.

  • Page 35: Ct Bus Controller

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.2.7.4 CT Bus Controller The Agere T8110L CT bus controller on the HW400c/2 board is accessed and programmed via the device bus. It also has a data bus width of 16 bits. Burst reads/writes are not supported by the T8110L.

  • Page 36: Multi-Purpose Port (Mpp) Usage

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.2.10 Multi-Purpose Port (MPP) Usage The MV64462 Discovery III includes a 32-bit Multi-Purpose Port (MPP) that can be used for a variety of possible functions. The HW400c/2 board uses the MPP for the...

  • Page 37: Computer Telephony Bus Controller

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.3 Computer Telephony Bus Controller The HW400c/2 includes the Agere T8110L CT Bus Controller to control TDM bus switching between the backplane (CompactPCI J4 connector) and the local bus, which is connected to the JN3 connector on each of the two PTMC sites.

  • Page 38: Figure 10. Local Ct Bus Clocking Block Diagram

    HighWire HW400c/2 User Reference Guide Rev 1.0 Figure 10. Local CT Bus Clocking Block Diagram Control for the local “A” and “B” bus drivers is provided by bits 4, 5, 6, and 7 in the Clock Select Register (CSR). Refer to Section 4.2.1 for further details. Figure 11 shows the implementation.

  • Page 39: Operation In Non-H.110 Backplane

    HighWire HW400c/2 User Reference Guide Rev 1.0 The T8110L can be programmed such that its local frame reference (LREF [3:2]) puts are used to generate all of the TDM bus clocks and syncs. The T8110L Local Clock Reference Inputs have been assigned to the PTMC JN3 H.110 clock pins as shown in Table 13.

  • Page 40: Switch Registers Initialization And Monitoring

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.4.1 Switch Re gisters Initialization and Monitoring The switch is initialized and its registers polled by utilizing its SPI bus interface. This interface is connected through the CPLD. For a description of how to access the SPI interface, please refer to Section 4.4.

  • Page 41: Pt5Mc Ethernet Ports

    HighWire HW400c/2 User Reference Guide Rev 1.0 .4.4 PT5MC Eth ernet Ports Each of the two PT5MC sites on the HW400c/2 have two 10/100/1000 Mbps ports connected to the Ethernet switch. The signals conform to PICMG ECN 2.15-1.0- 001, using the first 24 pins of the respective JN4 connectors.

  • Page 42: On-Board Ethernet Indicator Leds

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table 1 3.4.6 On-board Ethernet Indicator LEDs The HW400c/2 includes eight on-board LED Ethernet ports. The LEDs are labeled L0-L8 connector J5. The BCM5388 has a serial LED interface, fro be xtracted. The serial LED signal is routed to hine that decodes the LED states for each port.
  • Page 43 HighWire HW400c/2 User Reference Guide Rev 1.0 The Link/Activity/Speed LED indication is as follows: • solid gree • blinking at 3 Hz for 10 Mb/s Tx or Rx; • blinking at 6 Hz for 100 Mb/s Tx or Rx; •...

  • Page 44: Mezzanine Card Sites

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.5 Mezzanine Card Sites The HW400c/2 board supports I/O expansion using either one or two industry- standard PTMC and/or PMC modules. This section provides technical details for these expansion sites. 3.5.1 PT5MC Type Mezzanine Cards...

  • Page 45: Mezzanine Card Power

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.4 Mezzanine Card Power Each of the two mezzanine card sites on the HW400c/2 is allotted a portion of the total power budget for the board. For the standard version, the mezzanine power budget is 16.2 Watts for each slot, while the optional high-power version allows 26.4...

  • Page 46: Ptmc Jn1 And Jn2 Pci Connectors

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.6 PTMC Jn1 and Jn2 PCI Connectors Communication using the local PCI bus is done across two PTMC/PMC connectors, JN1 and JN2. Table 18 shows the 32-bit PCI connector pin assignment for JN1 an JN2 on the HW400c/2 as defined by the PMC specification Table 18.

  • Page 47: Ptmc Jn3 Ct Bus Connector

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.7 PTMC Jn3 CT Bus Connector Table 19 shows the PTMC Pn3 CT Bus connector pin assignment for the HW400c/2 for both Configuration #2 (PT2MC) and Configuration #5 (PT5MC). The signal definitions for Pn3 are per the PICMG 2.15 specification.

  • Page 48: Ptmc Jn4 Lan/User I/O Connector

    HighWire HW400c/2 User Reference Guide Rev 1.0 .5.8 PTMC Jn4 LAN/User I/O Connector Table 20 (Site A) and Table 21 (Site B) show the PTMC Pn4 LAN and/or User I/O connector pin assignment for the HW400c/2 for both Configuration #2 (PT2MC User I/O only) and C 3.5.8.1...

  • Page 49: Table 20. Ptmc Site A Configuration #2/#5 Pn4 Connector Pin Assignment

    HighWire HW400c/2 User Reference Guide Rev 1.0 Tabl e 20. PTMC Site A Configuration #2/#5 Pn4 Connector Pin Assignment Pn4 PT2MC Signal Name Signal Name cPCI J5 E22 cPCI J5 D22 cPCI J5 cPCI J5 B22 cPCI J5 A22 cPCI J5 E21...

  • Page 50: Ptmc Site B Pn4

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.8.2 PTMC Site B Pn4 This table shows the connections from PTMC Site B Jn4 to the Compact PCI onnector J5 and, for PT5MC, the signals for the Ethernet ports, Link Ports A and B.

  • Page 51: Ptmc Site Voltage Keying

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.9 PTMC Site Voltage Keying Voltage key po ection 2.10.3. he HW400c/2 local PCI bus I/O voltage is 3.3 volts only. Therefore, PTMC and MC modules with 5 volt only I/O signals cannot be used on the HW400c/2...

  • Page 52: Temperature And Voltage Monitor

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table 22. GPIO Port Assignments for IPMI GPIO Port GPIO_00 GPIO_01 GPIO_07 GPIO_12 GPIO_13 GPIO_14 GPIO_15 – GPIO_19 GPIO_20 – GPIO_23 3.6.2 Temperatu re and Voltage Monitor IPMI functions implemented on the HW400c/2 include board temperature sensors TS0 and TS1 connected to I oltage), 2.5V, 3.3V, 5V and other supply voltages are connected to A/D input ports...

  • Page 53: Hot Swap Ejector Latch Detection

    HighWire HW400c/2 User Reference Guide Rev 1.0 Table 23. Voltage Monitor A/D Port Assignments for IPMI Supply Voltage Monitor 5-Volt 3.3-Volt 1.1-Volt (CPU core) 1.5-Volt (System controller core) 2.5-Volt (SDRAM) Table 24. HW400c/2 Temperature Sensor Locations Device TS0 (U84) TS1 (U83) 3.6.3 Hot Swap...

  • Page 54: Board Reset Via Ipmi

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.6.6 Board Reset via IPMI The IPMI controller has the capability to issue a board reset. A GPIO port on the Zircon PM (see Ta set signal from the Host CompactPCI bus. A standard IPMI command is issued to initiate the board reset.

  • Page 55: Zircon Pm Reset

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.6.9 Zircon PM Reset At power -up, the Zircon PM is held in reset state until the 3.3V supply voltage is within tolerance. 3.6.10 IMPI Get Device ID The response to the IPMI command “GetDeviceID” from the Shelf Manager is of the standard format.

  • Page 56: Hot Swap Support

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.7 Hot Swap Support The HW400c/2 complies with the PICMG 2.1 specification for full hot swap in CompactPCI systems as defined by the PICMG 2.1 R2.0 specification. Hot swap functions, such as power FET control, are provided by a Linear Technologies LTC1664 Hot Swap Controller.

  • Page 57: Hot Swap Sequence

    HighWire HW400c/2 User Reference Guide Rev 1.0 3.7.5 Hot Swap Sequence The hot swap W400c/2 board, and the host system board that is capable of basic, full, or high- availability hot swap. Table 27 outlays the Hot Swap insertion and extraction sequences.

  • Page 58: Programming Information

    HighWire HW400c/2 User Reference Guide Rev 1.0 PROGRAMMING INFORMATION The HW400c/2 memory map and progra is section. .1 HW400c/2 M emory Map Table 28 shows the m Address Add ss Start (Hex) d (H E000 0000 E000 FFF E100 0000...

  • Page 59: Cpld Registers

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2 CPLD Registers All CPLD (Complex Pr are accessible by the system controller. 1: All reserved locations and bits are set to zero after a reset to the CPLD. : Check individual register descriptions for default register values after reset.

  • Page 60: Clock Select Register (Csr)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.1 Clock Select Register (CSR) The Clock Select Register (CSR) is a Read/Write register. This register selects whether or not the H.110 Controller (T8110L) drives the H.110 and local CT bus sync and clock. The register bit definitions are shown in Table 30.

  • Page 61: Board Status Register (Bsr)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.2 Board Status Register (BSR) The Board Status Register (BSR) is a Read/Write register. This register reflects the presence of the CT bus (H.110, see Section 3.3.3), the state of the FACT (Factory) mper in J7 (see Figure 9), and can control and report the state of two of the status EDS on the front panel (see Figure 3).

  • Page 62: Memory Option Register (Mor)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.4 Memory Option Register (MOR) The Memory Option Register (MOR) is a Read-Only register. This register reports the presence and size of the M-Systems Disk on Chip device. able 33. Memory Option Register (MOR) Offset Address 0x07...

  • Page 63: Ptmc Reset Register (Prr)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.6 PTMC Reset Register (PRR) PTMC Reset Register (PRR) is a Read/Write register that asserts and de-asserts reset to the individual PTMC sites. The Reset pulse applied to the PTMC modules must conform to the PCI standard, that is, it must be at least 10 PCI clock cycles long.

  • Page 64: Board Option Register (Bor)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.8 Board Option Register (BOR) The Board Option Register (BOR) is a Read Only register. This register indicates the configuration and product type. Bit 5, bit 2, bit 1 and bit 0 are always “1”...

  • Page 65: Pci Status Register (Psr)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.10 PCI Status Register (PSR) The PCI Status Register (PSR) is a Read-Only register and indicates the status of host and local PCI buses. The bits of this register are defined as follo Table 39.

  • Page 66: Hardware Revision Register (Hrr)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.12 Hardware Revision Register (HRR) The Hardware Revision Register (HRR) is a Read-Only register. It contains the current major and minor (optional) hardware revision for the board. Table 41. Hardware Revision Register (HRR) Offset Address...

  • Page 67: Pll Configuration Register B (Pllb)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.14 PLL Configuration Register B (PLLB) The PLL Configuration Register B (PLLB) is a Read-Only register. It contains the settings for the System bus and Device bus (external) PLLs. Reading this regis long with PLLA) can help software determine the CPU operating frequency, as well a s the Device bus operating frequency.

  • Page 68: Led Register B (Ledb)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.15 LED Register B (LEDB) The LED Register B (LEDB) is a Read/Write register. It contains controls for the eight on-board surface-mount LEDs as well as the optional LAN status LEDs. Table 44. LED Register B (LEDB) Offset Address 0x14...

  • Page 69: Device Control Register (Dcr)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.16 Device Control Register (DCR) The Device Control Register (DCR) is a Read/Write register, which controls the CP timer enable and three resets. The Reset pulse applied to any device must conform to the specifications of that particular device.

  • Page 70: Warm Reset Register (Wrr)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.18 Warm Reset Register (WRR) The Warm Reset Register is a Read/Write Register. Writing a value of 0x77 to the Warm Reset Register initializes a Warm Reset. The actual reset signal is driven by the CPLD 1-2 milliseconds after writing 0x77 to the WRR.

  • Page 71: Spi Read Byte Offset Register (Sor)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.21 SPI Read Byte Offset Register (SOR) The SPI Byte Offset Select Register is a Read/Write register. It is used for selectin the desired byte offset (within the register selected by the SAR) when rea e BCM5388 Ethernet Switch SPI port.

  • Page 72: Write Byte Count Register (Wbc)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.23 Write Byte Count Register (WBC) The Write Byte Count Register is a Read/Write register. It is used for setting the number of bytes to be written when writing to the BCM5388 SPI port.

  • Page 73: Spi Error And Status Register (Sesr)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.25 SPI Error and Status Register (SESR) The SPI Error Register is a Read Only register. SBSY clears when the previous operation is completed, and the SPIFER, RACKER, and BYTER error flags clear when the next operation is started.

  • Page 74: Eeprom Operation/Status Register (Eosr)

    EEPROM word addresses 0x00-0x0F without the FAC jumper stalled results in a write error, setting WERR bit. These addresses are reserved for SBE board ID identification and are programmed by SBE during board manufacturing. ble 57. EEPROM Operation/Status Register (EOSR) Offset Address 0x2...

  • Page 75: Eeprom Data Registers (Edr0 - Edr1)

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.28 EEPROM Data Registers (EDR0 – EDR1) EEPROM Data Registers are Read/Write registers. The data bytes to be read from or written to the serial EEPROM. Values written to EDR0-1 are stored in an internal shift register and cannot be read k by re ading EDR0-1.

  • Page 76: Writing An Eeprom Address

    HighWire HW400c/2 User Reference Guide Rev 1.0 4.3.2 Writing an EEPROM Address A. Check the EBSY flag in the EEPROM Oper Section 4.2.26). If set to “0”, proceed to the next ste B. Write a “0x01” to the EOSR. This starts the Write Enable operation (EWEN).

  • Page 77: Reading Bcm5388 Register

    HighWire HW400c/2 User Reference Guide Rev 1.0 RBC to a size that exceeds the actual register size will result in an incorrect read valu No error flags will be set to indicate these types of errors. When reading or writing the BCM5388 registers, ensure that the regist re in strict accordance with the BCM5388 data sheet.
  • Page 78 HighWire HW400c/2 User Reference Guide Rev 1.0 D. Write the bytes to be written into the SPI Data Reg 4.2.24), beginning with LSB in SDR0. E. Set the Write Byte Count Register (WBC, see Section 4.2.23) to the count of bytes to write.

  • Page 79: Linux On The Hw400C/2 And Host System

    GenericHDLC WAN stack enabled. The Gentoo Linux kernel may be delivered as a generic compressed archive that can be downloaded, or on a CD-ROM available from SBE. The compressed image is the tar gzip (.tgz) format, the form typically used for software obtained from the SBE website at http://www.sbei.co To summarize, the Linux kernel for the HW400c/2 is installed on a host system that also runs Linux.

  • Page 80: Network And System Configuration

    Before installing the Linux kernel you should read any available Release Notes. October 10, 2006 evelopment Linux installation. If you are putting together a on class. copy Gentoo Linux for the SBE HW400c/2 from SBE’s ftp archive. _file> www.gentoo.org Copyright 2006, SBE, Inc.

  • Page 81: Configuring The Host System

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.4 Configuring the Host System The next few sections describe daemons and system services that must be installed and correctly activated in order to boot the Linux kernel on the HW400c/2 and subsequently compile applications for the HW400 5.4.1 Modifying...

  • Page 82: Configuring Host Tftp Services

    5.4.3 Configurin g Host tftp services One of the ways the SBE HW400c/2 boots is by using the Trivial File Transfer Protocol (TFTP) to download a kernel image to the board. This server be available on the system on which you are hosting the Gentoo Linux kernel.

  • Page 83: Configuring Tftp With Inetd

    HighWire HW400c/2 User Reference Guide Rev 1.0 text editor to remove the hash mark on each line that contains the string tftp. Active TFTP entries in /etc/services should look like the following: tftp 69/tcp tftp 69/udp Depending on the Linux distribution and version you are using on the host, Linux systems typically use one of two mechanisms to activate and manage network servers such as TFTP servers.
  • Page 84 Gentoo Linux archive. # cp /opt/gentoo/usr/src/linux/arch/ppc/boot/images/uImage\ /tftpboot/. You can now proceed to the Section 5.4.6 to set up communications with your SBE HW400c/2 b October 10, 2006 0 1152 356 do_select S ? 0:00 inetd...

  • Page 85: Configuring Tftp With Xinetd

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.4.5 Configuring tftp with xinet The servers that can be managed by the xinetd are each listed in a server-specific configuration file located in the directory /etc/xinetd.d. The file for the TFTP server is aptly named tftp, and looks like the following:...

  • Page 86: Configuring A Bootp Server

    Section 5.4.6 to set up communications with your SBE oad and boot the Linux kernel. up table called bootptab. At power up, the HW400c/2 will 15278 25183...

  • Page 87: Booting The Hw400C/2

    HighWire HW400c/2 User Reference Guide Rev 1.0 If you don’t already have one, the easiest way to create a bootp server is to have it reside on the same LAN subnet as the HW400c/2. Creating bootp relay agents for bootp servers on different o set up a server with BOOTP with TFTP ability in a standard Linux box, uncomment (or add) these two lines in inetd.conf)

  • Page 88: U-Boot, Universal Bootloader

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.1 U-boot, Universal Bootloader The HW400c/2 uses a boot ROM based on Das U-boot. U-boot (Universal Bootloader) is an off-the-shelf freeware package found on Sourceforge.net. Ma commands and environment variables are available in U-boot to facilitate the f the Linux kernel from various locations.

  • Page 89: U-Boot Environment Variables

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.1.2 U-boot environment variables U-boot has large number of environment va be used with the HW400c/2, only a few are necessary for the boot process. A complete list of U-boot environment variables can be found in Appendix B .
  • Page 90 HighWire HW400c/2 User Reference Guide Rev 1.0 baudrate ethaddr he MAC address is assigned by SBE at the time of manufacture, stored in non-volatile memory, and must not be altered. Any attempt to change the MAC add ipaddr serverip gatewayip etmask Fixed environment variables.

  • Page 91: Power Up Call Trace

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.1.3 Power up call trace For reference purposes, this is a summary of the power up calls after U-boot runs and jumps to _start. _start (…/arch/ppc/kernel/head.S) early_init (…/arch/ppc/kernel/setup.c) start_here (…/arch/ppc/ke machine_init (…/arch/ppc/kernel/setup.c) start_kernel (…/init/main.c) setup_arch (…/arch/ppc/kernel/setup.c)

  • Page 92: Booting With Tftp

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.2 Booting with tftp Tftp boot requires a tftp boot server and an NFS mounted file syste dress is not assigned to the HW400c/2 through the boot console, a bootp server may also be necessary. The bootp server, tftp server, and the NFS server functions may or may not be the same machine.

  • Page 93: U-Boot Parameters For Tftp With Static Ip Address

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.2.2 U-boot pa rameters for tftp with static IP address The following example shows U-boot parameters necessary for a boot w ith a static IP address assigned using the U-boot command: # set ipaddr <ip address>...
  • Page 94 HighWire HW400c/2 User Reference Guide Rev 1.0 TFTP from server 10.0.0.5; our IP address is 10.0.0.10 Filename 'uImage'. Load address: 0x400000 Loading: ######################################## ################################## ################################################# ################################################# ############################### done Bytes transferred = 1551015 (17aaa7 hex) ## Booting image at 00400000 ...
  • Page 95 HighWire HW400c/2 User Reference Guide Rev 1.0 HDLC support module revision 1.17 Cronyx Ltd, Synchronous PPP and CISCO HDLC (c) 1994 Linux port (c) 1998 Loading Adaptec I2O Detecting Adaptec I2O RAID controllers... megaraid cmm: 2.20.2.0 (Release Date: Thu Aug 19 09:58:33 EDT 2004) megaraid: 2.20.4.0 (Release Date: Mon Sep 27 22:15:07 EDT 2004)

  • Page 96: Booting With Disk On Chip

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.3 Booting with Disk on Chip A Disk-on-Chip (DoC) flash file system device is used on the HW400c/2 for data storage. DoC is a high-density flash device manufactured by M-Systems Incorporated, and has a data bus width of 16 bits. The 128 MB device is standard on...

  • Page 97: Creating A Uramdisk Image

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.3.2 Creating a uRamdisk Image uRamdisk is a tiny kernel image needed to boot uImage from the Disk on Chip. uRamdisk has the same intent as a ramdisk on other linux platforms. It brings up necessary drivers needed to access the real kernel image (uImage).

  • Page 98: Compiling The Kernel (Uimage)

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.6 Compiling the Kernel (uImage) Unlike other some other Linux distributions, the Gentoo kernel can be nativel compiled on the HW400c/2 following standard Linux kernel build procedures. Rebuilding the kernel is necessary when changing the kernel configuration parameters.

  • Page 99: Gentoo Application Packages Management

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.6.1 Gentoo Application Packages Management “Portage” is the name of Gentoo's package management system. All Gentoo packages can be found under /usr/portage. If a package is needed, for exam firewall or ftp services, it can be found in the portage directory. Some of the packag...

  • Page 100: Enable Remote Login With Ssh

    HighWire HW400c/2 User Reference Guide Rev 1.0 5.6.1.2 Enable remo te login with ssh Gentoo Linux installs sshd by default, but it is not enabled. Before starting ssh server look through the configuration thing that you should consider setting is lo ins as root, which means that in order ular user (in the wheel group) and then su.

  • Page 101: Linux Device Drivers

    HighWire HW400c/2 User Reference Guide Rev 1.0 # rc-update add vsftpd default You may also want to modify your /etc/vsftpd/vsftpd.conf file configuration and security parameters. ome of the basic parameters in dirmessage_enable=YES ner_file=/etc/v chown_uploads=NO xferlog_enable=YES idle_session_timeout=600 data_connection_timeout=120 _uploa ascii _download_enabl...

  • Page 102: Appendix Aipmi Getdeviceid

    HighWire HW400c/2 User Reference Guide Rev 1.0 Appendix A IPMI GetDeviceID Response message data to IPMI GetDeviceID request. Values in bold are changes from default Zircon firmware response message. Byte offset Description IPMI Definition Completion code (returned in message, not part of data)

  • Page 103: U-Boot Environment Variables

    HighWire HW400c/2 User Reference Guide Rev 1.0 Appendix B U-Boot Environment variables Das U-boot was created by Wolfgang Denk as an ope complete U-boo t manual can be found at This appe ndix i s a brief list of known U-boot environment variable command or ? at the debug prompt.
  • Page 104 HighWire HW400c/2 User Reference Guide Rev 1.0 mtest - simple RAM test - memory write (fill) - boot image via network using NFS protocol - memory modify (constant address) - list and access PCI Configuraton Space ping - send ICMP ECHO_REQUEST to network host...

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