rtd FPGA35S6045HR Xilinx Spartan-6 FPGA Manuals

rtd FPGA35S6045HR Xilinx Spartan-6 FPGA Manuals

Manuals and User Guides for rtd FPGA35S6045HR Xilinx Spartan-6 FPGA. We have 1 rtd FPGA35S6045HR Xilinx Spartan-6 FPGA manual available for free PDF download: User Manual

Rtd FPGA35S6045HR User Manual

Rtd FPGA35S6045HR User Manual (31 pages)

FPGA Module

Brand: Rtd | Category: Computer Hardware | Size: 1 MB

Table of Contents

Revision History
3
Table of Contents
4
1 Introduction

7
- Product Overview
  7
- Board Features
  7
- Ordering Information
  8
- Contact Information
  8
  - Sales Support
    8
  - Technical Support
    8
  - Table 1: Ordering Options
    8
2 Specifications

9
3 Board Connection

10
- Board Handling Precautions
  10
- Physical Characteristics
  10
- Figure 1: Board Dimensions
  10
- Connectors and Jumpers
  11
- Steps for Installing
  16
- Figure 4: Example 104™Stack
  16
4 IDAN Connections

17
- Module Handling Precautions
  17
- Physical Characteristics
  17
- Figure 5: IDAN Dimensions
  17
- Connectors and Jumpers
  18
  - P2 & P3: Digital I/O Connector
    18
  - Table 11: P2 and P3 Pin Assignments
    18
  - P4: High Speed Digital I/O Connector
    19
  - Table 12: P4 Pin Assignments
    19
  - Bus Connectors
    21
    
    CN1 (Top) & CN2 (Bottom): Pcie Connector
    21
  - Jumpers
    21
    
    JP1, JP2, JP3, JP4, JP5, & JP6: Pull Up/Pull down Jumper
    21
    
    JP7: Reserved
    21
  - Solder Jumper
    21
    
    B1: Pull up Voltage
    21
    
    B2: Pull up Voltage
    21
    
    Table 13: Pull Up/Pull down Jumper Options
    21
    
    Table 14: B1 Pull up Voltage
    21
- Steps for Installing
  22
- Figure 6: Example IDAN System
  22
5 Functional Description

23
- Oscillator
  23
- Eeprom
  23
- Ddr2 Sram
  23
- Figure 7: FPGA35S6 Block Diagram
  23
- Digital I/O
  24
- Figure 8: CN4/CN9 Digital I/O Circuitry
  24
6 Register Address Space

25
- BAR0 - FPGA Example Register Map
  25
  - R_ID (Read)
    25
  - R_STATUS (Read)
    25
  - R_EEPROM (Read/Write)
    25
  - Table 16: FPGA Example Register Map
    25
  - R_PORT0_IN (Read)
    26
  - R_PORT0_OUT (Write)
    26
  - R_PORT0_DIR (Write)
    26
  - R_PORT1_IN (Read)
    26
  - R_PORT1_OUT (Write)
    26
  - R_PORT1_DIR (Read/Write)
    26
  - R_PORT2L_IN (Read)
    26
  - R_PORT2L_OUT (Write)
    26
  - R_PORT2L_DIR (Read/Write)
    26
  - R_PORT2H_IN (Read)
    26
  - R_DDR_STATUS (Read)
    27
7 Troubleshooting

28
8 Additional Information

29
- PC/104 Specifications
  29
- PCI and PCI Express Specification
  29
9 Limited Warranty

30

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