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rtd DM35425HR User Manual

Pci express data acquisition board
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DM35425HR
PCI Express Data Acquisition Board
User's Manual
BDM-610010047 Rev E

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  • Page 1 DM35425HR PCI Express Data Acquisition Board User’s Manual BDM-610010047 Rev E...
  • Page 2 Failure to follow the instructions found in this manual may result in damage to the product described in this manual, or other components of the system. The procedure set forth in this manual shall only be performed by persons qualified to service electronic equipment. Contents and specifications within this manual are given without warranty, and are subject to change without notice. RTD Embedded Technologies, Inc. shall not by persons qualified to service electronic equipment.

  • Page 3: Table Of Contents

    Block Diagram................................... 24 Control Interface with DMA Engine............................24 Analog input ....................................24 5.3.1 Initialization 5.3.2 Simplified block diagram of analog input Single-Ended Input Mode Differential Input Mode Full-Scale Input Range Bipolar/Unipolar Mode | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.
  • Page 4 CLK_DIV_CNTR (Read Only) 6.3.10 PRE_TRIGGER_CAPTURE (Read/Write) 6.3.11 POST_STOP_CAPTURE (Read/Write) 6.3.12 SAMPLE_CNT (Read Only) 6.3.13 INT_ENA (Maskable Read/Write) 6.3.14 INT_STAT (Read/Clear) 6.3.15 CLK_BUSn 6.3.16 CHn_FRONT_END_CONFIG (Maskable Read/Write) 6.3.17 CHn_FIFO_DATA_CNT (Read) 6.3.18 CHn_FILTER (Read/Write) | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.
  • Page 5 BAR2 – External Clocking Functional Block ..........................51 6.6.1 FB_ID (Read-Only) 6.6.2 FB_DMA_CHANNELS (Read -Only) 6.6.3 FB_DMA_BUFFERS (Read-Only) 6.6.4 EXT_CLK_IN (Read-Only) 6.6.5 EXT_CLK_GATE_IN (Read Only) 6.6.6 EXT_CLK_DIR (Read/Write) 6.6.7 EXT_CLK_EDGE (Read/Write) 6.6.8 EXT_CLK_PWn (Read/Write) 6.6.9 EXT_CLKn_CFG (Read/Write) | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.
  • Page 6 Figure 7: Example IDAN System .................................... 23 Figure 8: DM35425 Block Diagram..................................24 Figure 9: Filter Response with each ORDER Value ............................... 40 Figure 10: DM35425HR Trimpots ................................... 53 Table of Tables Table 1: Ordering Options ......................................8 Table 2: Operating Conditions ....................................10 Table 3: Electrical Characteristics ..................................
  • Page 7 Table 27: ADC Bit Weights, Unipolar..................................55 Table 28: Trimpots for Calibrating ADC Gain ................................. 55 Table 29: DAC Bit Weights ..................................... 56 Table 30: Trimpots for Calibrating DAC Gain ................................. 56 | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 8: Introduction

    The Intelligent Data Acquisition Node (IDAN™) building block can be used in just about any combination with other IDAN building blocks to create a simple but rugged 104™ stack. This module can also be incorporated in a custom-built RTD HiDAN™ or HiDANplus High Reliability Intelligent Data Acquisition Node.

  • Page 9: Technical Support

    If you are having problems with you system, please try the steps in the Troubleshooting section of this manual on page 57. For help with this product, or any other product made by RTD, you can contact RTD Embedded Technologies technical support via the following methods: Phone: 1-814-234-8087 Monday through Friday, 8:00am to 5:00pm (EST).

  • Page 10: Specifications

    Channel to Channel Cross Talk No Channel Delay -20.46 ½ Sample Delay -41.68 Sample Delay -59.54 2 Sample Delay -66.41 Gains 0.5,1,2,4,8 Digital to Analog Converter Full-Scale Analog Output Voltage G = 1 4.99756 | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.
  • Page 11 Output Current Slew Rate V/µs Gains Output Impedance Ω Digital I/O Input High Voltage Input Low Voltage -0.5 Output Low Voltage = 12mA Output High Voltage = -12mA 5V Output CN3, CN4 | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 12: Analog Input Fft Plots

    In Figure 2 you can see a histogram of samples from sampling a grounded input in +/-10 V, differential input range. The number of samples is 32768. 30000 25000 20000 15000 10000 5000 Figure 2: Histogram | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 13: Board Connection

    Physical Characteristics  Weight: Approximately 55 g (0.12 lbs.)  Dimensions: 90.17 mm L x 95.89 mm W (3.550 in L x 3.775 in W) Figure 3: Board Dimensions | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 14: Connectors And Jumpers

    The PCIe connector is the connection to the system CPU. The position and pin assignments are compliant with the PCI/104-Express Specification. (See PC/104 Specifications on page 58) The DM35425 is a “Universal” board, and can connect to either a Type 1 or Type 2 PCIe/104 connector. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 15: Dm35425 External I/O Connectors

    DIO11 DIO2 DIO10 DIO2 DIO10 DIO1 DIO9 DIO1 DIO9 DIO0 DIO8 DIO0 DIO8 EXT_CLK_2 EXT_CLK_2 EXT_CLK_3 EXT_CLK_4 EXT_CLK_3 EXT_CLK_4 EXT_CLK_5 EXT_CLK_6 EXT_CLK_5 EXT_CLK_6 EXT_CLK_7 Reserved EXT_CLK_7 Reserved Reserved Reserved Reserved Reserved | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 16: Other Connectors

    EXT_CLK_GATE5 EXT_CLK_GATE6 EXT_CLK_GATE5 EXT_CLK_GATE6 EXT_CLK_GATE7 Reserved EXT_CLK_GATE7 Reserved Reserved Reserved Reserved Reserved Other Connectors CN5 and CN6 are for Factory Use only 3.3.3 UMPERS There are no jumpers on the board. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 17: Steps For Installing

    10. Attach any necessary cables to the PC/104 stack. 11. Re-connect the power cord and apply power to the stack. 12. Boot the system and verify that all of the hardware is working properly. Figure 5: Example 104™Stack | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 18: Idan Connections

    The PCIe connector is the connection to the system CPU. The position and pin assignments are compliant with the PCI/104-Express Specification. (See PC/104 Specifications on page 58) The DM35425 is a “Universal” board, and can connect to either a Type 1 or Type 2 PCIe/104 connector. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 19: External I/O Connectors

    EXT_CLK_5 AIN4-/AIN12 EXT_CLK_6 AIN5+/AIN5 EXT_CLK_7 AIN5-/AIN13 Reserved AIN6+/AIN6 Reserved AIN6-/AIN14 AIN7+/AIN7 Reserved AIN7-/AIN15 AOUT0 AGND AOUT1 AGND AGND AGND DIO7 DIO15 DIO6 DIO14 DIO5 DIO13 DIO4 DIO12 DIO3 DIO11 DIO2 DIO10 | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 20: P3 Connector - 68-Pin Subminiature "D" Female Connector

    EXT_CLK_GATE5 AIN12-/AIN28 EXT_CLK_GATE6 AIN13+/AIN21 EXT_CLK_GATE7 AIN13-/AIN29 Reserved AIN14+/AIN22 Reserved AIN14-/AIN30 AIN15+/AIN23 Reserved AIN15-/AIN31 AOUT2 AGND AOUT3 AGND AGND AGND DIO23 DIO31 DIO22 DIO30 DIO21 DIO29 DIO20 DIO28 DIO19 DIO27 DIO18 DIO26 | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 21: P2 Connector - 62-Pin High Density "D" Female Connector

    Reserved AIN7+/AIN7 Reserved AGND Reserved AGND Reserved DIO15 Reserved DIO5 Reserved DIO12 AIN0-/AIN8 DIO2 AIN2+/AIN2 DIO9 AIN3-/AIN11 EXT_CLK_2 AIN5+/AIN5 EXT_CLK_4 AIN6-/AIN14 EXT_CLK_7 AOUT0 AGND Reserved DIO7 Reserved DIO14 Reserved DIO4 Reserved | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 22: P3 Connector - 62-Pin High Density "D" Female Connector

    Reserved AIN15+/AIN23 Reserved AGND Reserved AGND Reserved DIO31 Reserved DIO21 Reserved DIO28 AIN8-/AIN24 DIO18 AIN10+/AIN18 DIO25 AIN11-/AIN27 EXT_CLK_GATE2 AIN13+/AIN21 EXT_CLK_GATE4 AIN14-/AIN30 EXT_CLK_GATE7 AOUT2 AGND Reserved DIO23 Reserved DIO30 Reserved DIO20 Reserved | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 23: Steps For Installing

    10. Attach any necessary cables to the IDAN system. 11. Re-connect the power cord and apply power to the stack. 12. Boot the system and verify that all of the hardware is working properly. Figure 7: Example IDAN System | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 24: Functional Description

    ±12V overvoltage input protection to the analog connector. The DM35425 has a programmable input. This provides the user the ability to select single-ended/differential input, full-scale input range, unipolar/bipolar input, and channel sampling delay. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 25: Analog Input

    ADC - pin. In most cases, the board ground must still be attached to the device that is generating the input signal. When using the differential mode, you should install a 10 kΩ resistor pack at locations RN2 and RN18 on the DM35425HR to provide a reference to ground for signal sources without a separate ground reference.

  • Page 26: Bipolar/Unipolar Mode

    The DM35425 uses a multiplexed input to allow a max of 32 single-end/16-differential channels using one ADC. This module burst samples all enabled channels after each pacer clock pulse, starting at the first enabled channel and sequentially every enabled channel afterwards. Due to | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 27: Analog Output

    Refer to section 6.4.15 for more information about FPGA registers. CHn_Front_End_Config [DABIP_UNI] Refout CHn_Front_End_Config [GAIN] Offset From FPGA AOUTn Vout DAC: 12 Bit @ 200 KHz CHn_Front_End_Config [DAC_Enable] | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 28: Advanced Digital I/O

    When the clock pin is set to input, when the clock pin receives a rising edge and the valid pin is high all 32 bits on data will be written to the IN FIFO. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 29: External Clocking

    Set the sample rate (CLK_DIV_CNTR) Set the Pre and/or Post Capture counters (PRE_TRIGGER_CAPTURE, POST_STOP_CAPTURE) Set the ADC to the Reset state (MODE = Reset) Start the DMA 10. Start the ADC (MODE = Go) | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 30: Register Address Space

    Channel Threshold Inverted– All of the channels are within the High and Low threshold. 0x0A: CLK_BUS2 Inverted 0x0B: CLK_BUS3 Inverted 0x0C: CLK_BUS4 Inverted 0x0D: CLK_BUS5 Inverted 0x0E: CLK_BUS6 Inverted 0x0F: CLK_BUS7 Inverted | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 31: Bar0 - General Board Control

    This register contains the format ID that is used in this board. The current value is 0x01. 6.1.5 GBC_PDP (R This register contains the PDP number for this board. 6.1.6 GBC_BUILD (R This register contains a unique 32-bit build number for the FPGA code. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 32: Gbc_Sys_Clk_Freq (Read Only)

    This is the offset from the beginning of BAR2 that this Functional Block resides in. 6.1.12 _DMA (R FFSET This is the offset from the beginning of BAR2 that the Functional Block DMA Registers reside in. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 33: Bar2 - Functional Block Standard Dma

    It specifically aids the transition to the Clear state. When transitioning to Clear, the user should wait until FB_DMAm_Last_Action indicates that the Clear has been processed before initiating any other Action changes. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 34: Fb_Dmam_Setup (Read/Write)

    This is the amount of data available in the read FIFO in bytes. Software can use this to determine when the FIFO is empty. A value of 0x3FC indicates that there are 1020 or more bytes of data available. B15: RD_EMPTY- ‘1’ indicates that the read FIFO is empty | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 35: Fb_Dmam_Wr_Fifo_Cnt (Read-Only)

    The DMA engine will set the error bit and PAUSE if it is ready to use this descriptor and the Used bit is set, unless the IgnoreUsed bit is set. The bits are cleared by writing 0x00 to the byte. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 36: Bar2 - Adc Functional Block

    … FB + 0x334 CH_FIFO_ACCESS (ADC Channel n) + (0x04 * n) 6.3.1 FB_ID (R This is the functional block ID. This register should read 0x01031000 for the ADC functional block. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 37: Fb_Dma_Channels (Read -Only)

    Divider for the pacer clock. Pacer Clock Frequency = (Clk_Src_Frequency) / (1 + CLK_DIV). If synchronizing with the pacer clock from another Function Block (by using one of the CLK_BUS signals), this is typically set to 0. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 38: Clk_Div_Cntr (Read Only)

    A function block can drive multiple different Clock Buses. However, a Clock Bus N should not be driven by more than one function block at the same time or the clock signal will be undefined. B[7:0]: 0x00: Disables Clock Source 0x80: Sample – A sample has been taken. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 39: Chn_Front_End_Config (Maskable Read/Write)

    6.3.18 _FILTER (R RITE The programmable digital filter provides a single pole Infinite Impulse Response (IIR) filter on each channel. This a unity-gain filter. The filtered data has a value of: | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 40: Chn_Thresh_Stat(Read/Clear)

    Signed 32-bit value indicating the low threshold. If the input signal drops below this value, an interrupt or clock can be generated until the signal goes above this value. The 3 least significant bits are ignored from the actual threshold value. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 41: Chn_Thresh_High (Read/Write)

    This register provides direct access to the DMA FIFO. It can be used to access the data without the use of the DMA engine. The DMA engine for this channel must be set to “Pause.” Each register access advances to the next sample. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 42: Bar2 - Dac Functional Block

    Descriptor Registers. 6.4.3 FB_DMA_BUFFERS (R This register contains the number of Buffer Descriptors in each DMA Channel. 6.4.4 TATUS RITE Selects the current mode of operation and indicates its triggering status. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 43: Clk_Src (Read/Write)

    Number of conversions to send after the Stop Trigger. 6.4.11 CONVERSION_CNT (R Total number of conversions. This only increment in while in “Converting/Waiting for stop trigger” and “Output Post-Stop buffer” state. It also continues counting after a Re-Arm. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 44: Int_Ena (Maskable Read/Write)

    1 = Gain of 2 Table 20: DAC Full-Scale Settings GAIN Unipolar Mode Bipolar Mode ±5V 0-5V 0-10V ±10V NOTE: The Front End may take up to 100us to settle after writing to this register. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 45: Chn_Fifo_Data_Cnt (Read)

    This register provides direct access to the DMA FIFO. It can be used to access the data without the use of the DMA engine. The DMA engine for this channel must be set to “Pause.” Each register access advances to the next sample. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 46: Bar2 - Advanced Digital I/O Functional Block

    0x01: Paused. Sampling is stopped, but the counters and triggering state machine maintain their state. 0x02: Go, Single-Shot. After converting the Post-Stop number of values, converting stops. The Mode must be set back to RESET in order to convert more values. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 47: Clk_Src (Read/Write)

    The current value of the Clock Divide Counter. This counter starts at a value of CLK_DIV, and counts down. When it reaches zero, a sample is taken. This is useful when using a slow sample clock. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 48: Pre_Trigger_Capture (Read/Write)

    0x81: Advanced Int 0x82: Pre-Start Buffer Filled 0x83: Start Trigger 0x84: Stop Trigger 0x85: Post-Stop Buffer Filled 0x86: Sampling has completed and the FIFO is empty (all data transferred to host) | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 49: Dio_Input (Read Only)

    B[30]: P_BUS_READY: When set high, this will output high ready signal once the Digital I/O DMA INPUT FIFO is setup and started. When using the module to send data, set this bit low to receive the ready signal. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 50: Adv_Int_Mode (Read/Write)

    This register provides direct access to the DMA FIFO. It can be used to access the data without the use of the DMA engine. The DMA engine for this channel must be set to “Pause.” Each register access advances to the next sample. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 51: Bar2 - External Clocking Functional Block

    The bits in the register correspond with the External Clocking Gates pins as follows: CLK_BUSn Signal Number EXT_CLK_GATE7 EXT_CLK_GATE6 EXT_CLK_GATE5 EXT_CLK_GATE4 EXT_CLK_GATE3 EXT_CLK_GATE2 6.6.6 EXT_CLK_DIR (R RITE Selects the direction of the External Clocking bits. 0=input, 1=output. All pins default to inputs at power-up. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 52: Ext_Clk_Edge (Read/Write)

    Clock Gated (High): EXT_CLKn will be inputted when the EXT_CLK_GATEn corresponding gate value is high, this doesn’t affect when outputting a clock. 0x82: Clock Gated (Low): EXT_CLKn will be inputted when the EXT_CLK_GATEn corresponding gate value is low, this doesn’t affect when outputting a clock. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 53: Required Equipment

    Any time you suspect inaccurate readings, you can check the accuracy of your conversions using the procedure in this section, and make adjustments as necessary. Calibration is done with the module installed in your system. Power up the system and let the DM35425HR circuitry stabilize for 15 minutes before calibration.

  • Page 54: Adc Calibration

    0 to +10 V input range. Before making these adjustments, make sure that the module is programmed properly and has been calibrated for bipolar ranges. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 55: Unipolar Range Ideal Bit Weight

    Should you find it necessary to check any of the programmable gain settings, the following table will show the proper trimpot to adjust. Table 28: Trimpots for Calibrating ADC Gain Gain Trimpot | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 56: Dac Calibration

    +4.88 0000 0000 0001 -4997.56 +1.22 -9995.12 +2.44 0000 0000 0000 -5000.00 0.00 -10000.00 0.00 Table 30: Trimpots for Calibrating DAC Gain Trimpot AOUT0 TR11 AOUT1 TR12 AOUT2 TR13 AOUT3 TR14 | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 57: Troubleshooting

    If problems persist, or you have questions about configuring this product, contact RTD Embedded Technologies via the following methods: Phone: +1-814-234-8087 E-Mail: techsupport@rtd.com Be sure to check the RTD web site (http://www.rtd.com) frequently for product updates, including newer versions of the board manual and application software. | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 58: Additional Information

    A copy of the latest PC/104 specifications can be found on the webpage for the PC/104 Embedded Consortium: www.pc104.org PCI and PCI Express Specification A copy of the latest PCI and PCI Express specifications can be found on the webpage for the PCI Special Interest Group: www.pcisig.com | www.rtd.com DM35425HR User’s Manual RTD Embedded Technologies, Inc.

  • Page 59: 10 Limited Warranty

    During the one year warranty period, RTD Embedded Technologies will repair or replace, at its option, any defective products or parts at no additional charge, provided that the product is returned, shipping prepaid, to RTD Embedded Technologies. All replaced parts and products become the property of RTD Embedded Technologies.
  • Page 60 RTD Embedded Technologies, Inc. 103 Innovation Boulevard State College, PA 16803 USA Telephone: 814-234-8087 Fax: 814-234-5218 www.rtd.com sales@rtd.com techsupport@rtd.com Copyright 2017 by RTD Embedded Technologies, Inc. All rights reserved.

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