Renesas R-Car V3M Manuals

Manuals and User Guides for Renesas R-Car V3M. We have 1 Renesas R-Car V3M manual available for free PDF download: Manual

Renesas R-Car V3M Manual (56 pages)

Starter Kit

Brand: Renesas | Category: Automobile Electronics | Size: 10 MB

Table of Contents
8
Introduction
12
General Function
12
Figure 1. ASK-RCAR-V3M-WS10 Starter Kit Top View
12
Figure 2. ASK-RCAR-V3M-WS10 Starter Kit Bottom View
12
Table 1. Board Functions
12
Power Requirement
14
Order Codes
14
Operating Conditions
14
Figure 3. Power Connector Definition
14
Table 2. Order Codes
14
V3M Starter Kit Block Diagram
15
Figure 4. V3M Starter Kit Block Diagram
15
Board Releases
16
Fan Connector Pinout
16
Table 3. Fan Connector Pinout
16
Soc Mode
17
Figure 5. CPLD and SW4 Multiplexing Diagram
17
Figure 6. SW4 or CPLD Selection
18
Table 4. Soc Mode
18
Connectors / Leds / Components
19
Connectors
19
Figure 7. Connectors Placement Top View
19
Figure 8. Connectors Placement Bottom View
19
Table 5. Connectors
19
JTAG Connector
20
Switches
20
Figure 9. Switches Placement Top View
20
Table 6. JTAG Connector Pinout
20
Table 7. Switch Description
20
Leds
21
Figure 10. Top View of the Board. Leds Position
21
Table 8. Leds Description
21
Components
22
Figure 11. Component Position on Top Side
22
Figure 12. Component Position on Bottom Side
22
Table 9. List of Components
22
V3M Starter Kit Configuration Tool
23
First Use
23
Configuration Tool Overview
23
Figure 13. Device Manager View. Check for Comx Ports
23
Volatile/Non-Volatile
24
Terminal Blocking Virtual COM Ports
24
SCIF Disabled by Hardware
24
Figure 14. V3M Starter Kit Configuration Tool
24
Figure 15. Routing SCIF0 to Com-Express Connector
25
Flash Memory Selection
26
Multiplexing Drawing
26
Flash Memory Selection (Via CPLD/GUI)
26
Figure 16. Flash Memories Multiplexing Drawing
26
Boot Memory Selection
27
Figure 17. Flash Memory Selection
27
Figure 18. Mode Settings by Register or by DIP SW4 Selection
27
Figure 19. Soc Mode Interface
27
Selection Via SW4 Switch
28
Figure 20. Write CPLD
28
Table 10. Boot Source Selection
28
Emmc Memory
29
Figure 21. Emmc Block Diagram
29
Lvds
30
Multiplexing Drawing
30
Selection (Via CPLD/GUI)
30
Figure 22. LVDS Path Multiplexing
30
Figure 23. LVDS and HDMI Selection Using the Configuration Tool
31
Trace Connector
32
Pinout
32
HSSTP over LVDS Pins
32
Table 11. HSSTP Connector Pinout
32
Ethernet
33
Multiplexing Drawing
33
Selection (Via CPLD/GUI)
33
Figure 24. Ethernet RGMII Interface Multiplexing
33
Figure 25. Ethernet Selection
33
Software Leds
34
LED 6 / LED 7 / LED 8 Switching (Via CPLD)
34
Figure 26. LED Switching
34
Software DIPSW
35
Drawing of Configuration
35
Figure 27. SW5 Drawing of Configuration
35
SW5 Available Depending on CPLD
36
Figure 28. SW5 Switching by CPLD
36
Power Switching for Domains VDDQ_DU and VDDQ_VIN01
37
Overview
37
Drawing of Configuration
37
Power up Sequence for 3.3V
37
Figure 29. Power Switching
37
Figure 30. Power-Up Sequence
37
Power Settings Configuration
38
Figure 31. VDDQ_VIN01 Voltage at Start-Up When Set to 3.3V
38
Figure 32. Power Settings Configuration
38
Reset
39
Drawing of Configuration
39
Figure 33. Reset Drawing of Configuration
39
Serial Communications
40
Overview
40
SCIF0 Block Diagram
40
Figure 34. SCIF0 Block Diagram
40
Booting by SCIF0 (Serial Interface)
41
Booting Procedure
41
Terminal
41
Figure 35. Boot Source Selection
41
Figure 36. Terminal Configuration
41
Uploading Mini-Monitor
42
Figure 37. Ready to Receive Code
42
Figure 38. Tera-Term. Send Mini-Monitor to the System RAM
42
Figure 39. Upload Process
42
Figure 40. Command Terminal
43
Procedure for Flashing On-Board QSPI and Hyper-Flash Memories
44
Hardware Set-Up
44
QSPI Flash Erasing
44
Figure 41. QSPI Device Selection
44
Writing the Boot Loader (IPL) to the QSPI (Sector 1)
45
Figure 42. Mini-Mon Memory Erase
45
Figure 43. Memory Erase
45
Figure 44. Mini-Mon Load Program to QSPI Flash
45
Hyper-Flash Erasing
46
Figure 45. Program Area Selection
46
Figure 46. QSPI Device Selection
46
Writing the Boot Loader (IPL) to the Hyper-Flash (Sector 1)
47
Figure 47. Memory Erase Process
47
V3M Device Hardware Pin Allocation
48
GPIO Table
48
Table 12. GPIO Table
48
Daughter Boards
51
Figure 48. Daughter Board Example
51
List of Known Limitations
52
QSPI Speed Limitation
52
Emmc Availability
52
Initial Power-Up
52
HDMI EDID Read Errors
52
Multiplexors and Switches
52
CPLD Updates
52
Attachments
53
Schematic
53
Mechanical Drawing
53
Com-Express Pin out
53

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