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PI7C7100
Pericom PI7C7100 Manuals
Manuals and User Guides for Pericom PI7C7100. We have
1
Pericom PI7C7100 manual available for free PDF download: Manual
Pericom PI7C7100 Manual (132 pages)
3-Port PCI Bridge
Brand:
Pericom
| Category:
PCI Card
| Size: 2.6 MB
Table of Contents
Table of Contents
3
Introduction/Product Features
9
PI7C7100 on the System Board
10
PI7C7100 Block Diagram
11
Signal Definitions
12
Signal Types
12
Signals
12
Primary Bus Interface Signals
12
Secondary Bus Interface Signals
14
Clock Signals
16
Miscellaneous Signals
16
JTAG Boundary Scan Signals
16
Power and Ground
17
PI7C7100 PBGA Pin Listing
17
PCI Bus Operation
21
Types of Transactions
21
Single Address Phase
22
Device Select (DEVSEL#) Generation
22
Data Phase
22
Write Transactions
22
Posted Write Transactions
22
Write Transaction Forwarding
22
Memory Write and Invalidate Transactions
23
Delayed Write Transactions
23
Write Transaction Address Boundaries
24
Buffering Multiple Write Transactions
24
Fast Back-To-Back Write Transactions
24
Write Transaction Disconnect Address Boundaries
24
Read Transactions
25
Prefetchable Read Transactions
25
Non-Prefetchable Read Transactions
25
Read Pre-Fetch Address Boundaries
25
Delayed Read Requests
26
Delayed Read Completion with Target
26
Delayed Read Completion on Initiator Bus
26
Read Transaction Pre-Fetching
26
Configuration Transactions
27
Type 0 Access to PI7C7100
27
Type 1 to Type 0 Conversion
28
Type 1 to Type 1 Forwarding
29
Special Cycles
30
Transaction Termination
30
Master Termination Initiated by PI7C7100
31
Master Abort Received by PI7C7100
31
Target Termination Received by PI7C7100
32
Delayed Write Target Termination Response
32
Posted Write Target Termination Response
32
Delayed Read Target Termination Response
33
Target Termination Initiated by PI7C7100
34
Target Retry
34
Target Disconnect
35
Target Abort
35
Concurrent Mode Operation
35
Address Decoding
36
Address Ranges
36
I/O Address Decoding
36
I/O Base and Limit Address Registers
36
ISA Mode
37
Memory Address Decoding
37
Memory-Mapped I/O Base and Limit Address Registers
38
Prefetchable Memory Base and Limit Address Registers
38
VGA Support
39
VGA Mode
39
VGA Snoop Mode
39
Transaction Ordering
40
Transactions Governed by Ordering Rules
40
General Ordering Guidelines
40
Ordering Rules
41
Data Synchronization
42
Error Handling
43
Address Parity Errors
43
Data Parity Errors
43
Configuration Write Transactions to Configuration Space
43
Read Transactions
44
Delayed Write Transactions
44
Posted Write Transactions
46
Assertion of S_PERR
46
Data Parity Error Reporting Summary
47
Setting the Primary Interface Detected Parity Error Bit
47
Assertion of P_SERR# for Data Parity Errors
52
System Error (SERR#) Reporting
53
Exclusive Access
54
Concurrent Locks
54
Acquiring Exclusive Access Across PI7C7100
54
Ending Exclusive Access
55
PCI Bus Arbitration
56
Primary PCI Bus Arbitration
56
Secondary PCI Bus Arbitration
56
Secondary Bus Arbitration Using the Internal Arbiter
56
Secondary Bus Arbitration Using an External Arbiter
57
Bus Parking
57
Clocks
58
Primary Clock Inputs
58
Secondary Clock Outputs
58
Reset
59
Primary Interface Reset
59
Secondary Interface Reset
59
Chip Reset
59
Supported Commands
60
Primary Interface
60
Secondary Interface
62
Configuration Registers
63
Config Register 1
65
Config Register 2
65
Config Register 1 or 2:Vendor ID Register (Read Only, Bit 15-0; Offset 00H)
65
Config Register 1: Device ID Register (Read Only, Bit 31-16; Offset 00H)
65
Config Register 2: Device ID Register (Read Only, Bit 31-16; Offset 00H)
65
Config Register 1: Command Register (Bit 15-0; Offset 04H)
65
Config Register 2: Command Register (Bit 15-0; Offset 04H)
66
Config Register 1 or 2: Status Register (for Primary Bus, Bit 31-16; Offset 04H)
67
Config Register 1 or 2: Revision ID Register (Read Only, Bit 7-0; Offset 08H)
68
Config Register 1 or 2: Class Code Register (Read Only, Bit 31-8; Offset 08H)
68
Config Register 1 or 2: Cache Line Size Register (Read/Write, Bit 7-0; Offset 0Ch)
68
Config Register 1: Primary Latency Timer Register (Read/Write, Bit 15-8; Offset 0Ch)
68
Config Register 2: Primary Latency Timer Register (Read/Write, Bit 15-8; Offset 0Ch)
68
Config Register 1: Header Type Register (Read Only, Bit 23-16; Offset 0Ch)
68
Config Register 2: Header Type Register (Read Only, Bit 23-16; Offset 0Ch)
68
Config Register 1: Primary Bus Number Register (Read/Write, Bit 7-0; Offset 18H)
68
Config Register 2: Primary Bus Number Register (Read/Write, Bit 7-0; Offset 18H)
68
Config Register 1 or 2: Secondary Bus Number Register (Read/Write, Bit 15-8; Offset 18H)
68
Config Register 1 or 2: Secondary Status Register (Bit 31-16; Offset 1Ch)
69
Config Register 1 or 2: Memory Base Register (Read/Write, Bit 15-0; Offset 20H)
70
Config Register 1 or 2: Memory Limit Register (Read/Write, Bit 31:16; Offset 20H)
70
Config Register 1 or 2: Prefetchable Memory Base Register (Read/Write, Bit 15-0;Offset 24H)
70
Config Register 1 or 2: Prefetchable Memory Limit Register (Read/Write, Bit 31-16; Offset 24H)
70
Config Register 1 or 2: I/O Base Address Upper 16 Bits Register (Read/Write, Bit 15-0; Offset 30H)
70
Config Register 1 or 2: I/O Limit Address Upper 16 Bits Register (Read/Write, Bit 31-16; Offset 30H)
70
Config Register 1 or 2: Subsystem Vendor ID (Read/Write, Bit 15-0; Offset 34H)
70
Config Register 1 or 2: Subsystem ID (Read/Write, Bit 31-16; Offset 34H)
70
Config Register 1 or 2: Interrupt Pin Register (Read Only, Bit 15-8; Offset 3Ch)
70
Config Register 1 or 2: Bridge Control Register (Bit 31-16; Offset 3Ch)
71
Config Register 1 or 2: Diagnostic/Chip Control Register (Bit 15-0; Offset 40H)
72
Config Register 1 or 2: Arbiter Control Register (Bit 31-16; Offset 40H)
72
Config Register 1: Primary Prefetchable Memory Base Register (Read/Write, Bit 15-0; Offset 44H)
73
Config Register 2: Primary Prefetchable Memory Base Register (Read/Write, Bit 15-0; Offset 44H)
73
Config Register 1: Primary Prefetchable Memory Limit Register (Read/Write, Bit 31-16; Offset 44H)
73
Config Register 2: Primary Prefetchable Memory Limit Register (Read/Write, Bit 31-16; Offset 44H)
73
Config Register 1 or 2: P_SERR# Event Disable Register (Bit 7-0; Offset 64H)
73
Config Register 1: Secondary Clock Control Register (Bit 15-0; Offset 68H)
74
Config Register 2: Secondary Clock Control Register (Bit 15-0; Offset 68H)
74
Config Register 1 or 2: Non-Posted Memory Base Register (Read/Write, Bit 15-0; Offset 70H)
75
Config Register 1 or 2: Non-Posted Memory Limit Register (Read/Write, Bit 31-16; Offset 70H)
75
Config Register 1: Port Option Register (Bit 15-0; Offset 74H)
75
Config Register 2: Port Option Register (Bit 15-0; Offset 74H)
76
Config Register 1 or 2: Master Timeout Counter Register (Read/Write, Bit 31-16; Offset 74H)
77
Config Register 1 or 2: Retry Counter Register (Read/Write, Bit 31-0; Offset 78H)
77
Config Register 1 or 2: Sampling Timer Register (Read/Write, Bit 31-0; Offset 7Ch)
77
Config Register 1 or 2: Successful I/O Read Count Register (Read/Write, Bit 31-0; Offset 80H)
77
Config Register 1 or 2: Successful I/O Write Count Register (Read/Write, Bit 31-0; Offset 84H)
77
Config Register 1 or 2: Successful Memory Read Count Register (Read/Write, Bit 31-0; Offset 88H)
77
Config Register 1 or 2: Successful Memory Write Count Register (Read/Write, Bit 31-0; Offset 8Ch)
77
Config Register 1: Primary Successful I/O Read Count Register (Read/Write, Bit 31-0; Offset 90H)
77
Config Register 1: Primary Successful I/O Write Count Register (Read/Write, Bit 31-0; Offset 94H)
77
Config Register 1: Primary Successful Memory Read Count Register (Read/Write, Bit 31-0; Offset 98H)
77
Bridge Behavior
78
Bridge Actions for Various Cycle Types
78
Transaction Ordering
78
Abnormal Termination (Initiated by Bridge Master)
79
Master Abort
79
Parity and Error Reporting
79
Reporting Parity Errors
79
Secondary IDSEL Mapping
79
IEEE 1149.1 Compatible JTAG Controller
80
Boundary Scan Architecture
80
TAP Pins
80
Instruction Register
80
Boundary Scan Instruction Set
81
TAP Test Data Registers
82
Bypass Register
82
Boundary-Scan Register
82
TAP Controller
82
JTAG Boundary Register Order
83
Electrical and Timing Specifications
87
Maximum Ratings
87
DC Specifications
87
AC Specifications
88
Primary and Secondary Buses at 33 Mhz Clock Timing
88
Power Consumption
88
Pin PBGA Package
89
Part Number Ordering Information
89
Appendix A Timing Diagrams
91
Configuration Read Transaction
93
Configuration Write Transaction
93
Type 1 to Type 0 Configuration Write Transaction (P → S)
94
Downstream Type 1 to Special Cycle Transaction (P → S)
95
Downstream Type 1 to Type 1 Configuration Write Transaction (P → S)
96
Downstream Delayed Memory Read Transaction (P/33Mhz → S/33Mhz
97
Downstream Delayed Memory Read Transaction (S2/33Mhz → S1/33Mhz
98
Downstream Delayed Memory Read Transaction (S1/33Mhz → S2/33Mhz
98
Upstream Delayed Memory Read Transaction (S/33Mhz → P/33Mhz
99
Downstream Posted Memory Write Transaction (P/33Mhz → S/33Mhz
99
Downstream Posted Memory Write Transaction (S2/33Mhz → S1/33Mhz
100
Downstream Posted Memory Write Transaction (S1/33Mhz → S2/33Mhz
100
Downstream Flow-Through Posted Memory Write Transaction (P/33Mhz → S/33Mhz
101
Downstream Flow-Through Posted Memory Write Transaction (S2/33Mhz → S1/33Mhz
102
Downstream Flow-Through Posted Memory Write Transaction (S1/33Mhz → S2/33Mhz
102
Upstream Flow-Through Posted Memory Write Transaction (S/33Mhz → P/33Mhz)
103
Downstream Delayed I/O Read Transaction (S2/33Mhz → S1/33Mhz
104
Downstream Delayed I/O Read Transaction (S1/33Mhz → S2/33Mhz
104
Downstream Delayed I/O Write Transaction (P → S)
105
Downstream Delayed I/O Write Transaction (S2/33Mhz → S1/33Mhz
106
Downstream Delayed I/O Write Transaction (S1/33Mhz → S2/33Mhz
106
Upstream Delayed I/O Write Transaction (S → P)
107
Appendix B - Evaluation Board User's Manual
109
General Information
111
General Information
112
Frequently Asked Questions
113
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