Delayed Read Completion with Target ........................18 4.6.6 Delayed Read Completion on Initiator Bus ......................18 Configuration Transactions ........................... 19 4.7.1 Type 0 Access to PI7C7100 ........................... 19 4.7.2 Type 1 to Type 0 Conversion ..........................20 4.7.3 Type 1 to Type 1 Forwarding ..........................21 4.7.4...
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Data Parity Error Reporting Summary ........................39 System Error (SERR#) Reporting ........................... 45 Exclusive Access ..............................46 Concurrent Locks ..............................46 Acquiring Exclusive Access across PI7C7100 ....................... 46 Ending Exclusive Access ............................47 PCI Bus Arbitration .............................. 48 Primary PCI Bus Arbitration ........................... 48 Secondary PCI Bus Arbitration ..........................
1. Introduction Product Description PI7C7100 is the first triple port PCI-to-PCI Bridge device designed to be fully compliant with the 32-bit, 33 MHz implementation of the PCI Local Bus Specification, Revision 2.1 . PI7C7100 supports only synchronous bus transactions between devices on the primary 33 MHz bus and the secondary buses operating at 33 MHz.
PCI transaction. The Master and Target columns indicate support for each transaction when PI7C7100 initiates transactions as a master, on the primary (P) and secondary (S1, S2) buses, and when PI7C7100 responds to transactions as a target, on the primary (P) and secondary (S1, S2) buses.
P_CBE[3:0]. PI7C7100 supports the linear increment address mode only, which is indicated when the lowest two address bits are equal to zero. If either of the lowest two address bits is nonzero, PI7C7100 automatically disconnects the transaction after the first data transfer.
Once the posted write data moves to the head of the posted data queue, PI7C7100 asserts its request on the target bus. This can occur while PI7C7100 is still receiving data on the initiator bus. When the grant for the target bus is received and the target bus is detected in the idle condition, PI7C7100 asserts FRAME# and drives the stored write address out on the target bus.
If the initiator repeats the write transaction before the data has been transferred to the target, PI7C7100 returns a target retry to the initiator. PI7C7100 continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered.
4.6.2 Non-prefetchable Read Transactions A non-prefetchable read transaction is a read transaction where PI7C7100 requests one and only one DWORD from the target and disconnects the initiator after delivery of the first DWORD of read data. Unlike prefetchable read transactions, PI7C7100 forwards the read byte enable information for the data phase.
If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero for all data phases. If PI7C7100 receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered.
P_SERR# (see Section 7.4). PI7C7100 has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted as it is already contained in the delayed transaction queue.
Type 1 transaction is generated. PI7C7100 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C7100 must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it.
> PI7C7100 can assert up to 16 unique address lines to be used as IDSEL signals for up to 16 devices on the secondary bus, for device numbers ranging from 0 through 15. Because of electrical loading constraints of the PCI bus, more than 16 IDSEL signals should not be necessary.
Type 1 configuration write transactions in either the upstream or the downstream direction. PI7C7100 initiates a special cycle on the target bus when a Type 1 configuration write transaction is being detected on the initiating bus and the following conditions are met during the address phase: •...
For delayed read and write transactions, PI7C7100 is able to reflect the master abort condition back to the initiator. When PI7C7100 detects a master abort in response to a delayed transaction, and when the initiator repeats the transaction, PI7C7100 does not respond to the transaction with DEVSEL# which induces the master abort condition back to the initiator.
Note that when a target retry or target disconnect is returned and posted write data associated with that transaction remains in the write buffers, PI7C7100 initiates another write transaction to attempt to deliver the rest of the write data. If there is a target retry, the exact same address will be driven as for the initial write transaction attempt. If a target disconnect is received, the address that is driven on a subsequent write transaction attempt will be updated to reflect the address of the current DWORD.
4.8.4.1 Target Retry PI7C7100 returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. PI7C7100 returns a target retry to an initiator when any of the following conditions is met: For delayed write transactions: •...
PI7C7100 returns a target abort to an initiator when one of the following conditions is met: • PI7C7100 is returning a target abort from the intended target. When PI7C7100 returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface.
I/O transactions, the master enable bit must be set in the command register. If the master- enable bit is not set, PI7C7100 ignores all I/O and memory transactions initiated on the secondary bus. The master- enable bit also allows upstream forwarding of memory transactions if it is set.
PI7C7100 inside the I/O address range in order to support mapping of I/O space in the presence of an ISA bus in the system. This bit only affects the response of PI7C7100 when the transaction falls inside the address range defined by the I/O base and limit address registers, and only when this address also falls inside the first 64KB of I/O space (address bits [31:16] are 0000h).
PI7C7100 pre-fetches in this space only if the memory read line or memory read multiple commands are used; transactions using the memory read command are limited to a single data transfer.
1KB throughout the first 64KB of I/O space. Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C7100 behaves in the same way as if only the VGA mode bit were set.
In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C7100 as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator.
• System hardware guarantees that write buffers are flushed before interrupts are forwarded. PI7C7100 does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just...
PI7C7100 also asserts P_PERR#. If the parity error response bit is not set, PI7C7100 does not assert P_PERR#. • PI7C7100 sets the detected parity error bit in the status register, regardless of the state of the parity error response bit.
When a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits, and data parity are all captured and a target retry is returned to the initiator. When PI7C7100 detects a parity error on the write data for the initial delayed write request transaction, the following events occur: •...
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• When parity error is forwarded back from the target bus For downstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7100 has write status to return, the following events occur: •...
During upstream write transactions, when a data parity error is reported on the target (primary) bus by the target’s assertion of P_PERR#, the following events occur: • PI7C7100 sets the data parity detected bit in the status register, if the parity error response bit is set in the command register of the primary interface. •...
7.3 Data Parity Error Reporting Summary In the previous sections, the responses of PI7C7100 to data parity errors are presented according to the type of transaction in progress. This section organizes the responses of PI7C7100 to data parity errors according to the status bits that PI7C7100 sets and the signals that it asserts.
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Table 7–2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when PI7C7100 detects a parity error on the secondary interface. Table 7–2. Setting Secondary Interface Detected Parity Error Bit Table 7–3 shows setting data parity detected bit in the primary interface’s status register.
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Table 7–4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions: • The PI7C7100 must be a master on the secondary bus. • The parity error response bit must be set in the bridge control register of secondary interface.
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Table 7–5 shows assertion of P_PERR#. This signal is set under the following conditions: • PI7C7100 is either the target of a write transaction or the initiator of a read transaction on the primary bus. • The parity-error-response bit must be set in the command register of primary interface.
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Table 7–6 shows assertion of S_PERR# that is set under the following conditions: • PI7C7100 is either the target of a write transaction or the initiator of a read transaction on the secondary bus. • The parity error response bit must be set in the bridge control register of secondary interface.
• PI7C7100 did not detect the parity error as a target of the posted write transaction. • The parity error response bit on the command register and the parity error response bit on the bridge control register must both be set.
Whenever assertion of P_SERR# is discussed in this document, it is assumed that the following conditions apply: • For PI7C7100 to assert P_SERR# for any reason, the SERR# enable bit must be set in the command register. • Whenever PI7C7100 asserts P_SERR#, PI7C7100 must also set the signaled system error bit in the status register.
When the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, and byte enable bits, PI7C7100 transfers the read data back to the initiator, and the lock is then also established on the primary bus.
When PI7C7100 receives a target abort or a master abort in response to a locked posted write transaction, PI7C7100 cannot pass back that status to the initiator. PI7C7100 asserts SERR# on the initiator bus when a target abort or a master abort is received during a locked posted write transaction, if the SERR# enable bit is set in the command register.
Figure 9–1 shows an example of an internal arbiter where four masters, including PI7C7100, are in the high priority group, and five masters are in the low priority group. Using...
When P_GNT# is de-asserted, PI7C7100 3-states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C7100 is parking the primary PCI bus and wants to initiate a transaction on that bus, then PI7C7100 can start the transaction on the next PCI clock cycle by asserting P_FRAME# if P_GNT# is still asserted.
10.1 Primary Clock Inputs PI7C7100 implements a primary clock input for the PCI interface. The primary interface is synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized to the secondary clock. The secondary clock is derived internally from the primary clock, P_CLK, through an internal PLL.
11.3 Chip Reset The chip reset bit in the diagnostic control register can be used to reset PI7C7100 and the secondary buses. All registers, and chip state machines are reset and all signals are 3-stated when the chip reset is set. In addition, S1_RESET# or S2_RESET# is asserted, and the secondary reset bit is automatically set.
A 16-bit register for add-on cards to distinguish from one another. Reset to 0000h. 13.2.30 Config Register 1 or 2: Interrupt Pin Register (read only, bit 15-8; offset 3Ch) The register reads as 00h to indicate that PI7C7100 does not use any interrupt pins.
13.2.45 Config Register 1 or 2: Master Timeout Counter Register (read/write, bit 31-16; offset 74h) This register holds the maximum number of PCI clocks that PI7C7100 will wait for initiator to retry the same cycle before reporting timeout. Default is 8000h.
(sustained 3-state signal). 14.2 Transaction Ordering To maintain data coherency and consistency, PI7C7100 complies with the ordering rules put forth in the PCI Local Bus Specification, Rev 2.1. The following table summarizes the ordering relationship of all the transactions through the bridge.
14.3.4 Secondary IDSEL mapping When PI7C7100 detects a Type 1 configuration transaction for a device connected to the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream interface. Type 1 configuration format uses a 5-bit field at...
15.1.1 TAP Pins The PI7C7100’s TAP pins form a serial port composed of four input connections (TMS, TCK, TRST# and TDI) and one output connection (TDO). These pins are described in Table 15-1. The TAP pins provide access to the instruction register and the test data registers.
TCK. 15.2 Boundary-Scan Instruction Set The PI7C7100 supports three mandatory boundary-scan instructions (bypass, sample/preload and extest). The table shown below lists the PI7C7100’s boundary-scan instruction codes. The “reserved” code should not be used. Table 15-1. TAP Pins t i n...
The boundary-scan register contains a cell for each pin as well as control cells for I/O and the high-impedance pin. Table 15-2 shows the bit order of the PI7C7100 boundary-scan register. All table cells that contain “Control” select the direction of bidirectional pins or high-impedance output pins. When a “0” is loaded into the control cell, the associated pin(s) are high-impedance or selected as input.
(continued) 6. Turn on the power for the system. Your OS should already have drivers for the PI7C7100 evaluation board. In Win9X, Plug and Play should detect the device as a PCI-to-PCI bridge. The system may prompt you for the Win9X CD for the drivers.
However, the S_CLKOUT [15:0] are still derived by program- ming bits [15:0] in both configuration registers 1 and 2 at offset 68h. 8. What clock frequency combinations does the PI7C7100 support? Primary Bus...