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LPC24XX UM10237
NXP Semiconductors LPC24XX UM10237 Manuals
Manuals and User Guides for NXP Semiconductors LPC24XX UM10237. We have
1
NXP Semiconductors LPC24XX UM10237 manual available for free PDF download: User Manual
NXP Semiconductors LPC24XX UM10237 User Manual (792 pages)
NXP Semiconductors Microcontrollers User manual
Brand:
NXP Semiconductors
| Category:
Network Hardware
| Size: 4 MB
Table of Contents
4. Apb Peripheral Addresses
22
Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter (UART)
1
Contact Information
2
Chapter 1: LPC24XX Introductory Information
3
Introduction
3
How to Read this Manual
3
Table
3
LPC2400 Features
4
Applications
6
Ordering Options
6
LPC2458 Ordering Options
6
LPC2460 Ordering Options
6
LPC2468 Ordering Options
7
LPC2470 Ordering Options
7
LPC2478 Ordering Options
8
Architectural Overview
8
On-Chip Flash Programming Memory (LPC2458/68/78)
9
On-Chip SRAM
10
LPC2458 Block Diagram
11
LPC2420/60 Block Diagram
12
LPC2468 Block Diagram
13
LPC2470 Block Diagram
14
LPC2478 Block Diagram
15
Xe000
16
Chapter 2: LPC24XX Memory Mapping
16
How to Read this Chapter
16
Memory Map and Peripheral Addressing
16
Xe000
17
Xe001
17
Xe001
18
Memory Maps
18
Xe002
18
Xe002
19
Xe003
19
Xe003
20
APB Peripheral Addresses
22
Table of Contents
22
LPC2400 Memory Re-Mapping and Boot ROM
23
Memory Map Concepts and Operating Modes
23
Memory Re-Mapping
24
Memory Mapping Control
25
Memory Mapping Control Register (MEMMAP - 0Xe01F C040)
25
Memory Mapping Control Usage Notes
25
NXP B.V. 2008. All Rights Reserved
25
NXP B.V. 2008. All Rights Reserved
26
NXP B.V. 2008. All Rights Reserved
27
Rev. 02 — 19 December
27
Xe004
20
Xe004
27
Xe006
27
Xe007
27
Xe008
27
Prefetch Abort and Data Abort Exceptions
27
NXP B.V. 2008. All Rights Reserved
28
Chapter 3: LPC24XX System Control
28
Pin Description
28
Register Description
28
Summary of System Control Block Functions
28
External Interrupt Flag Register (EXTINT - 0Xe01F C140)
29
External Interrupt Inputs
29
NXP B.V. 2008. All Rights Reserved
29
Register Description
29
NXP B.V. 2008. All Rights Reserved
30
External Interrupt Mode Register (EXTMODE - 0Xe01F C148)
31
External Interrupt Polarity Register (EXTPOLAR - 0Xe01F C14C)
31
NXP B.V. 2008. All Rights Reserved
31
NXP B.V. 2008. All Rights Reserved
32
Timer
32
Reset
32
NXP B.V. 2008. All Rights Reserved
33
NXP B.V. 2008. All Rights Reserved
34
Reset Source Identification Register (RSIR - 0Xe01F C180)
34
NXP B.V. 2008. All Rights Reserved
35
Other System Controls and Status Flags
35
System Controls and Status Register (SCS - 0Xe01F C1A0)
35
AHB Arbiter Configuration Register 1 (AHBCFG1 - 0Xe01F C188)
36
AHB Configuration
36
NXP B.V. 2008. All Rights Reserved
36
Examples of AHB1 Settings
37
NXP B.V. 2008. All Rights Reserved
37
AHB Arbiter Configuration Register 2 (AHBCFG2 - 0Xe01F C18C)
38
NXP B.V. 2008. All Rights Reserved
38
Examples of AHB2 Settings
39
Brown-Out Detection
40
Code Security Vs. Debugging
40
Chapter 4: LPC24XX Clocking and Power Control
41
Summary of Clocking and Power Control Functions
41
Internal RC Oscillator
43
Main Oscillator
43
Oscillators
43
NXP B.V. 2008. All Rights Reserved
44
Clock Source Selection Multiplexer
45
NXP B.V. 2008. All Rights Reserved
45
Register Description
45
RTC Oscillator
45
CAN Controller
46
Clock Source Select Register (CLKSRCSEL - 0Xe01F C10C)
46
NXP B.V. 2008. All Rights Reserved
46
PLL (Phase Locked Loop)
46
PLL Operation
46
NXP B.V. 2008. All Rights Reserved
47
Timer
47
PLL and Startup/Boot Code Interaction
47
PLL Register Description
47
NXP B.V. 2008. All Rights Reserved
48
PLL Control Register (PLLCON - 0Xe01F C080)
48
0Xe01F C084)
49
NXP B.V. 2008. All Rights Reserved
49
PLL Configuration Register
49
NXP B.V. 2008. All Rights Reserved
50
51 3.2.7 PLL Interrupt: PLOCK
51
NXP B.V. 2008. All Rights Reserved
51
PLL Status Register (PLLSTAT - 0Xe01F C088)
51
NXP B.V. 2008. All Rights Reserved
52
PLL and Power-Down Mode
52
PLL Feed Register (PLLFEED - 0Xe01F C08C)
52
PLL Modes
52
NXP B.V. 2008. All Rights Reserved
53
PLL Frequency Calculation
53
Examples of PLL Settings
54
Procedure for Determining PLL Settings
54
NXP B.V. 2008. All Rights Reserved
55
Clock Dividers
56
NXP B.V. 2008. All Rights Reserved
56
PLL Setup Sequence
56
CPU Clock Configuration Register (CCLKCFG - 0Xe01F C104)
57
IRC Trim Register (IRCTRIM - 0Xe01F C1A4)
57
NXP B.V. 2008. All Rights Reserved
57
USB Clock Configuration Register (USBCLKCFG - 0Xe01F C108)
57
NXP B.V. 2008. All Rights Reserved
58
Timer
58
Peripheral Clock Selection Registers 0 and 1 (PCLKSEL0 - 0Xe01F C1A8 and PCLKSEL1 - 0Xe01F C1AC)
58
Battery RAM
59
Idle Mode
59
NXP B.V. 2008. All Rights Reserved
59
Power Control
59
System Control Block
59
Uart2
59
Uart3
59
NXP B.V. 2008. All Rights Reserved
60
Peripheral Power Control
60
Power-Down Mode
60
Sleep Mode
60
NXP B.V. 2008. All Rights Reserved
61
Power Control Register Description
61
Power Mode Control Register (PCON - 0Xe01F C0C0)
61
System Control Block
61
Interrupt Wakeup Register (INTWAKE - 0Xe01F C144)
62
NXP B.V. 2008. All Rights Reserved
62
System Control Block
62
NXP B.V. 2008. All Rights Reserved
63
Power Control for Peripherals Register (PCONP - 0Xe01F C0C4)
63
System Control Block
63
NXP B.V. 2008. All Rights Reserved
64
Uart2
64
Uart3
64
Battery RAM
65
Not Used
65
NXP B.V. 2008. All Rights Reserved
65
Power Control Usage Notes
65
Power Domains
65
Wakeup Timer
65
NXP B.V. 2008. All Rights Reserved
66
NXP B.V. 2008. All Rights Reserved
67
Chapter 5: LPC24XX External Memory Controller (EMC)
67
Basic Configuration
67
How to Read this Chapter
67
EMC Functional Description
68
Features
68
Introduction
68
NXP B.V. 2008. All Rights Reserved
68
AHB Slave Register Interface
69
NXP B.V. 2008. All Rights Reserved
69
AHB Slave Memory Interface
70
Data Buffers
70
Memory Transaction Endianness
70
Memory Transaction Size
70
NXP B.V. 2008. All Rights Reserved
70
Pad Interface
70
Write Buffers
70
Write Protected Memory Areas
70
Low-Power Operation
71
Memory Controller State Machine
71
NXP B.V. 2008. All Rights Reserved
71
Read Buffers
71
Low-Power SDRAM Deep-Sleep Mode
72
Low-Power SDRAM Partial Array Refresh
72
Memory Bank Select
72
NXP B.V. 2008. All Rights Reserved
72
NXP B.V. 2008. All Rights Reserved
73
Pin Description
73
Reset
73
System Control Block
73
NXP B.V. 2008. All Rights Reserved
74
Register Description
74
NXP B.V. 2008. All Rights Reserved
75
EMC Control Register (Emccontrol - 0Xffe0 8000)
76
NXP B.V. 2008. All Rights Reserved
76
EMC Status Register (Emcstatus - 0Xffe0 8004)
77
NXP B.V. 2008. All Rights Reserved
77
Dynamic Memory Control Register (Emcdynamiccontrol - 0Xffe0 8020)
78
EMC Configuration Register (Emcconfig - 0Xffe0 8008)
78
NXP B.V. 2008. All Rights Reserved
78
NXP B.V. 2008. All Rights Reserved
79
Dynamic Memory Refresh Timer Register (Emcdynamicrefresh - 0Xffe0 8024)
80
NXP B.V. 2008. All Rights Reserved
80
Dynamic Memory Percentage Command Period Register (Emcdynamictrp - 0Xffe0 8030)
81
Dynamic Memory Read Configuration Register (Emcdynamicreadconfig - 0Xffe0 8028)
81
NXP B.V. 2008. All Rights Reserved
81
Dynamic Memory Active to Precharge Command Period Register (Emcdynamictras - 0Xffe0 8034)
82
Dynamic Memory Self-Refresh Exit Time Register (Emcdynamictsrex - 0Xffe0 8038)
82
Period Register
82
NXP B.V. 2008. All Rights Reserved
83
Register (Emcdynamictapr - 0Xffe0 803C)
83
NXP B.V. 2008. All Rights Reserved
84
NXP B.V. 2008. All Rights Reserved
82
Dynamic Memory Write Recovery Time Register (Emcdynamictwr - 0Xffe0 8044)
84
0Xffe0 8048)
84
NXP B.V. 2008. All Rights Reserved
85
Dynamic Memory Auto-Refresh Period Register (Emcdynamictrfc - 0Xffe0 804C)
85
Dynamic Memory Exit Self-Refresh Register (Emcdynamictxsr - 0Xffe0 8050)
85
Dynamic Memory Active Bank a to Active Bank B Time Register (Emcdynamictrrd - 0Xffe0 8054)
86
Dynamic Memory Load Mode Register to Active Command Time (Emcdynamictmrd - 0Xffe0 8058)
86
NXP B.V. 2008. All Rights Reserved
86
Dynamic Memory Configuration Registers (Emcdynamicconfig0-3 - 0Xffe0 8100, 120, 140, 160)
87
NXP B.V. 2008. All Rights Reserved
87
Static Memory Extended Wait Register (Emcstaticextendedwait - 0Xffe0 8080)
87
NXP B.V. 2008. All Rights Reserved
88
NXP B.V. 2008. All Rights Reserved
89
Dynamic Memory RAS & cas Delay Registers (Emcdynamicrascas0-3 - 0Xffe0 8104, 124, 144, 164)
90
NXP B.V. 2008. All Rights Reserved
90
NXP B.V. 2008. All Rights Reserved
91
Static Memory Configuration Registers
91
NXP B.V. 2008. All Rights Reserved
92
Static Memory Write Enable Delay Registers
92
Not Used
93
NXP B.V. 2008. All Rights Reserved
93
Static Memory Output Enable Delay Registers
93
Static Memory Read Delay Registers
93
Not Used
94
Static Memory Page Mode Read Delay Registers (Emcstaticwaitpage0-3 - 0Xffe0 8210, 230, 250, 270)
94
Static Memory Write Delay Registers
94
External Memory Interface
95
NXP B.V. 2008. All Rights Reserved
95
Static Memory Turn Round Delay Registers
95
32-Bit Wide Memory Bank Connection
96
NXP B.V. 2008. All Rights Reserved
96
16-Bit Wide Memory Bank Connection
97
NXP B.V. 2008. All Rights Reserved
97
8-Bit Wide Memory Bank Connection
98
NXP B.V. 2008. All Rights Reserved
98
Memory Configuration Example
99
NXP B.V. 2008. All Rights Reserved
99
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
100
How to Read this Chapter
100
Introduction
100
NXP B.V. 2008. All Rights Reserved
100
Operation
100
Flash Memory Bank
101
Memory Acceleration Module Blocks
101
NXP B.V. 2008. All Rights Reserved
101
Flash Programming Issues
102
Instruction Latches and Data Latches
102
NXP B.V. 2008. All Rights Reserved
102
MAM Configuration
103
NXP B.V. 2008. All Rights Reserved
103
MAM Control Register (MAMCR - 0Xe01F C000)
104
MAM Timing Register (MAMTIM - 0Xe01F C004)
104
NXP B.V. 2008. All Rights Reserved
104
Register Description
104
NXP B.V. 2008. All Rights Reserved
105
MAM Usage Notes
106
NXP B.V. 2008. All Rights Reserved
106
NXP B.V. 2008. All Rights Reserved
107
Chapter 7: LPC24XX Vectored Interrupt Controller (VIC)
108
Description
108
Features
108
NXP B.V. 2008. All Rights Reserved
108
Register Description
108
NXP B.V. 2008. All Rights Reserved
109
NXP B.V. 2008. All Rights Reserved
110
NXP B.V. 2008. All Rights Reserved
111
Raw Interrupt Status Register (Vicrawintr - 0Xffff F008)
111
Software Interrupt Clear Register (Vicsoftintclear - 0Xffff F01C)
111
Software Interrupt Register (Vicsoftint - 0Xffff F018)
111
Interrupt Enable Clear Register (Vicintenclear - 0Xffff F014)
112
Interrupt Enable Register (Vicintenable - 0Xffff F010)
112
Interrupt Select Register (Vicintselect - 0Xffff F00C)
112
NXP B.V. 2008. All Rights Reserved
112
FIQ Status Register (Vicfiqstatus -
113
IRQ Status Register (Vicirqstatus -
113
NXP B.V. 2008. All Rights Reserved
113
Vector Address Registers 0-31 (Vicvectaddr0-31 - 0Xffff F100 to 17C)
113
NXP B.V. 2008. All Rights Reserved
114
Software Priority Mask Register (Vicswprioritymask - 0Xffff F024)
114
Vector Address Register (Vicaddress -
114
(Vicvectpriority0-31 - 0Xffff F200 to 27C)
114
Interrupt Sources
115
NXP B.V. 2008. All Rights Reserved
115
Protection Enable Register (Vicprotection -
115
NXP B.V. 2008. All Rights Reserved
116
NXP B.V. 2008. All Rights Reserved
117
Uart2
117
Uart3
117
NXP B.V. 2008. All Rights Reserved
118
Chapter 8: LPC24XX Pin Configuration
119
How to Read this Chapter
119
LPC2400 180-Pin Package
119
LPC2400 Pin Packages
119
NXP B.V. 2008. All Rights Reserved
119
LPC2400 208-Pin Packages
120
LPC2458 Pinning Information
120
NXP B.V. 2008. All Rights Reserved
120
NXP B.V. 2008. All Rights Reserved
121
NXP B.V. 2008. All Rights Reserved
122
NXP B.V. 2008. All Rights Reserved
123
Uart3
123
NXP B.V. 2008. All Rights Reserved
124
Uart2
124
NXP B.V. 2008. All Rights Reserved
125
NXP B.V. 2008. All Rights Reserved
126
Uart3
126
NXP B.V. 2008. All Rights Reserved
127
NXP B.V. 2008. All Rights Reserved
128
NXP B.V. 2008. All Rights Reserved
129
NXP B.V. 2008. All Rights Reserved
130
Uart2
130
NXP B.V. 2008. All Rights Reserved
131
NXP B.V. 2008. All Rights Reserved
132
NXP B.V. 2008. All Rights Reserved
133
NXP B.V. 2008. All Rights Reserved
134
Uart3
134
NXP B.V. 2008. All Rights Reserved
135
LPC2460/68 Pinning Information
136
NXP B.V. 2008. All Rights Reserved
136
NXP B.V. 2008. All Rights Reserved
137
NXP B.V. 2008. All Rights Reserved
138
NXP B.V. 2008. All Rights Reserved
139
Uart3
139
NXP B.V. 2008. All Rights Reserved
140
Uart2
140
NXP B.V. 2008. All Rights Reserved
141
Uart3
141
NXP B.V. 2008. All Rights Reserved
142
NXP B.V. 2008. All Rights Reserved
143
NXP B.V. 2008. All Rights Reserved
144
NXP B.V. 2008. All Rights Reserved
145
NXP B.V. 2008. All Rights Reserved
146
Uart2
146
NXP B.V. 2008. All Rights Reserved
147
NXP B.V. 2008. All Rights Reserved
148
NXP B.V. 2008. All Rights Reserved
149
NXP B.V. 2008. All Rights Reserved
150
NXP B.V. 2008. All Rights Reserved
151
NXP B.V. 2008. All Rights Reserved
152
Uart2
152
Uart3
152
NXP B.V. 2008. All Rights Reserved
153
LPC2470/78 Pinning Information
154
NXP B.V. 2008. All Rights Reserved
154
NXP B.V. 2008. All Rights Reserved
155
NXP B.V. 2008. All Rights Reserved
156
NXP B.V. 2008. All Rights Reserved
157
Uart3
157
NXP B.V. 2008. All Rights Reserved
158
NXP B.V. 2008. All Rights Reserved
159
Uart2
159
NXP B.V. 2008. All Rights Reserved
160
Uart3
160
NXP B.V. 2008. All Rights Reserved
161
NXP B.V. 2008. All Rights Reserved
162
NXP B.V. 2008. All Rights Reserved
163
NXP B.V. 2008. All Rights Reserved
164
NXP B.V. 2008. All Rights Reserved
165
NXP B.V. 2008. All Rights Reserved
166
Uart2
166
NXP B.V. 2008. All Rights Reserved
167
NXP B.V. 2008. All Rights Reserved
168
NXP B.V. 2008. All Rights Reserved
169
NXP B.V. 2008. All Rights Reserved
170
NXP B.V. 2008. All Rights Reserved
171
NXP B.V. 2008. All Rights Reserved
172
Uart2
172
Uart3
172
NXP B.V. 2008. All Rights Reserved
173
LPC2460/70 Boot Control
174
NXP B.V. 2008. All Rights Reserved
174
NXP B.V. 2008. All Rights Reserved
175
NXP B.V. 2008. All Rights Reserved
176
Chapter 9 : LPC24XX Pin Connect
176
Description
176
How to Read this Chapter
176
NXP B.V. 2008. All Rights Reserved
177
Pin Function Select Register Values
177
Pin Mode Select Register Values
177
Register Description
177
NXP B.V. 2008. All Rights Reserved
178
Pin Control Module Register Reset Values
178
Pin Function Select Register 0 (PINSEL0 - 0Xe002 C000)
178
NXP B.V. 2008. All Rights Reserved
179
Pin Function Select Register 1 (PINSEL1 - 0Xe002 C004)
179
NXP B.V. 2008. All Rights Reserved
180
Pin Function Select Register 2 (PINSEL2 - 0Xe002 C008)
180
Pin Function Select Register 3 (PINSEL3 - 0Xe002 C00C)
180
NXP B.V. 2008. All Rights Reserved
181
Pin Function Select Register 4 (PINSEL4 - 0Xe002 C010)
181
NXP B.V. 2008. All Rights Reserved
182
NXP B.V. 2008. All Rights Reserved
183
Pin Function Select Register 5 (PINSEL5 - 0Xe002 C014)
183
NXP B.V. 2008. All Rights Reserved
184
NXP B.V. 2008. All Rights Reserved
185
Pin Function Select Register 6 (PINSEL6 - 0Xe002 C018)
185
Pin Function Select Register 7 (PINSEL7 - 0Xe002 C01C)
185
NXP B.V. 2008. All Rights Reserved
186
Pin Function Select Register 8 (PINSEL8 - 0Xe002 C020)
186
NXP B.V. 2008. All Rights Reserved
187
Pin Function Select Register 9 (PINSEL9 - 0Xe002 C024)
187
NXP B.V. 2008. All Rights Reserved
188
Pin Function Select Register 10 (PINSEL10 - 0Xe002 C028)
188
NXP B.V. 2008. All Rights Reserved
189
Pin Function Select Register 11 (PINSEL11 - 0Xe002 C02C)
189
Pin Mode Select Register 0 (PINMODE0 - 0Xe002 C040)
189
NXP B.V. 2008. All Rights Reserved
190
Pin Mode Select Register 1 (PINMODE1 - 0Xe002 C044)
190
Pin Mode Select Register 2 (PINMODE2 - 0Xe002 C048)
190
Pin Mode Select Register 3 (PINMODE3 - 0Xe002 C04C)
190
Pin Mode Select Register 4 (PINMODE4 - 0Xe002 C050)
190
NXP B.V. 2008. All Rights Reserved
191
Pin Mode Select Register 5 (PINMODE5 - 0Xe002 C054)
191
Pin Mode Select Register 6 (PINMODE6 - 0Xe002 C058)
191
Pin Mode Select Register 7 (PINMODE7 - 0Xe002 C05C)
191
Pin Mode Select Register 8 (PINMODE8 - 0Xe002 C060)
191
NXP B.V. 2008. All Rights Reserved
192
Pin Mode Select Register 9 (PINMODE9 - 0Xe002 C064)
192
Basic Configuration
193
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
193
Digital I/O Ports
193
Features
193
How to Read this Chapter
193
NXP B.V. 2008. All Rights Reserved
193
Applications
194
Interrupt Generating Digital Ports
194
NXP B.V. 2008. All Rights Reserved
194
NXP B.V. 2008. All Rights Reserved
195
Pin Description
195
Register Description
195
NXP B.V. 2008. All Rights Reserved
196
NXP B.V. 2008. All Rights Reserved
197
GPIO Port Direction Register IODIR and FIODIR(IO[0/1]DIR - 0Xe002 80[0/1]8 and FIO[0/1/2/3/4]DIR - 0X3Fff C0[0/2/4/6/8]0)
198
NXP B.V. 2008. All Rights Reserved
198
GPIO Port Output Set Register IOSET and FIOSET(IO[0/1]SET - 0Xe002 80[0/1]4 and FIO[0/1/2/3/4]SET - 0X3Fff C0[1/3/5/7/9]8)
199
NXP B.V. 2008. All Rights Reserved
199
NXP B.V. 2008. All Rights Reserved
200
GPIO Port Output Clear Register IOCLR and FIOCLR
201
FIO[0/1/2/3/4]CLR - 0X3Fff C0[1/3/5/7/9]C)
201
NXP B.V. 2008. All Rights Reserved
202
NXP B.V. 2008. All Rights Reserved
201
GPIO Port Pin Value Register IOPIN and FIOPIN
202
FIO[0/1/2/3/4]PIN - 0X3Fff C0[1/3/5/7/9]4)
202
Fiomask
203
NXP B.V. 2008. All Rights Reserved
203
0X3Fff C0[1/3/5/7/9]0)
204
NXP B.V. 2008. All Rights Reserved
204
NXP B.V. 2008. All Rights Reserved
205
NXP B.V. 2008. All Rights Reserved
206
GPIO Interrupt Enable for Falling Edge Register (Io0Intenf - 0Xe002 8094 and Io2Intenf - 0Xe002 80B4)
206
GPIO Interrupt Enable for Rising Edge Register (Io0Intenr - 0Xe002 8090 and Io2Intenr - 0Xe002 80B0)
206
GPIO Interrupt Registers
206
GPIO Overall Interrupt Status Register (Iointstatus - 0Xe002 8080)
206
GPIO Interrupt Status for Falling Edge Register (Io0Intstatf - 0Xe002 8088 and Io2Intstatf - 0Xe002 80A8)
207
GPIO Interrupt Status for Rising Edge Register (Io0Intstatr - 0Xe002 8084 and Io2Intstatr - 0Xe002 80A4)
207
NXP B.V. 2008. All Rights Reserved
207
Example 1: Sequential Accesses to IOSET and IOCLR Affecting the same GPIO Pin/Bit
208
Example 2: an Instantaneous Output of 0S and 1S on a GPIO Port
208
NXP B.V. 2008. All Rights Reserved
209
GPIO Interrupt Clear Register (Io0Intclr - 0Xe002 808C and Io2Intclr - 0Xe002 80AC) 207 GPIO Usage Notes
208
NXP B.V. 2008. All Rights Reserved
208
Writing to IOSET/IOCLR Vs. IOPIN
209
Basic Configuration
210
Chapter 11: LPC24XX Ethernet
210
How to Read this Chapter
210
Introduction
210
NXP B.V. 2008. All Rights Reserved
210
Features
211
NXP B.V. 2008. All Rights Reserved
211
Ethernet Architecture
212
NXP B.V. 2008. All Rights Reserved
212
NXP B.V. 2008. All Rights Reserved
213
Partitioning
213
DMA Engine Functions
214
Example PHY Devices
214
NXP B.V. 2008. All Rights Reserved
214
Ethernet Packet
215
NXP B.V. 2008. All Rights Reserved
215
Overview of DMA Operation
215
NXP B.V. 2008. All Rights Reserved
216
Pin Description
216
NXP B.V. 2008. All Rights Reserved
217
Register Description
217
NXP B.V. 2008. All Rights Reserved
218
Ethernet MAC Register Definitions
219
NXP B.V. 2008. All Rights Reserved
219
MAC Configuration Register 1 (MAC1 - 0Xffe0 0000)
220
MAC Configuration Register 2 (MAC2 - 0Xffe0 0004)
220
NXP B.V. 2008. All Rights Reserved
220
NXP B.V. 2008. All Rights Reserved
221
Back-To-Back Inter-Packet-Gap Register (IPGT - 0Xffe0 0008)
222
Collision Window / Retry Register (CLRT - 0Xffe0 0010)
222
Non Back-To-Back Inter-Packet-Gap Register (IPGR - 0Xffe0 000C)
222
NXP B.V. 2008. All Rights Reserved
222
Maximum Frame Register (MAXF - 0Xffe0 0014)
223
NXP B.V. 2008. All Rights Reserved
223
PHY Support Register (SUPP - 0Xffe0 0018)
223
Test Register (TEST - 0Xffe0 001C)
223
MII Mgmt Command Register (MCMD - 0Xffe0 0024)
224
MII Mgmt Configuration Register (MCFG - 0Xffe0 0020)
224
NXP B.V. 2008. All Rights Reserved
224
MII Mgmt Address Register
225
MII Mgmt Indicators Register (MIND - 0Xffe0 0034)
225
MII Mgmt Read Data Register (MRDD - 0Xffe0 0030)
225
MII Mgmt Write Data Register (MWTD - 0Xffe0 002C)
225
NXP B.V. 2008. All Rights Reserved
225
Not Used
226
NXP B.V. 2008. All Rights Reserved
226
Station Address 0 Register (SA0 - 0Xffe0 0040)
226
Station Address 1 Register
226
0Xffe0 0044)
226
Station Address 2 Register
226
Command Register (Command - 0Xffe0 0100)
227
Control Register Definitions
227
0Xffe0 0048)
227
NXP B.V. 2008. All Rights Reserved
227
NXP B.V. 2008. All Rights Reserved
228
Receive Descriptor Base Address Register (Rxdescriptor - 0Xffe0 0108)
228
Status Register (Status - 0Xffe0 0104)
228
NXP B.V. 2008. All Rights Reserved
229
Receive Number of Descriptors Register (Rxdescriptor - 0Xffe0 0110)
229
Receive Produce Index Register (Rxproduceindex - 0Xffe0 0114)
229
Receive Status Base Address Register (Rxstatus - 0Xffe0 010C)
229
NXP B.V. 2008. All Rights Reserved
230
Receive Consume Index Register (Rxconsumeindex - 0Xffe0 0118)
230
Transmit Descriptor Base Address Register (Txdescriptor - 0Xffe0 011C)
230
Transmit Status Base Address Register (Txstatus - 0Xffe0 0120)
230
NXP B.V. 2008. All Rights Reserved
231
Transmit Number of Descriptors Register (Txdescriptornumber - 0Xffe0 0124)
231
Transmit Produce Index Register (Txproduceindex - 0Xffe0 0128)
231
NXP B.V. 2008. All Rights Reserved
232
Transmit Consume Index Register (Txconsumeindex - 0Xffe0 012C)
232
Transmit Status Vector 0 Register (TSV0 - 0Xffe0 0158)
232
NXP B.V. 2008. All Rights Reserved
233
Receive Status Vector Register (RSV - 0Xffe0 0160)
233
Transmit Status Vector 1 Register (TSV1 - 0Xffe0 015C)
233
Flow Control Counter Register (Flowcontrolcounter - 0Xffe0 0170)
234
NXP B.V. 2008. All Rights Reserved
234
Flow Control Status Register (Flowcontrolstatus - 0Xffe0 0174)
235
NXP B.V. 2008. All Rights Reserved
235
Receive Filter Control Register (Rxfilterctrl - 0Xffe0 0200)
235
Receive Filter Register Definitions
235
NXP B.V. 2008. All Rights Reserved
236
Receive Filter Wol Clear Register
236
Receive Filter Wol Status Register
236
Hash Filter Table Lsbs Register
237
Hash Filter Table Msbs Register (Hashfilterh - 0Xffe0 0214)
237
Interrupt Status Register (Intstatus - 0Xffe0 0FE0)
237
Module Control Register Definitions
237
NXP B.V. 2008. All Rights Reserved
237
Interrupt Enable Register (Intenable - 0Xffe0 0FE4)
238
NXP B.V. 2008. All Rights Reserved
238
Interrupt Clear Register (Intclear - 0Xffe0 0FE8)
239
Interrupt Set Register (Intset - 0Xffe0 0FEC)
239
NXP B.V. 2008. All Rights Reserved
239
NXP B.V. 2008. All Rights Reserved
240
Descriptor and Status Formats
240
Power down Register (Powerdown - 0Xffe0 0FF4)
240
Receive Descriptors and Statuses
240
NXP B.V. 2008. All Rights Reserved
241
NXP B.V. 2008. All Rights Reserved
242
NXP B.V. 2008. All Rights Reserved
243
NXP B.V. 2008. All Rights Reserved
244
Transmit Descriptors and Statuses
244
NXP B.V. 2008. All Rights Reserved
245
NXP B.V. 2008. All Rights Reserved
246
Ethernet Block Functional Description
246
Overview
246
AHB Interface
247
Direct Memory Access (DMA)
247
Interrupts
247
NXP B.V. 2008. All Rights Reserved
247
NXP B.V. 2008. All Rights Reserved
248
NXP B.V. 2008. All Rights Reserved
249
Initialization
250
NXP B.V. 2008. All Rights Reserved
250
NXP B.V. 2008. All Rights Reserved
251
Transmit Process
251
NXP B.V. 2008. All Rights Reserved
252
NXP B.V. 2008. All Rights Reserved
253
NXP B.V. 2008. All Rights Reserved
254
NXP B.V. 2008. All Rights Reserved
255
NXP B.V. 2008. All Rights Reserved
256
NXP B.V. 2008. All Rights Reserved
257
Receive Process
257
NXP B.V. 2008. All Rights Reserved
258
NXP B.V. 2008. All Rights Reserved
259
NXP B.V. 2008. All Rights Reserved
260
NXP B.V. 2008. All Rights Reserved
261
NXP B.V. 2008. All Rights Reserved
262
NXP B.V. 2008. All Rights Reserved
263
Status Hash CRC Calculations
263
Transmission Retry
263
Duplex Modes
264
IEE 802.3/Clause 31 Flow Control
264
NXP B.V. 2008. All Rights Reserved
264
NXP B.V. 2008. All Rights Reserved
265
Half-Duplex Mode Backpressure
266
NXP B.V. 2008. All Rights Reserved
266
NXP B.V. 2008. All Rights Reserved
267
Receive Filtering
267
NXP B.V. 2008. All Rights Reserved
268
NXP B.V. 2008. All Rights Reserved
269
Power Management
269
NXP B.V. 2008. All Rights Reserved
270
Wake-Up on LAN
270
Enabling and Disabling Receive and Transmit
271
NXP B.V. 2008. All Rights Reserved
271
NXP B.V. 2008. All Rights Reserved
272
NXP B.V. 2008. All Rights Reserved
273
Transmission Padding and CRC
273
Huge Frames and Frame Length Checking
274
MAC Status Vectors
274
NXP B.V. 2008. All Rights Reserved
274
Statistics Counters
274
NXP B.V. 2008. All Rights Reserved
275
Reset
275
AHB Bandwidth
276
DMA Access
276
Ethernet Errors
276
NXP B.V. 2008. All Rights Reserved
276
NXP B.V. 2008. All Rights Reserved
277
CRC Calculation
278
NXP B.V. 2008. All Rights Reserved
278
Overall Bandwidth
278
Types of CPU Access
278
NXP B.V. 2008. All Rights Reserved
279
Basic Configuration
280
Features
280
How to Read this Chapter
280
Introduction
280
NXP B.V. 2008. All Rights Reserved
280
Chapter 12: LPC24XX LCD Controller
281
Hardware Cursor Support
281
NXP B.V. 2008. All Rights Reserved
281
Programmable Parameters
281
Color STN Panels
282
NXP B.V. 2008. All Rights Reserved
282
TFT Panels
282
Types of LCD Panels Supported
282
Monochrome STN Panels
283
NXP B.V. 2008. All Rights Reserved
283
Pin Description
283
Signal Usage
283
Signals Used for Single Panel STN Displays
283
NXP B.V. 2008. All Rights Reserved
284
Signals Used for Dual Panel STN Displays
284
Signals Used for TFT Displays
284
LCD Controller Functional Description
285
NXP B.V. 2008. All Rights Reserved
285
AHB Interfaces
286
AMBA AHB Slave Interface
286
NXP B.V. 2008. All Rights Reserved
286
AMBA AHB Master Interface
287
Dual DMA Fifos and Associated Control Logic
287
NXP B.V. 2008. All Rights Reserved
287
Pixel Serializer
287
NXP B.V. 2008. All Rights Reserved
288
NXP B.V. 2008. All Rights Reserved
289
NXP B.V. 2008. All Rights Reserved
290
NXP B.V. 2008. All Rights Reserved
291
RAM Palette
291
NXP B.V. 2008. All Rights Reserved
292
Cursor Operation
293
Hardware Cursor
293
NXP B.V. 2008. All Rights Reserved
293
Cursor Movement
294
Cursor Sizes
294
Cursor XY Positioning
294
NXP B.V. 2008. All Rights Reserved
294
Cursor Clipping
295
NXP B.V. 2008. All Rights Reserved
295
Cursor Image Format
296
NXP B.V. 2008. All Rights Reserved
296
NXP B.V. 2008. All Rights Reserved
297
Gray Scaler
298
NXP B.V. 2008. All Rights Reserved
298
Upper and Lower Panel Formatters
298
Interrupt Generation
299
NXP B.V. 2008. All Rights Reserved
299
Panel Clock Generator
299
STN and TFT Data Select
299
STN Displays
299
TFT Displays
299
Timing Controller
299
FIFO Underflow Interrupt
300
Master Bus Error Interrupt
300
Next Base Address Update Interrupt
300
NXP B.V. 2008. All Rights Reserved
300
Vertical Compare Interrupt
300
LCD Power up and Power down Sequence
301
NXP B.V. 2008. All Rights Reserved
301
NXP B.V. 2008. All Rights Reserved
302
Register Description
302
LCD Configuration Register (LCD_CFG, RW - 0Xe01F C1B8)
303
0Xffe1 0000)
303
NXP B.V. 2008. All Rights Reserved
304
NXP B.V. 2008. All Rights Reserved
303
Horizontal Timing Restrictions
304
NXP B.V. 2008. All Rights Reserved
305
Vertical Timing Register (LCD_TIMV, RW - 0Xffe1 0004)
305
0Xffe1 0008)
306
NXP B.V. 2008. All Rights Reserved
306
NXP B.V. 2008. All Rights Reserved
307
NXP B.V. 2008. All Rights Reserved
308
Line End Control Register (LCD_LE, RW - 0Xffe1 000C)
308
Lower Panel Frame Base Address Register
309
(LCD_LPBASE, RW - 0Xffe1 0014)
309
NXP B.V. 2008. All Rights Reserved
310
NXP B.V. 2008. All Rights Reserved
309
Upper Panel Frame Base Address Register
309
LCD Control Register (LCD_CTRL, RW - 0Xffe1 0018)
310
NXP B.V. 2008. All Rights Reserved
311
0Xffe1 001C)
312
NXP B.V. 2008. All Rights Reserved
312
0Xffe1 0020)
313
NXP B.V. 2008. All Rights Reserved
313
0Xffe1 0028)
314
NXP B.V. 2008. All Rights Reserved
314
RW - 0Xffe1 0024)
314
NXP B.V. 2008. All Rights Reserved
315
Color Palette Registers (LCD_PAL, RW - 0Xffe1 0200 to 0Xffe1 03FC)
315
Lower Panel Current Address Register
315
(LCD_LPCURR, RW - 0Xffe1 0030)
315
Upper Panel Current Address Register
315
0Xffe1 0800 to 0Xffe1 0BFC)
316
NXP B.V. 2008. All Rights Reserved
316
0Xffe1 0C00)
317
0Xffe1 0C04)
317
NXP B.V. 2008. All Rights Reserved
317
0Xffe1 0C08)
318
0Xffe1 0C0C)
318
NXP B.V. 2008. All Rights Reserved
318
0Xffe1 0C10)
319
0Xffe1 0C14)
319
NXP B.V. 2008. All Rights Reserved
319
NXP B.V. 2008. All Rights Reserved
320
RW - 0Xffe1 0C20)
320
RW - 0Xffe1 0C24)
320
NXP B.V. 2008. All Rights Reserved
321
Cursor Masked Interrupt Status Register (CRSR_INTSTAT, RW - 0Xffe1 0C2C)
321
Cursor Raw Interrupt Status Register (CRSR_INTRAW, RW - 0Xffe1 0C28)
321
LCD Timing Diagrams
322
NXP B.V. 2008. All Rights Reserved
322
NXP B.V. 2008. All Rights Reserved
323
LCD Panel Signal Usage
324
NXP B.V. 2008. All Rights Reserved
324
NXP B.V. 2008. All Rights Reserved
325
NXP B.V. 2008. All Rights Reserved
326
NXP B.V. 2008. All Rights Reserved
327
Basic Configuration
328
Introduction
328
NXP B.V. 2008. All Rights Reserved
328
Chapter 13: LPC24XX USB Device Controller
329
Features
329
Fixed Endpoint Configuration
329
NXP B.V. 2008. All Rights Reserved
329
Functional Description
330
NXP B.V. 2008. All Rights Reserved
330
Analog Transceiver
331
Endpoint RAM (EP_RAM)
331
EP_RAM Access Control
331
NXP B.V. 2008. All Rights Reserved
331
Serial Interface Engine (SIE)
331
DMA Engine and Bus Master Interface
332
Goodlink
332
NXP B.V. 2008. All Rights Reserved
332
Operational Overview
332
Register Interface
332
Softconnect
332
Clocking and Power Management
333
NXP B.V. 2008. All Rights Reserved
333
Pin Description
333
USB Device Usage Note
333
Clocks
334
NXP B.V. 2008. All Rights Reserved
334
Power Management Support
334
Power Requirements
334
NXP B.V. 2008. All Rights Reserved
335
Register Description
335
Remote Wake-Up
335
NXP B.V. 2008. All Rights Reserved
336
Port Select Register
336
C110)
336
NXP B.V. 2008. All Rights Reserved
337
Clock Control Registers
337
USB Clock Control Register (Usbclkctrl - 0Xffe0 CFF4)
337
USB Clock Status Register (Usbclkst - 0Xffe0 CFF8)
337
Device Interrupt Registers
338
NXP B.V. 2008. All Rights Reserved
338
USB Interrupt Status Register (Usbintst - 0Xe01F C1C0)
338
NXP B.V. 2008. All Rights Reserved
339
USB Device Interrupt Status Register (Usbdevintst - 0Xffe0 C200)
339
NXP B.V. 2008. All Rights Reserved
340
USB Device Interrupt Clear Register (Usbdevintclr - 0Xffe0 C208)
340
USB Device Interrupt Enable Register (Usbdevinten - 0Xffe0 C204)
340
NXP B.V. 2008. All Rights Reserved
341
USB Device Interrupt Set Register (Usbdevintset - 0Xffe0 C20C)
341
Endpoint Interrupt Registers
342
NXP B.V. 2008. All Rights Reserved
342
USB Device Interrupt Priority Register (Usbdevintpri - 0Xffe0 C22C)
342
USB Endpoint Interrupt Status Register (Usbepintst - 0Xffe0 C230)
342
NXP B.V. 2008. All Rights Reserved
343
USB Endpoint Interrupt Enable Register (Usbepinten - 0Xffe0 C234)
343
NXP B.V. 2008. All Rights Reserved
344
USB Endpoint Interrupt Clear Register (Usbepintclr - 0Xffe0 C238)
344
NXP B.V. 2008. All Rights Reserved
345
USB Endpoint Interrupt Priority Register (Usbepintpri - 0Xffe0 C240)
345
USB Endpoint Interrupt Set Register (Usbepintset - 0Xffe0 C23C)
345
Endpoint Realization Registers
346
EP RAM Requirements
346
NXP B.V. 2008. All Rights Reserved
346
NXP B.V. 2008. All Rights Reserved
347
USB Realize Endpoint Register (Usbreep - 0Xffe0 C244)
347
NXP B.V. 2008. All Rights Reserved
348
USB Endpoint Index Register (Usbepin - 0Xffe0 C248)
348
USB Maxpacketsize Register (Usbmaxpsize - 0Xffe0 C24C)
348
NXP B.V. 2008. All Rights Reserved
349
USB Receive Data Register (Usbrxdata - 0Xffe0 C218)
349
USB Receive Packet Length Register (Usbrxplen - 0Xffe0 C220)
349
USB Transfer Registers
349
NXP B.V. 2008. All Rights Reserved
350
USB Transmit Data Register (Usbtxdata - 0Xffe0 C21C)
350
USB Transmit Packet Length Register (Usbtxplen - 0Xffe0 C224)
350
NXP B.V. 2008. All Rights Reserved
351
SIE Command Code Registers
351
USB Command Code Register (Usbcmdcode - 0Xffe0 C210)
351
USB Control Register (Usbctrl - 0Xffe0 C228)
351
DMA Registers
352
NXP B.V. 2008. All Rights Reserved
352
USB Command Data Register (Usbcmddata - 0Xffe0 C214)
352
USB DMA Request Status Register (Usbdmarst - 0Xffe0 C250)
352
NXP B.V. 2008. All Rights Reserved
353
USB DMA Request Clear Register (Usbdmarclr - 0Xffe0 C254)
353
USB DMA Request Set Register (Usbdmarset - 0Xffe0 C258)
353
NXP B.V. 2008. All Rights Reserved
354
USB EP DMA Status Register (Usbepdmast - 0Xffe0 C284)
354
USB UDCA Head Register (USBUDCAH - 0Xffe0 C280)
354
NXP B.V. 2008. All Rights Reserved
355
USB DMA Interrupt Status Register (Usbdmaintst - 0Xffe0 C290)
355
USB EP DMA Disable Register (Usbepdmadis - 0Xffe0 C28C)
355
USB EP DMA Enable Register (Usbepdmaen - 0Xffe0 C288)
355
NXP B.V. 2008. All Rights Reserved
356
USB DMA Interrupt Enable Register (Usbdmainten - 0Xffe0 C294)
356
USB End of Transfer Interrupt Status Register (Usbeotintst - 0Xffe0 C2A0)
356
NXP B.V. 2008. All Rights Reserved
357
USB End of Transfer Interrupt Clear Register (Usbeotintclr - 0Xffe0 C2A4)
357
USB End of Transfer Interrupt Set Register (Usbeotintset - 0Xffe0 C2A8)
357
USB New DD Request Interrupt Status Register
357
(Usbnddrintst - 0Xffe0 C2AC)
357
NXP B.V. 2008. All Rights Reserved
358
USB New DD Request Interrupt Clear Register
358
(Usbnddrintclr - 0Xffe0 C2B0)
358
USB New DD Request Interrupt Set Register
358
(Usbnddrintset - 0Xffe0 C2B4)
358
USB System Error Interrupt Clear Register (Usbsyserrintclr - 0Xffe0 C2BC)
358
USB System Error Interrupt Status Register (Usbsyserrintst - 0Xffe0 C2B8)
358
Interrupt Handling
359
Slave Mode
359
DMA Mode
360
NXP B.V. 2008. All Rights Reserved
360
NXP B.V. 2008. All Rights Reserved
361
NXP B.V. 2008. All Rights Reserved
362
NXP B.V. 2008. All Rights Reserved
359
USB System Error Interrupt Set Register (Usbsyserrintset - 0Xffe0 C2C0)
359
Serial Interface Engine Command Description
362
Configure Device (Command: 0Xd8, Data: Write 1 Byte)
363
Get Error Code
363
NXP B.V. 2008. All Rights Reserved
363
Read Error Status
363
Read Test Register
363
Set Address (Command: 0Xd0, Data: Write 1 Byte)
363
Set Endpoint Status
363
NXP B.V. 2008. All Rights Reserved
364
Set Mode (Command: 0Xf3, Data: Write 1 Byte)
364
NXP B.V. 2008. All Rights Reserved
365
Read Current Frame Number
365
Data: Read 1 or 2 Bytes)
365
Read Test Register (Command: 0Xfd, Data: Read 2 Bytes)
365
Set Device Status (Command: 0Xfe, Data: Write 1 Byte)
365
Get Device Status (Command: 0Xfe, Data: Read 1 Byte)
366
Get Error Code (Command: 0Xff, Data: Read 1 Byte)
366
NXP B.V. 2008. All Rights Reserved
366
NXP B.V. 2008. All Rights Reserved
367
Read Error Status (Command: 0Xfb, Data: Read 1 Byte)
367
Select Endpoint (Command: 0X00 - 0X1F, Data: Read 1 Byte (Optional))
368
Select Endpoint/Clear Interrupt (Command: 0X40 - 0X5F, Data: Read 1 Byte)
369
Set Endpoint Status (Command: 0X40 - 0X55, Data: Write 1 Byte (Optional))
369
Clear Buffer (Command: 0Xf2, Data: Read 1 Byte (Optional))
370
Validate Buffer (Command: 0Xfa, Data: None)
370
NXP B.V. 2008. All Rights Reserved
371
USB Device Controller Initialization
371
Data Transfer for out Endpoints
372
Interrupt Generation
372
NXP B.V. 2008. All Rights Reserved
372
Slave Mode Operation
372
Data Transfer for in Endpoints
373
DMA Operation
373
NXP B.V. 2008. All Rights Reserved
373
Transfer Terminology
373
NXP B.V. 2008. All Rights Reserved
374
Triggering the DMA Engine
374
USB Device Communication Area
374
NXP B.V. 2008. All Rights Reserved
375
The DMA Descriptor
375
Dma_Mode
376
Isochronous_Endpoint
376
Max_Packet_Size
376
Next_Dd_Pointer
376
Next_Dd_Valid
376
NXP B.V. 2008. All Rights Reserved
376
Dd_Retired
377
Dd_Status
377
Dma_Buffer_Length
377
Dma_Buffer_Start_Addr
377
NXP B.V. 2008. All Rights Reserved
377
Packet_Valid
377
Finding DMA Descriptor
378
Isochronous_Packetsize_Memory_Address
378
Ls_Byte_Extracted
378
Message_Length_Position
378
Ms_Byte_Extracted
378
Non-Isochronous Endpoint Operation
378
NXP B.V. 2008. All Rights Reserved
378
Present_Dma_Count
378
Setting up DMA Transfers
378
Ending the Packet Transfer
379
NXP B.V. 2008. All Rights Reserved
379
Optimizing Descriptor Fetch
379
Transferring the Data
379
Finding the DMA Descriptor
380
No_Packet DD
380
Isochronous Endpoint Operation
380
NXP B.V. 2008. All Rights Reserved
380
Setting up DMA Transfers
380
Transferring the Data
380
DMA Descriptor Completion
381
Isochronous out Endpoint Operation Example
381
IN Endpoints
381
NXP B.V. 2008. All Rights Reserved
381
OUT Endpoints
381
Auto Length Transfer Extraction (ATLE) Mode Operation
382
OUT Transfers in ATLE Mode
382
NXP B.V. 2008. All Rights Reserved
383
IN Transfers in ATLE Mode
384
NXP B.V. 2008. All Rights Reserved
384
NXP B.V. 2008. All Rights Reserved
382
Finding the DMA Descriptor
384
Setting up the DMA Transfer
384
Transferring the Data
384
IN Endpoints
384
OUT Endpoints
384
NXP B.V. 2008. All Rights Reserved
385
Bulk Endpoints
385
Double Buffered Endpoint Operation
385
Ending the Packet Transfer
385
IN Endpoints
385
OUT Endpoints
385
NXP B.V. 2008. All Rights Reserved
386
Isochronous Endpoints
387
NXP B.V. 2008. All Rights Reserved
387
Basic Configuration
388
Chapter 14: LPC24XX USB Host Controller
388
Features
388
Introduction
388
NXP B.V. 2008. All Rights Reserved
388
Architecture
389
Interfaces
389
NXP B.V. 2008. All Rights Reserved
389
Pin Description
389
NXP B.V. 2008. All Rights Reserved
390
Register Map
390
Software Interface
390
USB Host Usage Note
390
NXP B.V. 2008. All Rights Reserved
391
NXP B.V. 2008. All Rights Reserved
392
USB Host Register Definitions
392
Architecture
393
Basic Configuration
393
Chapter 15: LPC24XX USB OTG Controller
393
Features
393
Introduction
393
NXP B.V. 2008. All Rights Reserved
393
Modes of Operation
394
NXP B.V. 2008. All Rights Reserved
394
Pin Configuration
394
Transceiver
394
NXP B.V. 2008. All Rights Reserved
395
NXP B.V. 2008. All Rights Reserved
396
NXP B.V. 2008. All Rights Reserved
397
NXP B.V. 2008. All Rights Reserved
398
Connecting USB as a Two-Port Host
398
Connecting USB as One Port Host and One Port Device
398
NXP B.V. 2008. All Rights Reserved
399
Register Description
399
NXP B.V. 2008. All Rights Reserved
400
USB Interrupt Status Register (Usbintst - 0Xe01F C1C0)
400
NXP B.V. 2008. All Rights Reserved
401
OTG Interrupt Clear Register (Otgintclr - 0Xffe0 C10C)
401
OTG Interrupt Enable Register (Otginten - 0Xffe0 C104)
401
OTG Interrupt Set Register (Otgintset - 0Xffe0 C20C)
401
OTG Interrupt Status Register (Otgintst - 0Xe01F C100)
401
OTG Status and Control Register (Otgstctrl - 0Xffe0 C110)
401
NXP B.V. 2008. All Rights Reserved
402
NXP B.V. 2008. All Rights Reserved
403
OTG Clock Control Register (Otgclkctrl - 0Xffe0 CFF4)
403
OTG Timer Register (Otgtmr - 0Xffe0 C114)
403
NXP B.V. 2008. All Rights Reserved
404
OTG Clock Status Register (Otgclkst - 0Xffe0 CFF8)
404
I2C Receive Register (I2C_RX - 0Xffe0 C300)
405
I2C Status Register (I2C_STS - 0Xffe0 C304)
405
I2C Transmit Register (I2C_TX - 0Xffe0 C300)
405
NXP B.V. 2008. All Rights Reserved
405
NXP B.V. 2008. All Rights Reserved
406
I2C Control Register (I2C_CTL - 0Xffe0 C308)
407
NXP B.V. 2008. All Rights Reserved
407
I2C Clock High Register (I2C_CLKHI - 0Xffe0 C30C)
408
NXP B.V. 2008. All Rights Reserved
408
I2C Clock Low Register (I2C_CLKLO - 0Xffe0 C310)
409
Interrupt Handling
409
NXP B.V. 2008. All Rights Reserved
409
HNP Support
410
NXP B.V. 2008. All Rights Reserved
410
B-Device: Peripheral to Host Switching
411
NXP B.V. 2008. All Rights Reserved
411
NXP B.V. 2008. All Rights Reserved
412
NXP B.V. 2008. All Rights Reserved
413
Remove D+ Pull-Up
413
Add D+ Pull-Up
414
NXP B.V. 2008. All Rights Reserved
414
A-Device: Host to Peripheral HNP Switching
414
NXP B.V. 2008. All Rights Reserved
415
NXP B.V. 2008. All Rights Reserved
416
Set BDIS_ACON_EN in External OTG Transceiver
416
Ceiver
417
Discharge VBUS
417
NXP B.V. 2008. All Rights Reserved
417
Load and Enable OTG Timer
418
NXP B.V. 2008. All Rights Reserved
418
Stop OTG Timer
418
Suspend Host on Port 1
418
Clocking and Power Management
418
Device Clock Request Signals
419
NXP B.V. 2008. All Rights Reserved
419
Host Clock Request Signals
420
NXP B.V. 2008. All Rights Reserved
420
Power-Down Mode Support
420
USB OTG Controller Initialization
420
NXP B.V. 2008. All Rights Reserved
421
Basic Configuration
422
Features
422
NXP B.V. 2008. All Rights Reserved
422
Pin Description
422
Uart2
422
Uart3
422
Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter
423
NXP B.V. 2008. All Rights Reserved
423
Register Description
423
Uart3
425
0Xe007 C004 When DLAB = 1)
426
NXP B.V. 2008. All Rights Reserved
426
Uartn Divisor Latch LSB Register
426
NXP B.V. 2008. All Rights Reserved
427
Uartn Interrupt Enable Register (U0IER - 0Xe000 C004, U2IER - 0Xe007 8004, U3IER - 0Xe007 C004 When DLAB = 0)
427
NXP B.V. 2008. All Rights Reserved
428
Uartn Interrupt Identification Register (U0IIR - 0Xe000 C008, U2IIR - 0Xe007 8008, U3IIR - 0X7008 C008, Read Only)
428
NXP B.V. 2008. All Rights Reserved
429
NXP B.V. 2008. All Rights Reserved
430
Uartn FIFO Control Register (U0FCR - 0Xe000 C008, U2FCR - 0Xe007 8008, U3FCR - 0Xe007 C008, Write Only)
430
0Xe007 C00C)
430
NXP B.V. 2008. All Rights Reserved
431
Uartn Line Status Register
431
0Xe007 C014, Read Only)
431
NXP B.V. 2008. All Rights Reserved
432
NXP B.V. 2008. All Rights Reserved
433
Uartn Auto-Baud Control Register
433
0Xe007 C020)
433
NXP B.V. 2008. All Rights Reserved
434
Uartn Scratch Pad Register
433
0Xe007 C01C)
433
Auto-Baud
434
Auto-Baud Modes
434
NXP B.V. 2008. All Rights Reserved
435
NXP B.V. 2008. All Rights Reserved
436
Uart3
436
Irda Control Register for UART3 Only (U3ICR - 0Xe007 C024)
436
NXP B.V. 2008. All Rights Reserved
437
Uartn Fractional Divider Register (U0FDR - 0Xe000 C028, U2FDR - 0Xe007 8028, U3FDR - 0Xe007 C028)
437
Baudrate Calculation
438
NXP B.V. 2008. All Rights Reserved
438
NXP B.V. 2008. All Rights Reserved
439
Example 1: PCLK = 14.7456 Mhz, BR = 9600
440
Example 2: PCLK = 12 Mhz, BR = 115200
440
NXP B.V. 2008. All Rights Reserved
440
Uartn Transmit Enable Register (U0TER - 0Xe000 C030, U2TER - 0Xe007 8030, U3TER - 0Xe007 C030)
440
Architecture
441
NXP B.V. 2008. All Rights Reserved
441
NXP B.V. 2008. All Rights Reserved
442
Basic Configuration
443
Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter (UART)
443
Features
443
NXP B.V. 2008. All Rights Reserved
443
NXP B.V. 2008. All Rights Reserved
444
Pin Description
444
Register Description
444
0Xe001 0000 When DLAB = 0, Write Only)
447
0Xe001 0004, When DLAB = 1)
447
NXP B.V. 2008. All Rights Reserved
447
UART1 Divisor Latch LSB and MSB Registers
447
UART1 Receiver Buffer Register (U1RBR - 0Xe001 0000, When DLAB = 0 Read Only)
447
UART1 Transmitter Holding Register
447
NXP B.V. 2008. All Rights Reserved
448
UART1 Interrupt Enable Register (U1IER - 0Xe001 0004, When DLAB = 0)
448
NXP B.V. 2008. All Rights Reserved
449
UART1 Interrupt Identification Register (U1IIR - 4.15 0Xe001 0008, Read Only)
449
NXP B.V. 2008. All Rights Reserved
450
NXP B.V. 2008. All Rights Reserved
451
NXP B.V. 2008. All Rights Reserved
452
UART1 FIFO Control Register (U1FCR - 0Xe001 0008, Write Only)
452
UART1 Line Control Register (U1LCR - 0Xe001 000C)
452
NXP B.V. 2008. All Rights Reserved
453
UART1 Modem Control Register (U1MCR - 0Xe001 0010)
453
Auto-Flow Control
454
Auto-RTS
454
NXP B.V. 2008. All Rights Reserved
454
Auto-CTS
455
NXP B.V. 2008. All Rights Reserved
455
NXP B.V. 2008. All Rights Reserved
456
UART1 Line Status Register (U1LSR - 0Xe001 0014, Read Only)
456
NXP B.V. 2008. All Rights Reserved
457
UART1 Modem Status Register (U1MSR - 0Xe001 0018)
457
NXP B.V. 2008. All Rights Reserved
458
UART1 Auto-Baud Control Register (U1ACR - 0Xe001 0020)
458
UART1 Scratch Pad Register (U1SCR - 0Xe001 001C)
458
Auto-Baud
459
NXP B.V. 2008. All Rights Reserved
459
Auto-Baud Modes
460
NXP B.V. 2008. All Rights Reserved
460
NXP B.V. 2008. All Rights Reserved
461
UART1 Fractional Divider Register (U1FDR - 0Xe001 0028)
461
Baudrate Calculation
462
NXP B.V. 2008. All Rights Reserved
462
NXP B.V. 2008. All Rights Reserved
463
Example 1: PCLK = 14.7456 Mhz, BR = 9600
464
NXP B.V. 2008. All Rights Reserved
464
UART1 Transmit Enable Register (U1TER - 0Xe001 0030)
464
Architecture
465
NXP B.V. 2008. All Rights Reserved
465
NXP B.V. 2008. All Rights Reserved
466
NXP B.V. 2008. All Rights Reserved
467
Chapter 18: LPC24XX CAN Controllers CAN1/2
467
Basic Configuration
467
CAN Controllers
467
How to Read this Chapter
467
Acceptance Filter Features
468
CAN Controller Features
468
Features
468
General CAN Features
468
NXP B.V. 2008. All Rights Reserved
468
Pin Description
468
APB Interface Block (AIB)
469
CAN Controller Architecture
469
Interface Management Logic (IML)
469
NXP B.V. 2008. All Rights Reserved
469
NXP B.V. 2008. All Rights Reserved
470
Receive Buffer (RXB)
470
Transmit Buffers (TXB)
470
Bit Stream Processor (BSP)
471
Bit Timing Logic (BTL)
471
CAN Controller Self-Tests
471
Error Management Logic (EML)
471
NXP B.V. 2008. All Rights Reserved
471
Global Self Test
472
Local Self Test
472
NXP B.V. 2008. All Rights Reserved
472
NXP B.V. 2008. All Rights Reserved
473
Memory Map of the CAN Block
473
Register Description
473
NXP B.V. 2008. All Rights Reserved
474
Mode Register (CAN1MOD - 0Xe004 4000, CAN2MOD - 0Xe004 8000)
475
NXP B.V. 2008. All Rights Reserved
475
Command Register (CAN1CMR - 0Xe004 X004, CAN2CMR - 0Xe004 8004)
476
NXP B.V. 2008. All Rights Reserved
476
NXP B.V. 2008. All Rights Reserved
477
Global Status Register (CAN1GSR - 0Xe004 X008, CAN2GSR - 0Xe004 8008)
478
NXP B.V. 2008. All Rights Reserved
478
NXP B.V. 2008. All Rights Reserved
479
RX Error Counter
479
NXP B.V. 2008. All Rights Reserved
480
TX Error Counter
480
Interrupt and Capture Register
480
0Xe004 400C, CAN2ICR - 0Xe004 800C)
480
NXP B.V. 2008. All Rights Reserved
481
NXP B.V. 2008. All Rights Reserved
482
NXP B.V. 2008. All Rights Reserved
483
NXP B.V. 2008. All Rights Reserved
484
Interrupt Enable Register (CAN1IER - 9
484
Bus Timing Register
485
CAN2BTR - 0Xe004 8014)
485
Baud Rate Prescaler
486
NXP B.V. 2008. All Rights Reserved
486
Synchronization Jump Width
486
Time Segment 1 and Time Segment 2
486
NXP B.V. 2008. All Rights Reserved
487
NXP B.V. 2008. All Rights Reserved
485
Error Warning Limit Register
487
0Xe004 4018, CAN2EWL - 0Xe004 8018)
487
Status Register (CAN1SR - 0Xe004 401C, CAN2SR - 0Xe004 801C)
487
NXP B.V. 2008. All Rights Reserved
488
NXP B.V. 2008. All Rights Reserved
489
Receive Frame Status Register (CAN1RFS - 0Xe004 4020, CAN2RFS - 0Xe004 8020)
489
ID Index Field
490
NXP B.V. 2008. All Rights Reserved
490
Receive Data Register a (CAN1RDA - 0Xe004 4028, CAN2RDA - 0Xe004 8028)
490
Receive Identifier Register (CAN1RID - 0Xe004 4024, CAN2RID - 0Xe004 8024)
490
NXP B.V. 2008. All Rights Reserved
491
Receive Data Register B (CAN1RDB - 0Xe004 402C, CAN2RDB - 0Xe004 802C)
491
Transmit Frame Information Register (CAN1TFI[1/2/3] - 0Xe004 40[30/ 40/50], CAN2TFI[1/2/3] - 0Xe004 80[30/40/50])
491
Automatic Transmit Priority Detection
492
NXP B.V. 2008. All Rights Reserved
492
Tx DLC
492
NXP B.V. 2008. All Rights Reserved
493
Transmit Data Register a (CAN1TDA[1/2/3] - 0Xe004 40[38/48/58], CAN2TDA[1/2/3] - 0Xe004 80[38/48/58])
493
Transmit Identifier Register (CAN1TID[1/2/3] - 0Xe004 40[34/44/54], CAN2TID[1/2/3] - 0Xe004 80[34/44/54])
493
Error Handling
494
NXP B.V. 2008. All Rights Reserved
494
Sleep Mode
494
Transmit Data Register B (CAN1TDB[1/2/3] - 0Xe004 40[3C/4C/5C], CAN2TDB[1/2/3] - 0Xe004 80[3C/4C/5C])
494
CAN Controller Operation
494
Centralized CAN Registers
495
NXP B.V. 2008. All Rights Reserved
495
Transmit Priority
495
NXP B.V. 2008. All Rights Reserved
496
Acceptance Filter off Mode
497
Global Acceptance Filter
497
NXP B.V. 2008. All Rights Reserved
497
Acceptance Filter Bypass Mode
498
Acceptance Filter Operating Mode
498
NXP B.V. 2008. All Rights Reserved
498
Sections of the ID Look-Up Table RAM
498
NXP B.V. 2008. All Rights Reserved
499
Acceptance Filter Registers
500
NXP B.V. 2008. All Rights Reserved
500
NXP B.V. 2008. All Rights Reserved
501
Section Configuration Registers
501
NXP B.V. 2008. All Rights Reserved
502
NXP B.V. 2008. All Rights Reserved
503
NXP B.V. 2008. All Rights Reserved
504
Status Registers
504
NXP B.V. 2008. All Rights Reserved
505
Acceptance Filter Search Algorithm
506
Configuration and Search Algorithm
506
NXP B.V. 2008. All Rights Reserved
506
Fullcan Mode
507
NXP B.V. 2008. All Rights Reserved
507
NXP B.V. 2008. All Rights Reserved
508
Fullcan Message Layout
509
NXP B.V. 2008. All Rights Reserved
509
NXP B.V. 2008. All Rights Reserved
510
Fullcan Message Interrupt Enable Bit
511
NXP B.V. 2008. All Rights Reserved
511
Message Lost Bit and CAN Channel Number
512
NXP B.V. 2008. All Rights Reserved
512
NXP B.V. 2008. All Rights Reserved
513
NXP B.V. 2008. All Rights Reserved
514
NXP B.V. 2008. All Rights Reserved
515
Scenario 3.1: Message Gets Overwritten Indicated by Semaphore Bits and Message Lost
515
NXP B.V. 2008. All Rights Reserved
516
NXP B.V. 2008. All Rights Reserved
517
Scenario 4: Clearing Message Lost Bit
517
Examples of Acceptance Filter Tables and ID Index Values
518
Not Used
518
NXP B.V. 2008. All Rights Reserved
518
Configuration Example
519
NXP B.V. 2008. All Rights Reserved
519
NXP B.V. 2008. All Rights Reserved
520
Not Used
521
NXP B.V. 2008. All Rights Reserved
521
NXP B.V. 2008. All Rights Reserved
522
Not Used
523
NXP B.V. 2008. All Rights Reserved
523
Look-Up Table Programming Guidelines
524
NXP B.V. 2008. All Rights Reserved
524
NXP B.V. 2008. All Rights Reserved
525
Basic Configuration
526
NXP B.V. 2008. All Rights Reserved
526
SPI Data Transfers
526
SPI Overview
526
NXP B.V. 2008. All Rights Reserved
527
General Information
528
Master Operation
528
NXP B.V. 2008. All Rights Reserved
528
SPI Peripheral Details
528
Exception Conditions
529
NXP B.V. 2008. All Rights Reserved
529
Slave Operation
529
NXP B.V. 2008. All Rights Reserved
530
Pin Description
530
NXP B.V. 2008. All Rights Reserved
531
Register Description
531
NXP B.V. 2008. All Rights Reserved
532
NXP B.V. 2008. All Rights Reserved
533
SPI Clock Counter Register (S0SPCCR - 0Xe002 000C)
533
SPI Test Control Register (SPTCR - 0Xe002 0010)
533
NXP B.V. 2008. All Rights Reserved
534
SPI Interrupt Register (S0SPINT - 0Xe002 001C) 534 Architecture
534
Spi Test Status Register (Sptsr - 0Xe)
534
NXP B.V. 2008. All Rights Reserved
535
Basic Configuration
536
Chapter 20: LPC24XX SSP Interface SSP0/1
536
Description
536
Features
536
NXP B.V. 2008. All Rights Reserved
536
Bus Description
537
Format
537
NXP B.V. 2008. All Rights Reserved
537
Pin Descriptions
537
Clock Polarity (CPOL) and Phase (CPHA) Control
538
NXP B.V. 2008. All Rights Reserved
538
SPI Frame Format
538
NXP B.V. 2008. All Rights Reserved
539
SPI Format with CPOL=0,CPHA=0
539
NXP B.V. 2008. All Rights Reserved
540
SPI Format with CPOL = 1,CPHA = 0
540
SPI Format with CPOL=0,CPHA=1
540
NXP B.V. 2008. All Rights Reserved
541
NXP B.V. 2008. All Rights Reserved
542
Semiconductor Microwire Frame Format
542
SPI Format with CPOL = 1,CPHA = 1
542
NXP B.V. 2008. All Rights Reserved
543
NXP B.V. 2008. All Rights Reserved
544
Register Description
544
Setup and Hold Time Requirements on CS with Respect to SK in Microwire Mode
544
NXP B.V. 2008. All Rights Reserved
545
Sspn Control Register 0 (SSP0CR0 - 0Xe006 8000, SSP1CR0 - 0Xe003 0000)
545
NXP B.V. 2008. All Rights Reserved
546
Sspn Control Register 1 (SSP0CR1 -
546
NXP B.V. 2008. All Rights Reserved
547
Sspn Data Register (SSP0DR - 0Xe006 8008
547
NXP B.V. 2008. All Rights Reserved
548
Sspn Interrupt Mask Set/Clear Register (SSP0IMSC - 0Xe006 8014, SSP1IMSC - 0Xe003 0014)
548
Sspn Status Register (SSP0SR - 0Xe006 800C, SSP1SR - 0Xe003 000C)
548
0Xe006 8010, SSP1CPSR - 0Xe003 0010)
548
NXP B.V. 2008. All Rights Reserved
549
Sspn Masked Interrupt Status Register (SSP0MIS - 0Xe006 801C, SSP1MIS - 0Xe003 001C)
549
Sspn Raw Interrupt Status Register (SSP0RIS -
549
NXP B.V. 2008. All Rights Reserved
550
Sspn Interrupt Clear Register (SSP0ICR -
550
Basic Configuration
551
Chapter 21 : LPC24XX SD/MMC Card Interface
551
Features of the MCI
551
Introduction
551
NXP B.V. 2008. All Rights Reserved
551
SD/MMC Card Interface Pin Description
551
Functional Overview
552
Mutimedia Card
552
NXP B.V. 2008. All Rights Reserved
552
Secure Digital Memory Card
552
MCI Adapter
553
NXP B.V. 2008. All Rights Reserved
553
SD/MMC Card Interface
553
Secure Digital Memory Card Bus Signals
553
Adapter Register Block
554
Command Path
554
Command Path State Machine
554
Control Unit
554
NXP B.V. 2008. All Rights Reserved
554
SD/MMC Card Interface
554
NXP B.V. 2008. All Rights Reserved
555
SD/MMC Card Interface
555
Command Format
556
NXP B.V. 2008. All Rights Reserved
556
SD/MMC Card Interface
556
Not Used
557
Data Path
557
Data Path State Machine
557
NXP B.V. 2008. All Rights Reserved
557
SD/MMC Card Interface
557
NXP B.V. 2008. All Rights Reserved
558
SD/MMC Card Interface
558
Data Counter
559
NXP B.V. 2008. All Rights Reserved
559
SD/MMC Card Interface
559
Bus Mode
560
CRC Token Status
560
NXP B.V. 2008. All Rights Reserved
560
SD/MMC Card Interface
560
CRC Generator
561
Data FIFO
561
NXP B.V. 2008. All Rights Reserved
561
SD/MMC Card Interface
561
Status Flags
561
NXP B.V. 2008. All Rights Reserved
562
Receive FIFO
562
SD/MMC Card Interface
562
Transmit FIFO
562
APB Interfaces
563
Clock Control Register
563
Interrupt Logic
563
NXP B.V. 2008. All Rights Reserved
563
Power Control Register
563
Register Description
563
SD/MMC Card Interface
563
0Xe008 C000)
564
0Xe008 C004)
564
NXP B.V. 2008. All Rights Reserved
564
SD/MMC Card Interface
564
NXP B.V. 2008. All Rights Reserved
565
SD/MMC Card Interface
565
Argument Register (Mciargument - 0Xe008 C008)
565
Command Register (Mcicommand - 0Xe008 C00C)
565
Command Response Register (Mcirespcommand - 0Xe008 C010)
566
NXP B.V. 2008. All Rights Reserved
566
Response Registers (Mciresponse0-3 - 0Xe008 C014, E008 C018, E008 C01C and E008 C020)
566
SD/MMC Card Interface
566
Data Length Register (Mcidatalength - 0Xe008 C028)
567
Data Timer Register (Mcidatatimer - 0Xe008 C024)
567
NXP B.V. 2008. All Rights Reserved
567
SD/MMC Card Interface
567
Data Control Register (Mcidatactrl - 0Xe008 C02C)
568
Data Counter Register (Mcidatacnt - 0Xe008 C030)
568
NXP B.V. 2008. All Rights Reserved
568
SD/MMC Card Interface
568
NXP B.V. 2008. All Rights Reserved
569
SD/MMC Card Interface
569
Status Register (Mcistatus - 0Xe008 C034)
569
Clear Register (Mciclear - 0Xe008 C038)
570
Interrupt Mask Registers (Mcimask0 - 0Xe008 C03C)
570
NXP B.V. 2008. All Rights Reserved
570
SD/MMC Card Interface
570
NXP B.V. 2008. All Rights Reserved
571
SD/MMC Card Interface
571
Basic Configuration
572
NXP B.V. 2008. All Rights Reserved
572
NXP B.V. 2008. All Rights Reserved
573
Not Used
573
I 2 C Operating Modes
574
Master Transmitter Mode
574
NXP B.V. 2008. All Rights Reserved
574
Pin Description
574
Master Receiver Mode
575
NXP B.V. 2008. All Rights Reserved
575
NXP B.V. 2008. All Rights Reserved
576
Slave Receiver Mode
576
Input Filters and Output Stages
577
NXP B.V. 2008. All Rights Reserved
577
Slave Transmitter Mode
577
NXP B.V. 2008. All Rights Reserved
578
Address Register I2ADDR
579
Arbitration and Synchronization Logic
579
NXP B.V. 2008. All Rights Reserved
579
Shift Register I2DAT
579
Control Register I2CONSET and I2CONCLR
580
NXP B.V. 2008. All Rights Reserved
580
Serial Clock Generator
580
Timing and Control
580
Not Used
581
NXP B.V. 2008. All Rights Reserved
581
Register Description
581
Status Decoder and Status Register
581
NXP B.V. 2008. All Rights Reserved
582
NXP B.V. 2008. All Rights Reserved
583
NXP B.V. 2008. All Rights Reserved
584
NXP B.V. 2008. All Rights Reserved
585
NXP B.V. 2008. All Rights Reserved
586
Operating Modes
586
NXP B.V. 2008. All Rights Reserved
587
NXP B.V. 2008. All Rights Reserved
588
NXP B.V. 2008. All Rights Reserved
589
NXP B.V. 2008. All Rights Reserved
590
NXP B.V. 2008. All Rights Reserved
591
NXP B.V. 2008. All Rights Reserved
592
NXP B.V. 2008. All Rights Reserved
593
NXP B.V. 2008. All Rights Reserved
594
NXP B.V. 2008. All Rights Reserved
595
NXP B.V. 2008. All Rights Reserved
596
NXP B.V. 2008. All Rights Reserved
597
NXP B.V. 2008. All Rights Reserved
598
Miscellaneous States
599
NXP B.V. 2008. All Rights Reserved
599
Data Transfer after Loss of Arbitration
600
NXP B.V. 2008. All Rights Reserved
600
Simultaneous Repeated START Conditions from Two Masters
600
Some Special Cases
600
Bus Error
601
NXP B.V. 2008. All Rights Reserved
601
NXP B.V. 2008. All Rights Reserved
602
Not Used
603
NXP B.V. 2008. All Rights Reserved
603
Software Example
603
I 2 C Interrupt Routine
604
Master States
604
NXP B.V. 2008. All Rights Reserved
604
NXP B.V. 2008. All Rights Reserved
605
NXP B.V. 2008. All Rights Reserved
606
NXP B.V. 2008. All Rights Reserved
607
NXP B.V. 2008. All Rights Reserved
608
NXP B.V. 2008. All Rights Reserved
609
NXP B.V. 2008. All Rights Reserved
610
Basic Configuration
611
NXP B.V. 2008. All Rights Reserved
611
NXP B.V. 2008. All Rights Reserved
612
NXP B.V. 2008. All Rights Reserved
613
Register Description
613
NXP B.V. 2008. All Rights Reserved
614
NXP B.V. 2008. All Rights Reserved
615
NXP B.V. 2008. All Rights Reserved
616
NXP B.V. 2008. All Rights Reserved
617
FIFO Controller
618
NXP B.V. 2008. All Rights Reserved
618
NXP B.V. 2008. All Rights Reserved
619
NXP B.V. 2008. All Rights Reserved
620
NXP B.V. 2008. All Rights Reserved
621
Multiple CAP and MAT Pins
622
NXP B.V. 2008. All Rights Reserved
622
Pin Description
622
NXP B.V. 2008. All Rights Reserved
623
NXP B.V. 2008. All Rights Reserved
624
NXP B.V. 2008. All Rights Reserved
625
Match Registers (MR0 - MR3)
626
NXP B.V. 2008. All Rights Reserved
626
NXP B.V. 2008. All Rights Reserved
627
Capture Registers (CR0 - CR3)
628
NXP B.V. 2008. All Rights Reserved
628
NXP B.V. 2008. All Rights Reserved
629
Example Timer Operation
630
NXP B.V. 2008. All Rights Reserved
630
NXP B.V. 2008. All Rights Reserved
631
NXP B.V. 2008. All Rights Reserved
632
NXP B.V. 2008. All Rights Reserved
633
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
633
NXP B.V. 2008. All Rights Reserved
634
NXP B.V. 2008. All Rights Reserved
635
Rules for Double Edge Controlled PWM Outputs
635
Rules for Single Edge Controlled PWM Outputs
635
NXP B.V. 2008. All Rights Reserved
636
NXP B.V. 2008. All Rights Reserved
637
Pin Description
637
Register Description
637
NXP B.V. 2008. All Rights Reserved
638
NXP B.V. 2008. All Rights Reserved
639
NXP B.V. 2008. All Rights Reserved
640
NXP B.V. 2008. All Rights Reserved
641
NXP B.V. 2008. All Rights Reserved
642
NXP B.V. 2008. All Rights Reserved
643
NXP B.V. 2008. All Rights Reserved
644
Not Used
645
NXP B.V. 2008. All Rights Reserved
645
NXP B.V. 2008. All Rights Reserved
646
Basic Configuration
647
Battery RAM
647
NXP B.V. 2008. All Rights Reserved
647
LPC24XX Real-Time Clock (RTC) and Battery RAM
648
Not Used
648
NXP B.V. 2008. All Rights Reserved
648
Battery RAM
649
NXP B.V. 2008. All Rights Reserved
649
Battery RAM
650
Interrupt Location Register (Ilr - 0Xe)
650
Miscellaneous Register Group
650
NXP B.V. 2008. All Rights Reserved
650
Rtc Interrupts
650
Battery RAM
651
NXP B.V. 2008. All Rights Reserved
651
Battery RAM
652
NXP B.V. 2008. All Rights Reserved
652
Alarm Mask Register (Amr - 0Xe)
653
Battery RAM
653
NXP B.V. 2008. All Rights Reserved
653
Battery RAM
654
Consolidated Time Registers
654
NXP B.V. 2008. All Rights Reserved
654
Battery RAM
655
Leap Year Calculation
655
NXP B.V. 2008. All Rights Reserved
655
Time Counter Group
655
Alarm Output
656
Alarm Register Group
656
Battery RAM
656
NXP B.V. 2008. All Rights Reserved
656
Rtc Usage Notes
656
Battery RAM
657
NXP B.V. 2008. All Rights Reserved
657
Reference Clock Divider (Prescaler)
657
Rtc Clock Generation
657
Battery RAM
658
Example of Prescaler Usage
658
NXP B.V. 2008. All Rights Reserved
658
Battery RAM
659
NXP B.V. 2008. All Rights Reserved
659
Prescaler Operation
659
Battery RAM
660
NXP B.V. 2008. All Rights Reserved
660
RTC External 32 Khz Oscillator Component Selection
660
Battery RAM
661
NXP B.V. 2008. All Rights Reserved
661
Chapter 27: Lpc24Xx Watchdog Timer (Wdt)
662
NXP B.V. 2008. All Rights Reserved
662
NXP B.V. 2008. All Rights Reserved
663
Register Description
663
NXP B.V. 2008. All Rights Reserved
664
NXP B.V. 2008. All Rights Reserved
665
Block Diagram
666
NXP B.V. 2008. All Rights Reserved
666
NXP B.V. 2008. All Rights Reserved
667
Pin Description
667
Chapter 28: LPC24XX Analog-To Digital Converter (ADC)
668
Not Used
668
NXP B.V. 2008. All Rights Reserved
668
A/D Control Register (Ad0Cr - 0Xe)
669
NXP B.V. 2008. All Rights Reserved
669
NXP B.V. 2008. All Rights Reserved
670
A/D Status Register (Ad0Stat - 0Xe)
671
NXP B.V. 2008. All Rights Reserved
671
NXP B.V. 2008. All Rights Reserved
672
Accuracy Vs. Digital Receiver
673
Hardware-Triggered Conversion
673
NXP B.V. 2008. All Rights Reserved
673
Chapter 29: Lpc24Xx Digital-To Analog Converter (Dac)
674
Not Used
674
NXP B.V. 2008. All Rights Reserved
674
NXP B.V. 2008. All Rights Reserved
675
NXP B.V. 2008. All Rights Reserved
676
Chapter 30: LPC24XX Flash Memory Programming Firmware
677
Criterion for Valid User Code
677
Memory Map after any Reset
677
NXP B.V. 2008. All Rights Reserved
677
NXP B.V. 2008. All Rights Reserved
678
NXP B.V. 2008. All Rights Reserved
679
Boot Process Flowchart
680
NXP B.V. 2008. All Rights Reserved
680
NXP B.V. 2008. All Rights Reserved
681
Sector Numbers
681
Code Read Protection (Crp)
682
NXP B.V. 2008. All Rights Reserved
682
ISP Commands
683
NXP B.V. 2008. All Rights Reserved
683
NXP B.V. 2008. All Rights Reserved
684
Set Baud Rate
684
NXP B.V. 2008. All Rights Reserved
685
Read Memory
685
NXP B.V. 2008. All Rights Reserved
686
Sector Number
686
Copy RAM to Flash
687
NXP B.V. 2008. All Rights Reserved
687
Blank Check Sector(S)
688
Erase Sector(S)
688
NXP B.V. 2008. All Rights Reserved
688
Read Part Identification Number
688
ISP Return Codes
689
NXP B.V. 2008. All Rights Reserved
689
Read Boot Code Version Number
689
IAP Commands
690
NXP B.V. 2008. All Rights Reserved
690
NXP B.V. 2008. All Rights Reserved
691
NXP B.V. 2008. All Rights Reserved
692
Prepare Sector(S) for Write Operation
692
Copy Ram to Flash
693
NXP B.V. 2008. All Rights Reserved
693
Blank Check Sector(S)
694
Erase Sector(S)
694
NXP B.V. 2008. All Rights Reserved
694
NXP B.V. 2008. All Rights Reserved
695
Reinvoke ISP
695
IAP Status Codes
696
JTAG Flash Programming Interface
696
NXP B.V. 2008. All Rights Reserved
696
Chapter 31: Lpc24Xx On-Chip Bootloader for Flashless Parts
697
Not Used
697
NXP B.V. 2008. All Rights Reserved
697
NXP B.V. 2008. All Rights Reserved
698
NXP B.V. 2008. All Rights Reserved
699
NXP B.V. 2008. All Rights Reserved
700
Ram Used by Iap Command Handler
700
Ram Used by Realmonitor
700
NXP B.V. 2008. All Rights Reserved
701
NXP B.V. 2008. All Rights Reserved
702
NXP B.V. 2008. All Rights Reserved
703
NXP B.V. 2008. All Rights Reserved
704
Not Used
705
NXP B.V. 2008. All Rights Reserved
705
Not Used
706
NXP B.V. 2008. All Rights Reserved
706
NXP B.V. 2008. All Rights Reserved
707
NXP B.V. 2008. All Rights Reserved
708
NXP B.V. 2008. All Rights Reserved
709
Not Used
710
NXP B.V. 2008. All Rights Reserved
710
NXP B.V. 2008. All Rights Reserved
711
Chapter 32: LPC24XX General Purpose DMA (GPDMA) Controller
712
Gpdma Functional Description
712
Memory Regions Accessible by the Gpdma
712
NXP B.V. 2008. All Rights Reserved
712
Ahb Slave Interface
713
Control Logic and Register Bank
713
Dma Request and Response Interface
713
NXP B.V. 2008. All Rights Reserved
713
NXP B.V. 2008. All Rights Reserved
714
NXP B.V. 2008. All Rights Reserved
715
Error Conditions
716
NXP B.V. 2008. All Rights Reserved
716
Channel Hardware
717
DMA Request Priority
717
Dma System Connections
717
NXP B.V. 2008. All Rights Reserved
717
Disabling the Gpdma
718
Enabling the Gpdma
718
NXP B.V. 2008. All Rights Reserved
718
Programming the Gpdma
718
Disabling a Dma Channel
719
Enabling a Dma Channel
719
Halting a Dma Transfer
719
NXP B.V. 2008. All Rights Reserved
719
Setup a New Dma Transfer
719
NXP B.V. 2008. All Rights Reserved
720
Programming a Dma Channel
720
Register Description
720
General Gpdma Registers
721
NXP B.V. 2008. All Rights Reserved
721
NXP B.V. 2008. All Rights Reserved
722
NXP B.V. 2008. All Rights Reserved
723
Not Used
724
NXP B.V. 2008. All Rights Reserved
724
NXP B.V. 2008. All Rights Reserved
725
NXP B.V. 2008. All Rights Reserved
726
Channel Registers
727
NXP B.V. 2008. All Rights Reserved
727
Channel Control Registers
728
NXP B.V. 2008. All Rights Reserved
728
Not Used
729
NXP B.V. 2008. All Rights Reserved
729
NXP B.V. 2008. All Rights Reserved
730
Protection and Access Information
730
Dmacc1Configuration - 0Xffe
731
NXP B.V. 2008. All Rights Reserved
731
Lock Control
732
NXP B.V. 2008. All Rights Reserved
732
Address Generation
733
Linked List Items
733
NXP B.V. 2008. All Rights Reserved
733
Example of Scatter/Gather Dma
734
NXP B.V. 2008. All Rights Reserved
734
Programming the Gpdma for Scatter/Gather Dma
734
Interrupt Requests
735
NXP B.V. 2008. All Rights Reserved
735
Gpdma Data Flow
736
Hardware Interrupt Sequence Flow
736
Interrupt Polling Sequence Flow
736
NXP B.V. 2008. All Rights Reserved
736
NXP B.V. 2008. All Rights Reserved
737
Peripheral-To-Peripheral Dma Flow
737
Memory-To-Memory Dma Flow
738
NXP B.V. 2008. All Rights Reserved
738
Flow Control
739
NXP B.V. 2008. All Rights Reserved
739
NXP B.V. 2008. All Rights Reserved
740
NXP B.V. 2008. All Rights Reserved
741
NXP B.V. 2008. All Rights Reserved
742
NXP B.V. 2008. All Rights Reserved
743
Chapter 34: Lpc24Xx Embedded Trace Module (Etm)
744
Etm Configuration
744
NXP B.V. 2008. All Rights Reserved
744
NXP B.V. 2008. All Rights Reserved
745
NXP B.V. 2008. All Rights Reserved
746
Reset State of Multiplexed Pins
746
NXP B.V. 2008. All Rights Reserved
747
Chapter 35: Lpc24Xx Realmonitor
748
NXP B.V. 2008. All Rights Reserved
748
NXP B.V. 2008. All Rights Reserved
749
Realmonitor Components
749
Rmhost
749
Rmtarget
749
How Realmonitor Works
750
NXP B.V. 2008. All Rights Reserved
750
Adding Stacks
751
How to Enable Realmonitor
751
IRQ Mode
751
NXP B.V. 2008. All Rights Reserved
751
SVC Mode
751
Undef Mode
751
NXP B.V. 2008. All Rights Reserved
752
Prefetch Abort Mode
752
Code Example
753
NXP B.V. 2008. All Rights Reserved
753
Rmtarget Initialization
753
NXP B.V. 2008. All Rights Reserved
754
NXP B.V. 2008. All Rights Reserved
755
NXP B.V. 2008. All Rights Reserved
756
Realmonitor Build Options
756
NXP B.V. 2008. All Rights Reserved
757
NXP B.V. 2008. All Rights Reserved
758
Abbreviations
759
NXP B.V. 2008. All Rights Reserved
759
Chapter 36: LPC24XX Supplementary Information
760
Definitions
760
Disclaimers
760
Legal Information
760
NXP B.V. 2008. All Rights Reserved
760
NXP B.V. 2008. All Rights Reserved
761
NXP B.V. 2008. All Rights Reserved
762
NXP B.V. 2008. All Rights Reserved
763
NXP B.V. 2008. All Rights Reserved
764
NXP B.V. 2008. All Rights Reserved
765
NXP B.V. 2008. All Rights Reserved
766
NXP B.V. 2008. All Rights Reserved
767
Uart3
767
NXP B.V. 2008. All Rights Reserved
768
NXP B.V. 2008. All Rights Reserved
769
SD/MMC Card Interface
769
NXP B.V. 2008. All Rights Reserved
770
NXP B.V. 2008. All Rights Reserved
771
NXP B.V. 2008. All Rights Reserved
772
NXP B.V. 2008. All Rights Reserved
773
NXP B.V. 2008. All Rights Reserved
774
System Control Block/Nxp B.V. 2008. All Rights Reserved
775
NXP B.V. 2008. All Rights Reserved
775
System Control Block
775
NXP B.V. 2008. All Rights Reserved
776
NXP B.V. 2008. All Rights Reserved
777
NXP B.V. 2008. All Rights Reserved
778
NXP B.V. 2008. All Rights Reserved
779
NXP B.V. 2008. All Rights Reserved
780
NXP B.V. 2008. All Rights Reserved
781
NXP B.V. 2008. All Rights Reserved
782
NXP B.V. 2008. All Rights Reserved
783
Uart3
783
NXP B.V. 2008. All Rights Reserved
784
NXP B.V. 2008. All Rights Reserved
785
NXP B.V. 2008. All Rights Reserved
786
SD/MMC Card Interface
786
NXP B.V. 2008. All Rights Reserved
787
NXP B.V. 2008. All Rights Reserved
788
Battery RAM
788
NXP B.V. 2008. All Rights Reserved
789
Battery RAM
789
NXP B.V. 2008. All Rights Reserved
790
NXP B.V. 2008. All Rights Reserved
791
: Lpc24Xx Supplementary Information
792
Chapter 36: LPC24XX Supplementary Information
792
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