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UM10237
LPC24XX User manual
Rev. 02 — 19 December 2008
Document information
Info
Content
Keywords
LPC2400, LPC2458, LPC2420, LPC2460, LPC2468, LPC2470, LPC2478,
ARM, ARM7, 32-bit, Single-chip, External memory interface, USB 2.0,
Device, Host, OTG, Ethernet, CAN, I2S, I2C, SPI, UART, PWM, IRC,
Microcontroller
Abstract
LPC24XX User manual release
User manual
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Chapters
Table of Contents
Related Manuals for NXP Semiconductors LPC24XX UM10237
Summary of Contents for NXP Semiconductors LPC24XX UM10237
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Page 1: Chapter 17: Lpc24Xx Universal Asynchronous Receiver/Transmitter (Uart)
UM10237 LPC24XX User manual Rev. 02 — 19 December 2008 Document information Info Content Keywords LPC2400, LPC2458, LPC2420, LPC2460, LPC2468, LPC2470, LPC2478, ARM, ARM7, 32-bit, Single-chip, External memory interface, USB 2.0, Device, Host, OTG, Ethernet, CAN, I2S, I2C, SPI, UART, PWM, IRC, Microcontroller Abstract LPC24XX User manual release... -
Page 2: Contact Information
NXP Semiconductors Revision history Date Description 20081219 LPC24XX user manual release. Modifications: • Added parts LPC2420. • Editorial updates. • AHB1 and AHB2 configuration registers added. 20080718 Initial LPC24XX user manual release. Replaces all draft versions UM10237_1.00 to UM10237_1.05. Contact information... -
Page 3: Chapter 1: Lpc24Xx Introductory Information
UM10237 Chapter 1: LPC24XX Introductory information Rev. 02 — 19 December 2008 1. Introduction NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speed Flash memory. -
Page 4: Lpc2400 Features
NXP Semiconductors Most features and peripherals are identical for all LPC2400 parts. All differences are listed Table 1–2. Table 2. LPC2458 LPC2460/20 LPC2468 LPC2470 LPC2478 3. LPC2400 features • ARM7TDMI-S processor, running at up to 72 MHz. • 98 kB on-chip SRAM includes: –... -
Page 5: Um10237
NXP Semiconductors – SPI controller. – Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller. – Three I – I S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA. -
Page 6: Applications
NXP Semiconductors • Boundary scan for simplified board testing. • Versatile pin function selections allow more possibilities for using on-chip peripheral functions. 4. Applications • Industrial control • Medical systems • Protocol converter • Communications 5. Ordering options 5.1 LPC2458 ordering options Table 3. -
Page 7: Lpc2468 Ordering Options
NXP Semiconductors Table 6. LPC2420/60 ordering options Type number Flash SRAM (kB) (kB) LPC2420FBD208 64 - LPC2460FBD208 64 16 16 2 LPC2460FET208 64 16 16 2 5.3 LPC2468 ordering options Table 7. LPC2468 ordering information Type number Package Name Description plastic low profile quad flat package;... -
Page 8: Lpc2478 Ordering Options
NXP Semiconductors Table 10. LPC2470 ordering options Type number Flash SRAM (kB) (kB) LPC2470FBD208 N/A LPC2470FET208 5.5 LPC2478 ordering options Table 11. LPC2478 ordering information Type number Package Name Description plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm LPC2478FBD208 LQFP208 LPC2478FET208 TFBGA208 plastic thin fine-pitch ball grid array package;... -
Page 9: On-Chip Flash Programming Memory (Lpc2458/68/78)
NXP Semiconductors The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1. -
Page 10: On-Chip Sram
NXP Semiconductors 8. On-chip SRAM The LPC2400 includes a SRAM memory of 64 kB reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. -
Page 11: Lpc2458 Block Diagram
NXP Semiconductors 9. LPC2458 block diagram LPC2458 P0, P1, P2, 64 kB P3, P4 SRAM HIGH-SPEED GPI/O CONTROLLERS 136 PINS TOTAL SRAM AHB2 16 kB ETHERNET SRAM MII/RMII MAC WITH EINT3 to EINT0 EXTERNAL INTERRUPTS P0, P2 2 × CAP0/CAP1/... -
Page 12: Lpc2420/60 Block Diagram
NXP Semiconductors 10. LPC2420/60 block diagram LPC2420/2460 P0, P1, P2, P3, P4 HIGH-SPEED GPI/O 160 PINS CONTROLLER TOTAL AHB2 16 kB ETHERNET SRAM MII/RMII MAC WITH EINT3 to EINT0 EXTERNAL INTERRUPTS P0, P2 2 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2/MAT3, TIMER2/TIMER3 2 ×... -
Page 13: Lpc2468 Block Diagram
NXP Semiconductors 11. LPC2468 block diagram LPC2468 P0, P1, P2, 64 kB P3, P4 SRAM HIGH-SPEED GPI/O CONTROLLERS 160 PINS TOTAL SRAM AHB2 16 kB ETHERNET SRAM MII/RMII MAC WITH EINT3 to EINT0 EXTERNAL INTERRUPTS P0, P2 2 × CAP0/CAP1/... -
Page 14: Lpc2470 Block Diagram
NXP Semiconductors 12. LPC2470 block diagram LPC2470 P0, P1, P2, P3, P4 HIGH-SPEED GPI/O 160 PINS CONTROLLER TOTAL AHB2 16 kB ETHERNET SRAM MII/RMII MAC WITH EINT3 to EINT0 EXTERNAL INTERRUPTS P0, P2 2 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2/MAT3, TIMER2/TIMER3 2 ×... -
Page 15: Lpc2478 Block Diagram
NXP Semiconductors 13. LPC2478 block diagram LPC2478 P0, P1, P2, 64 kB P3, P4 SRAM HIGH-SPEED GPI/O CONTROLLERS 160 PINS TOTAL SRAM AHB2 16 kB ETHERNET SRAM MII/RMII MAC WITH EINT3 to EINT0 EXTERNAL INTERRUPTS P0, P2 2 × CAP0/CAP1/... -
Page 16: Xe000
UM10237 Chapter 2: LPC24XX Memory mapping Rev. 02 — 19 December 2008 1. How to read this chapter The memory addressing and mapping for different LPC2400 parts depends on flash size, EMC size, and the LCD peripheral, see Table 13. LPC2458 LPC2420 LPC2460... -
Page 17: Xe001
NXP Semiconductors Table 15. LPC2420/60/70 memory usage and details Address range General use 0x0000 0000 to Fast I/O 0x3FFF FFFF 0x4000 0000 to On-chip RAM 0x7FFF FFFF 0x8000 0000 to Off-Chip Memory 0xDFFF FFFF 0xE000 0000 to APB Peripherals 0xEFFF FFFF... -
Page 18: Xe002
NXP Semiconductors Table 16. LPC2468/78 memory usage and details Address range General use 0x8000 0000 to Off-Chip Memory 0xDFFF FFFF 0xE000 0000 to APB Peripherals 0xEFFF FFFF 0xF000 0000 to AHB peripherals 0xFFFF FFFF 3. Memory maps The LPC2400 incorporates several distinct memory regions, shown in the following figures. -
Page 19: Xe003
NXP Semiconductors 4.0 GB 3.75 GB 3.5 GB 2.0 GB 1.0 GB 0.0 GB Fig 6. LPC2400 system memory map UM10237_2 User manual Chapter 2: LPC24XX Memory mapping AHB PERIPHERALS APB PERIPHERALS EXTERNAL STATIC AND DYNAMIC MEMORY BOOT ROM AND BOOT FLASH... -
Page 20: Xe004
NXP Semiconductors 4.0 GB - 2 MB 3.5 GB + 2 MB Fig 7. Peripheral memory map Figure AHB and APB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the address decoding for each peripheral. - Page 21 NXP Semiconductors All peripheral register addresses are word aligned (to 32 bit boundaries) regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8 bit) or half-word (16 bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once.
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Page 22: Table Of Contents
NXP Semiconductors 4. APB peripheral addresses The following table shows the APB address map. No APB peripheral uses all of the 16 kB space allocated to it. Typically each device’s registers are "aliased" or repeated at multiple locations within each 16 kB range. -
Page 23: Lpc2400 Memory Re-Mapping And Boot Rom
NXP Semiconductors 5. LPC2400 memory re-mapping and boot ROM 5.1 Memory map concepts and operating modes The basic concept on the LPC2400 is that each memory area has a "natural" location in the memory map. This is the address range for which code residing in that area is written. -
Page 24: Memory Re-Mapping
NXP Semiconductors Table 19. Mode Boot Loader mode User Flash mode User RAM mode User External memory mode See EMCControl register address mirror bit in Connect external boot memory to chip select 1. During boot from external memory, the address mirror bit is set and memory bank addresses 0 and 1 are swapped. -
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NXP Semiconductors Re-mapped memory areas, including the Boot ROM and interrupt vectors, continue to appear in their original location in addition to the re-mapped address. Details on re-mapping and examples can be found in control” on page 6. Memory mapping control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. -
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NXP Semiconductors read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of MEMMAP[1:0] = 00 (Boot Loader Mode), read/fetch from 0x0000 0008 will provide data available also at 0x7FFF E008 (Boot ROM remapped from on-chip Bootloader). -
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NXP Semiconductors 7. Prefetch abort and data abort exceptions The LPC2400 generates the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or unassigned address region. The regions are: • Areas of the memory map that are not implemented for a specific ARM derivative. For the LPC2400, these are: –... -
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UM10237 Chapter 3: LPC24XX System control Rev. 02 — 19 December 2008 1. Summary of system control block functions The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include: •... -
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NXP Semiconductors Table 23. Name Reset RSID Syscon miscellaneous registers AHB priority scheduling registers AHBCFG1 AHBCFG2 Reset Value reflects the data stored in used bits only. It does not include reserved bits content. 3.1 External interrupt inputs The LPC2400 includes four External Interrupt Inputs as selectable pin functions. In addition, external interrupts have the ability to wake up the CPU from Power down mode. -
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NXP Semiconductors Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise event that was just triggered by activity on the EINT pin will not be recognized in future. -
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NXP Semiconductors 3.1.3 External Interrupt Mode register (EXTMODE - 0xE01F C148) The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins that are selected for the EINT function (see VICIntEnable register 0xFFFF F010)”) can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions). -
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NXP Semiconductors Table 27. Bit Symbol EXTPOLAR0 0 EXTPOLAR1 0 EXTPOLAR2 0 EXTPOLAR3 0 7:4 - 3.2 Reset Reset has four sources on the LPC2400: the RESET pin, the Watchdog Reset, Power On Reset (POR) and the Brown Out Detection circuit (BOD). The RESET pin is a Schmitt trigger input pin. -
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NXP Semiconductors external reset watchdog reset power down EINT0 wakeup EINT1 wakeup EINT2 wakeup EINT3 wakeup RTC wakeup BOD wakeup Ethernet MAC wakeup USB need_clk wakeup CAN wakeup GPIO0 port wakeup GPIO2 port wakeup Fig 10. Reset block diagram including the wakeup timer... -
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NXP Semiconductors IRC status RESET DD(3V3) supply ramp-up time processor status Fig 11. Example of start-up after reset The various Resets have some small differences. For example, a Power On Reset causes the value of certain pins to be latched to configure the part. -
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NXP Semiconductors Table 28. Symbol Description EXTR WDTR BODR 3.3 Other system controls and status flags Some aspects of controlling LPC2400 operation that do not fit into peripheral or other registers are grouped here. 3.3.1 System Controls and Status register (SCS - 0xE01F C1A0) Table 29. -
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NXP Semiconductors Table 29. System Controls and Status register (SCS - address 0xE01F C1A0) bit description Symbol Value Description Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. MCIPWR MCIPWR pin control. -
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NXP Semiconductors Table 31. Symbol scheduler break_burst quantum_type quantum_size 10:8 default_master 14:12 EP1 19:16 EP2 22:20 EP3 26:24 EP4 30:28 EP5 Allowed values for nnn are: 101 (highest priority), 100, 011, 010, 001 (lowest priority). 3.4.1.1 Examples of AHB1 settings The following examples use the LPC2478 to illustrate how to select the priority of each AHB1 master based on different system requirements. -
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NXP Semiconductors Table 32. Symbol 14:12 18:16 22:20 26:24 30:28 Table 33. Symbol 14:12 18:16 22:20 26:24 30:28 Table 34. Symbol 14:12 18:16 22:20 26:24 30:28 Sequence based on round-robin. Table 35. Symbol 14:12 18:16 22:20 26:24 30:28 Sequence based on round-robin. -
Page 39: Examples Of Ahb2 Settings
NXP Semiconductors Table 36. Symbol scheduler break_burst quantum_type quantum_size default_master 13:12 EP1 17:16 EP2 31:18 - Allowed values for nn are: 10 (high priority) and 01 (low priority). 3.4.2.1 Examples of AHB2 settings Table 37. Symbol 13:12 18:16 UM10237_2 User manual... -
Page 40: Brown-Out Detection
NXP Semiconductors Table 38. Symbol 13:12 18:16 Sequence based on round-robin. 4. Brown-out detection The LPC2400 includes 2-stage monitoring of the voltage on the V voltage falls below 2.95 V, the Brown-Out Detector (BOD) asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt... -
Page 41: Chapter 4: Lpc24Xx Clocking And Power Control
UM10237 Chapter 4: LPC24XX Clocking and power control Rev. 02 — 19 December 2008 1. Summary of clocking and power control functions This section describes the generation of the various clocks needed by the LPC2400 and options of clock source selection, as well as power control and wakeup from reduced power modes. - Page 42 NXP Semiconductors MAIN OSCILLATOR system (CLKSRCSEL) INTERNAL OSCILLATOR (WDTCLKSEL) OSCILLATOR Fig 12. Clock generation for the LPC2400 UM10237_2 User manual Chapter 4: LPC24XX Clocking and power control USB clock config pllclk (USBCLKCFG) clock BYPASS select SYNCHRO- CPU clock config NIZER...
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Page 43: Oscillators
NXP Semiconductors 2. Oscillators The LPC2400 includes three independent oscillators. These are the Main Oscillator, the Internal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following Reset, the LPC2400 will operate from the Internal RC Oscillator until switched by software. -
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NXP Semiconductors LPC24xx XTAL1 XTAL2 Clock Fig 13. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external crystal model used for C Table 39. Fundamental oscillation frequency 1 MHz - 5 MHz 5 MHz - 10 MHz... -
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NXP Semiconductors register) so that software can determine when the oscillator is running and stable. At that point, software can control switching to the main oscillator as a clock source. Prior to starting the main oscillator, a frequency range must be selected by configuring the OSCRANGE bit in the SCS register. -
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NXP Semiconductors • The IRC oscillator cannot be used as clock source for the USB block. • The IRC oscillator cannot be used as clock source for the CAN controllers if the CAN baud rate is larger than 100 kbit/s. -
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NXP Semiconductors PLLC PLLE pllclkin = 18.432 MHz N-DIVIDER NSEL[23:16] 1.152 MHz MSEL[14:0] Fig 14. PLL block diagram (N = 16, M = 125, USBSEL = 6, CCLKSEL = 4) PLL activation is controlled via the PLLCON register. The PLL multiplier and divider values are controlled by the PLLCFG register. -
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NXP Semiconductors Table 43. Name PLLCON PLLCFG PLLSTAT PLLFEED Reset Value reflects the data stored in used bits only. It does not include reserved bits content. 3.2.4 PLL Control register (PLLCON - 0xE01F C080) The PLLCON register contains the bits that enable and connect the PLL. Enabling the PLL allows it to attempt to lock to the current settings of the multiplier and divider values. -
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NXP Semiconductors disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is likely that the oscillator clock has become unstable and disconnecting the PLL will not remedy the situation. 3.2.5 PLL Configuration register (PLLCFG - 0xE01F C084) The PLLCFG register contains the PLL multiplier and divider values. -
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NXP Semiconductors Table 46. Multiplier (M) 6836 6866 6958 7050 7324 7425 7690 7813 7935 8057 8100 8545 8789 9155 9613 10254 10376 10986 11719 12085 12207 12817 12817 13184 13184 13672 13733 13733 13916 14099 14420 14648 15381 15381... -
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NXP Semiconductors Table 46. Multiplier (M) 18311 19226 19775 20508 20599 20874 21149 21973 23071 23438 23804 24170 3.2.6 PLL Status register (PLLSTAT - 0xE01F C088) The read-only PLLSTAT register provides the actual PLL parameters that are in effect at the time it is read, as well as the PLL status. -
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NXP Semiconductors connected for use. The value of PLOCK may not be stable when the PLL reference frequency (F divided by the pre-divider value) is less than 100 kHz or greater than 20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time has passed. This time is 500 μs when FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less... -
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NXP Semiconductors 3.2.11 PLL frequency calculation The PLL equations use the following parameters: Table 50. Parameter The PLL output frequency (when the PLL is both active and connected) is given by: = (2 × M × F The PLL inputs and settings must meet the following: •... -
Page 54: Procedure For Determining Pll Settings
NXP Semiconductors Table 51. 16479 19775 21973 3.2.12 Procedure for determining PLL settings PLL parameter determination can be simplified by using a spreadsheet available from NXP. To determine PLL parameters by hand, the following general procedure may be used: 1. Determine if the application requires use of the USB interface. The USB requires a 50% duty cycle clock of 48 MHz within a very small tolerance, which means that F must be an even integer multiple of 48 MHz (i.e. -
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NXP Semiconductors M = (F Start by assuming N = 1, since this produces the smallest multiplier needed for the PLL. So, M = 288 × 10 look further for a good set of PLL configuration values. The value written to PLLCFG would be 0x23 (N - 1 = 0;... -
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NXP Semiconductors In general, larger vlaues of F frequency. Even the first table entry shows a very small error of just over 1 hundredth of a percent, or 107 parts per million (ppm). If that is not accurate enough in the application, the second case gives a much smaller error of 7 ppm. -
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NXP Semiconductors 3.3.1 CPU Clock Configuration register (CCLKCFG - 0xE01F C104) The CCLKCFG register controls the division of the PLL output before it is used by the CPU. When the PLL is bypassed, the division may be by 1. When the PLL is running, the output must be divided in order to bring the CPU clock frequency (cclk) within operating limits. -
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NXP Semiconductors Table 55. Symbol IRCtrim 15:8 3.3.4 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 - 0xE01F C1A8 and PCLKSEL1 - 0xE01F C1AC) A pair of bits in a Peripheral Clock Selection register controls the rate of the clock signal that will be supplied to the corresponding peripheral as specified in Table 4–57... -
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NXP Semiconductors Table 57. Symbol 13:12 PCLK_TIMER2 15:14 PCLK_TIMER3 17:16 PCLK_UART2 19:18 PCLK_UART3 21:20 PCLK_I2C2 23:22 PCLK_I2S 25:24 PCLK_MCI 27:26 29:28 PCLK_SYSCON 31:30 Table 58. PCLKSEL0 and PCLKSEL1 individual peripheral’s clock select options For PCLK_RTC only, the value ’01’ is illegal. Do not write ’01’ to the PCLK_RTC. Attempting to write ’01’... -
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NXP Semiconductors In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. -
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NXP Semiconductors 3.4.5 Power control register description The Power Control function uses registers shown in descriptions follow. Table 59. Name PCON INTWAKE Interrupt Wakeup Register. Controls which PCONP Reset Value reflects the data stored in used bits only. It does not include reserved bits content. -
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NXP Semiconductors Table 60. Symbol BORD Encoding of Reduced Power Modes The PM2, PM1, and PM0 bits in PCON allow entering reduced power modes as needed. The encoding of these bits allows backward compatibility with devices that previously only supported Idle and Power-down modes. -
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NXP Semiconductors Table 62. Symbol EXTWAKE0 EXTWAKE1 EXTWAKE2 EXTWAKE3 ETHWAKE USBWAKE CANWAKE GPIO0WAKE GPIO2WAKE 13:9 BODWAKE RTCWAKE 3.4.8 Power Control for Peripherals register (PCONP - 0xE01F C0C4) The PCONP register allows turning off selected peripheral functions for the purpose of saving power. -
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NXP Semiconductors Some peripherals, particularly those that include analog functions, may consume power that is not clock dependent. These peripherals may contain a separate disable control that turns off additional circuitry to reduce power. Information on peripheral specific power saving features may be found in the chapter describing that peripheral. -
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NXP Semiconductors Table 63. Symbol PCI2S PCSDC PCGPDMA GP DMA function power/clock control bit. PCENET PCUSB LPC247x only. 3.4.9 Power control usage notes After every reset, the PCONP register contains the value that enables selected interfaces and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper configuring via peripheral dedicated registers, the user’s application might have to access... -
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NXP Semiconductors whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wakeup of the processor from Power-down mode makes use of the Wakeup Timer. -
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UM10237 Chapter 5: LPC24XX External Memory Controller (EMC) Rev. 02 — 19 December 2008 1. How to read this chapter This chapter describes the external memory controller for all LPC2400 parts. For EMC configurations that are specific to LPC2458 and LPC2420/60/68/70/78, see Table 64. -
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NXP Semiconductors 3. Pins: Select data, address, and control pins and their modes in PINSEL6/8/9 and PINMODE6/8/9 (see 4. Configuration: see 3. Introduction The LPC2400 External Memory Controller (EMC) is an ARM PrimeCell™ MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM and Flash, as well as dynamic memories such as Single Data Rate SDRAM. -
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NXP Semiconductors AHB SLAVE REGISTER INTERFACE AHB SLAVE MEMORY INTERFACE Fig 15. EMC block diagram The functions of the EMC blocks are described in the following sections: • AHB slave register interface. • AHB slave memory interfaces. • Data buffers. -
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NXP Semiconductors 5.2 AHB slave memory interface The AHB slave memory interface allows access to external memories. 5.2.1 Memory transaction endianness The endianness of the data transfers to and from the external memories is determined by the Endian mode (N) bit in the EMCConfig register. -
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NXP Semiconductors • If the buffers are enabled, an AHB write operation writes into the Least Recently Used (LRU) buffer, if empty. If the LRU buffer is not empty, the contents of the buffer are flushed to memory to make space for the AHB write data. -
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NXP Semiconductors Self-refresh mode can be entered by software by setting the SREFREQ bit in the EMCDynamicControl Register and polling the SREFACK bit in the EMCStatus Register. Any transactions to memory that are generated while the memory controller is in self-refresh mode are rejected and an error response is generated to the AHB bus. -
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NXP Semiconductors 8. Reset The EMC receives two reset signals. One is Power-On Reset (POR), asserted when chip power is applied, and when a brown-out condition is detected (see the System Control Block chapter for details of Brown-Out Detect). The other reset is from the external Reset pin and the Watchdog Timer. -
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NXP Semiconductors Table 66. Name CLKOUT[1:0] CKEOUT[3:0] DQMOUT[3:0] 10. Register description This chapter describes the EMC registers and provides details required when programming the microcontroller. The EMC registers are shown in Table 67. Summary of EMC registers Address Register Name... -
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NXP Semiconductors Table 67. Summary of EMC registers Address Register Name 0xFFE0 8124 EMCDynamic RasCas1 0xFFE0 8140 EMCDynamic Config2 0xFFE0 8144 EMCDynamic RasCas2 0xFFE0 8160 EMCDynamic Config3 0xFFE0 8164 EMCDynamic RasCas3 0xFFE0 8200 EMCStatic Config0 0xFFE0 8204 EMCStatic WaitWen0 0xFFE0 8208... -
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NXP Semiconductors Table 67. Summary of EMC registers Address Register Name 0xFFE0 8268 EMCStatic WaitOen3 0xFFE0 826C EMCStatic WaitRd3 0xFFE0 8270 EMCStatic WaitPage3 0xFFE0 8274 EMCStatic WaitWr3 0xFFE0 8278 EMCStatic WaitTurn3 Reset Value reflects the data stored in used bits only. It does not include reserved bits content. -
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NXP Semiconductors Table 68. Symbol Low-power mode 31:3 The external memory cannot be accessed in low-power or disabled state. If a memory access is performed an AHB error response is generated. The EMC registers can be programmed in low-power and/or disabled state. -
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NXP Semiconductors 10.3 EMC Configuration register (EMCConfig - 0xFFE0 8008) The EMCConfig register configures the operation of the memory controller. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. -
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NXP Semiconductors Table 71. Symbol Self-refresh request, EMCSREFREQ (SR) Memory clock control (MMC) SDRAM initialization (I) 12:9 Low-power SDRAM deep-sleep mode (DP) 31:14 - Clock enable must be HIGH during SDRAM initialization. The memory controller exits from power-on reset with the self-refresh bit HIGH. To enter normal functional mode set this bit LOW. -
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NXP Semiconductors 10.5 Dynamic Memory Refresh Timer register (EMCDynamicRefresh - 0xFFE0 8024) The EMCDynamicRefresh register configures dynamic memory operation. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. -
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NXP Semiconductors 10.6 Dynamic Memory Read Configuration register (EMCDynamicReadConfig - 0xFFE0 8028) The EMCDynamicReadConfig register configures the dynamic memory read strategy. This register must only be modified during system initialization. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed. -
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NXP Semiconductors Table 74. Symbol Precharge command period (tRP) 31:4 10.8 Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS - 0xFFE0 8034) The EMCDynamicTRAS register enables you to program the active to precharge command period, tRAS. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. -
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NXP Semiconductors Table 76. Symbol Self-refresh exit time (tSREX) 31:4 10.10 Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR - 0xFFE0 803C) The EMCDynamicTAPR register enables you to program the last-data-out to active command time, tAPR. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. -
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NXP Semiconductors Table 78. Symbol Data-in to active command (tDAL) 31:4 10.12 Dynamic Memory Write Recovery Time register (EMCDynamictWR - 0xFFE0 8044) The EMCDynamicTWR register enables you to program the write recovery time, tWR. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. -
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NXP Semiconductors Table 80. Symbol Active to active command period (tRC) 31:5 10.14 Dynamic Memory Auto-refresh Period register (EMCDynamictRFC - 0xFFE0 804C) The EMCDynamicTRFC register enables you to program the auto-refresh period, and auto-refresh to active command period, tRFC. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. -
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NXP Semiconductors Table 82. Symbol Exit self-refresh to active command time (tXSR) 31:5 10.16 Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD - 0xFFE0 8054) The EMCDynamicTRRD register enables you to program the active bank A to active bank B latency, tRRD. -
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NXP Semiconductors Table 84. Symbol Load mode register to active command time (tMRD) 31:4 10.18 Static Memory Extended Wait register (EMCStaticExtendedWait - 0xFFE0 8080) ExtendedWait (EW) bit in the EMCStaticConfig register is set. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. -
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NXP Semiconductors Table 86. Symbol Memory device (MD) 12:7 Address mapping (AM) Address mapping (AM) 18:15 - Buffer enable Write protect (P) 0 31:21 - The SDRAM column and row width and number of banks are computed automatically from the address mapping. -
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NXP Semiconductors Table 87. 11:9 8:7 16 bit external bus low-power SDRAM address mapping (Bank, Row, Column) 32 bit external bus high-performance address mapping (Row, Bank, Column) 32 bit external bus low-power SDRAM address mapping (Bank, Row, Column) UM10237_2 User manual... -
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NXP Semiconductors Table 87. 11:9 8:7 A chip select can be connected to a single memory device, in this case the chip select data bus width is the same as the device width. Alternatively the chip select can be connected to a number of external devices. In this case the chip select data bus width is the sum of the memory device data bus widths. -
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NXP Semiconductors 10.21 Static Memory Configuration registers (EMCStaticConfig0-3 - 0xFFE0 8200, 220, 240, 260) The EMCStaticConfig0-3 registers configure the static memory configuration. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. -
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NXP Semiconductors Table 89. Symbol Byte lane state (PB) Extended wait (EW) 18:9 Buffer enable Write protect (P) 0 31:21 - Extended wait and page mode cannot be selected simultaneously. EMC may perform burst read access even when the buffer enable bit is cleared. -
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NXP Semiconductors Table 5–90 Table 90. Symbol Wait write enable (WAITWEN) 31:4 10.23 Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3 - 0xFFE0 8208, 228, 248, 268) The EMCStaticWaitOen0-3 registers enable you to program the delay from the chip select or address change, whichever is later, to the output enable. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. -
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NXP Semiconductors Table 92. Symbol Non-page mode read wait states or asynchronous page mode readfirst access wait state (WAITRD) 31:5 10.25 Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3 - 0xFFE0 8210, 230, 250, 270) The EMCStaticWaitPage0-3 registers enable you to program the delay for asynchronous page mode sequential accesses. -
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NXP Semiconductors Table 94. Symbol Write wait states (WAITWR) 31:5 10.27 Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3 - 0xFFE0 8218, 238, 258, 278) The EMCStaticWaitTurn0-3 registers enable you to program the number of bus turnaround cycles. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. -
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NXP Semiconductors Symbol "a_b" in the following figures refers to the highest order address line in the data bus. Symbol "a_m" refers to the highest order address line of the memory chip used in the external memory interface. If the external memory is used as external boot memory for flashless devices, refer to Section 8–6... -
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NXP Semiconductors c. 32 bit wide memory bank interfaced to one 8 bit memory chip Fig 16. 32 bit bank external memory interfaces ( bits MW = 10) 11.2 16-bit wide memory bank connection A[a_b:1] a. 16 bit wide memory bank interfaced to two 8 bit memory chips b. -
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NXP Semiconductors 11.3 8-bit wide memory bank connection Fig 18. 8 bit bank external memory interface (bits MW = 00) UM10237_2 User manual Chapter 5: LPC24XX External Memory Controller (EMC) BLS[0] IO[7:0] D[7:0] A[a_m:0] A[a_b:0] Rev. 02 — 19 December 2008 UM10237 ©... -
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NXP Semiconductors 11.4 Memory configuration example A[20:0] BLS3 BLS2 BLS1 BLS0 Fig 19. Typical memory configuration diagram UM10237_2 User manual Chapter 5: LPC24XX External Memory Controller (EMC) D[31:0] A[20:0] A[20:0] Q[31:0] 2Mx32 Burst Mask ROM A[15:0] D[31:16] A[15:0] IO[15:0] A[15:0]... -
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UM10237 Chapter 6: LPC24XX Memory Accelerator Module (MAM) Rev. 02 — 19 December 2008 1. How to read this chapter The Memory Accelerator Module operates in combination with the flash controller and is available in parts LPC2458/68/78. 2. Introduction The MAM block in the LPC2400 maximizes the performance of the ARM processor when it is running code in Flash memory using a single Flash bank. -
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NXP Semiconductors Branches and other program flow changes cause a break in the sequential flow of instruction fetches described above. The Branch Trail buffer captures the line to which such a non-sequential break occurs. If the same branch is taken again, the next instruction is taken from the Branch Trail buffer. -
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NXP Semiconductors Fig 20. Simplified block diagram of the Memory Accelerator Module 4.2 Instruction latches and data latches Code and Data accesses are treated separately by the Memory Accelerator Module. There is a 128 bit Latch, a 15 bit Address Latch, and a 15 bit comparator associated with each buffer (prefetch, branch trail, and data). -
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NXP Semiconductors Mode 1: MAM partially enabled. Sequential instruction accesses are fulfilled from the holding latches if the data is present. Instruction prefetch is enabled. Non-sequential instruction accesses initiate Flash read operations (see that all branches cause memory fetches. All data operations cause a Flash read because buffered data access timing is hard to predict and is very situation dependent. -
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NXP Semiconductors 7. Register description The MAM is controlled by the registers shown in follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic zero. Table 98. Name Description MAMCR Memory Accelerator Module Control Register. -
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NXP Semiconductors Table 100. MAM Timing register (MAMTIM - address 0xE01F C004) bit description Symbol MAM_fetch_ cycle_timing UM10237_2 User manual Chapter 6: LPC24XX Memory Accelerator Module (MAM) Value Description These bits set the duration of MAM fetch operations. 0 - Reserved... -
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NXP Semiconductors INCREMENTOR ENAL0 ADDR cclk [18:4] EQA0 ADDR PREFETCH LATCH EQPREF LA[3:2] PREFETCH MUX Fig 21. Block diagram of the Memory Accelerator Module 8. MAM usage notes When changing MAM timing, the MAM must first be turned off by writing a zero to MAMCR. -
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NXP Semiconductors Table 101. Suggestions for MAM timing selection system clock < 20 MHz 20 MHz to 40 MHz 40 MHz to 60 MHz > 60 MHz UM10237_2 User manual Chapter 6: LPC24XX Memory Accelerator Module (MAM) Number of MAM fetch cycles in MAMTIM... -
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UM10237 Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Rev. 02 — 19 December 2008 1. Features • ARM PrimeCell Vectored Interrupt Controller • Mapped to AHB address space for fast access • Supports 32 vectored IRQ interrupts • 16 programmable interrupt priority levels •... -
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NXP Semiconductors Table 102. Summary of VIC registers Name Description VICIRQStatus IRQ Status Register. This register reads out the state of those interrupt requests that are enabled and classified as IRQ. VICFIQStatus FIQ Status Requests. This register reads out the state of those interrupt requests that are enabled and classified as FIQ. -
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NXP Semiconductors Table 102. Summary of VIC registers Name Description VICVectAddr19 Vector address 19 register. VICVectAddr20 Vector address 20 register. VICVectAddr21 Vector address 21 register. VICVectAddr22 Vector address 22 register. VICVectAddr23 Vector address 23 register. VICVectAddr24 Vector address 24 register. -
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NXP Semiconductors Table 102. Summary of VIC registers Name Description VICVectPriority26 Vector priority 26 register. VICVectPriority27 Vector priority 27 register. VICVectPriority28 Vector priority 28 register. VICVectPriority29 Vector priority 29 register. VICVectPriority30 Vector priority 30 register. VICVectPriority31 Vector priority 31 register. -
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NXP Semiconductors Table 105. Raw Interrupt Status register (VICRawIntr - address 0xFFFF F008) bit description Symbol 31:0 See Table 7–117 “Interrupt sources bit allocation table”. 3.4 Interrupt Enable Register (VICIntEnable - 0xFFFF F010) This is a read/write accessible register. This register controls which of the 32 combined hardware and software interrupt requests are enabled to contribute to FIQ or IRQ. -
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NXP Semiconductors Table 108. Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit description Symbol 31:0 See Table 7–117 “Interrupt sources bit allocation table”. 3.7 IRQ Status Register (VICIRQStatus - 0xFFFF F000) This is a read only register. This register reads out the state of those interrupt requests that are enabled and classified as IRQ. -
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NXP Semiconductors Table 111. Vector Address registers 0-31 (VICVectAddr0-31 - addresses 0xFFFF F100 to Symbol 31:0 VICVectAddr The VIC provides the contents of one of these registers in 3.10 Vector Priority Registers 0-31 (VICVectPriority0-31 - 0xFFFF F200 to 27C) These registers select a priority level for the 32 vectored IRQs. There are 16 priority levels, corresponding to the values 0 through 15 decimal, of which 15 is the lowest priority. -
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NXP Semiconductors Table 114. Software Priority Mask register (VICSWPriorityMask - address 0xFFFF F024) bit Symbol 15:0 VICSWPriorityMask 0 31:16 - 3.13 Protection Enable Register (VICProtection - 0xFFFF F020) This is a read/write accessible register. This one bit register controls access to the VIC registers by software running in User mode. -
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NXP Semiconductors Table 116. Connection of interrupt sources to the Vectored Interrupt Controller Block UART1 PWM0, PWM1 SPI, SSP0 SSP 1 System Control (External Interrupts) ADC0 Ethernet UM10237_2 User manual Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Flag(s) Rx Line Status (RLS) -
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NXP Semiconductors Table 116. Connection of interrupt sources to the Vectored Interrupt Controller Block SD/ MMC interface GP DMA Timer 2 Timer 3 UART 2 UART 3 Table 117. Interrupt sources bit allocation table Symbol I2C2 Symbol CAN1&2 Symbol EINT1... -
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NXP Semiconductors interrupt request, masking, and selection SoftIntClear [31:0] SoftInt [31:0] VICINT SOURCE [31:0] RawIntr [31:0] vectored interrupt 0 IRQStatus SWPriorityMask [0] HWPriorityMask [0] VectPriority0 [3:0] vectored interrupt 1 IRQStatus vectored interrupt 31 IRQStatus [31] Fig 22. Block diagram of the Vectored Interrupt Controller... -
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UM10237 Chapter 8: LPC24XX Pin configuration Rev. 02 — 19 December 2008 1. How to read this chapter For information about the individual LPC2400 parts, refer to table LPC2460 and LPC2470 are flashless and use pins P3[15] and P3[14] for boot control. Table 118. -
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NXP Semiconductors 2.2 LPC2400 208-pin packages Fig 24. LPC2400 pinning LQFP208 package Fig 25. LPC2400 pinning TFBGA208 package 3. LPC2458 pinning information Table 119. LPC2458 pin allocation table Pin Symbol Pin Symbol Row A P3[12]/D12 P3[2]/D2 P1[1]/ENET_TXD1 P3[8]/D8 P1[3]/ENET_TXD3/ MCICMD/PWM0[2]... -
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NXP Semiconductors Table 119. LPC2458 pin allocation table Pin Symbol Pin Symbol P3[11]/D11 P1[0]/ENET_TXD0 P1[8]/ENET_CRS_DV/ ENET_CRS P4[29]/BLS3/ P1[6]/ENET_TX_CLK/ MAT2[1]/RXD3 MCIDAT0/PWM0[4] P1[5]/ENET_TX_ER/ P4[13]/A13 MCIPWR/PWM0[3] Row C P3[13]/D13 P1[4]/ENET_TX_EN DD(3V3) P1[17]/ENET_MDIO P4[15]/A15 P1[7]/ENET_COL/ P2[1]/PWM1[2]/RXD1/ MCIDAT1/PWM0[5] PIPESTAT0 Row D P0[26]/AD0[3]/ AOUT/RXD3 P0[2]/TXD0 P3[0]/D0... -
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NXP Semiconductors Table 119. LPC2458 pin allocation table Pin Symbol Pin Symbol RSTOUT ALARM P4[5]/A5 P0[15]/TXD1/ P0[16]/RXD1/ SCK0/SCK SSEL0/SSEL Row J RESET RTCX1 P0[13]/USB_UP_LED2/ MOSI1/AD0[7] P0[19]/DSR1/ MCICLK/SDA1 P0[18]/DCD1/ MOSI0/MOSI Row K VBAT P1[31]/USB_OVRCR2/ SCK1/AD0[5] P0[29]/USB_D+1 P1[20]/USB_TX_DP1/ PWM1[2]/SCK0 P4[3]/A3 P4[6]/A6 P4[26]/BLS0... -
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NXP Semiconductors Table 119. LPC2458 pin allocation table Pin Symbol Pin Symbol P2[19]/CLKOUT1 P1[21]/USB_TX_DM1/ PWM1[3]/SSEL0 P1[29]/USB_SDA1/ DD(DCDC)(3V3) PCAP1[1]/MAT0[1] P4[17]/A17 P2[12]/EINT2/ MCIDAT2/I2STX_WS Row P P2[24]/CKEOUT0 P2[25]/CKEOUT1 P1[19]/USB_TX_E1/ P2[20]/DYCS0 USB_PPWR1/CAP1[1] P2[16]/CAS P1[28]/USB_SCL1/ PCAP1[0]/MAT0[0] P4[4]/A4 P4[18]/A18 Table 120. Pin description Symbol Ball Type... -
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NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0] P0[7]/ I2STX_CLK/ SCK1/MAT2[1] P0[8]/ I2STX_WS/ MISO1/MAT2[2] P0[9]/ I2STX_SDA/ MOSI1/MAT2[3] P0[10]/TXD2/ SDA2/MAT3[0] P0[11]/RXD2/ SCL2/MAT3[1] P0[12]/ USB_PPWR2/ MISO1/AD0[6] P0[13]/ USB_UP_LED2/ MOSI1/AD0[7] UM10237_2 User manual Chapter 8: LPC24XX Pin configuration Description P0[6] —... -
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NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type P0[14]/ USB_HSTEN2/ USB_CONNECT2/ SSEL1 P0[15]/TXD1/ SCK0/SCK P0[16]/RXD1/ SSEL0/SSEL P0[17]/CTS1/ MISO0/MISO P0[18]/DCD1/ MOSI0/MOSI P0[19]/DSR1/ MCICLK/SDA1 P0[20]/DTR1/ MCICMD/SCL1 P0[21]/RI1/ MCIPWR/RD1 P0[22]/RTS1/ MCIDAT0/TD1 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration Description P0[14] — General purpose digital input/output pin. -
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NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0] P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1] P0[25]/AD0[2]/ I2SRX_SDA/ TXD3 [2][3] P0[26]/AD0[3]/ AOUT/RXD3 P0[27]/SDA0 P0[28]/SCL0 P0[29]/USB_D+1 P0[30]/USB_D−1 P0[31]/USB_D+2 P1[0] to P1[31] P1[0]/ ENET_TXD0 P1[1]/ ENET_TXD1 P1[2]/ ENET_TXD2/ MCICLK/ PWM0[1] UM10237_2 User manual... -
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NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type P1[3]/ ENET_TXD3/ MCICMD/ PWM0[2] P1[4]/ ENET_TX_EN P1[5]/ ENET_TX_ER/ MCIPWR/ PWM0[3] P1[6]/ ENET_TX_CLK/ MCIDAT0/ PWM0[4] P1[7]/ ENET_COL/ MCIDAT1/ PWM0[5] P1[8]/ ENET_CRS_DV/ ENET_CRS P1[9]/ ENET_RXD0 P1[10]/ ENET_RXD1 P1[11]/ ENET_RXD2/ MCIDAT2/ PWM0[6] P1[12]/... -
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NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type P1[16]/ ENET_MDC P1[17]/ ENET_MDIO P1[18]/ USB_UP_LED1/ PWM1[1]/ CAP1[0] P1[19]/ USB_TX_E1/ USB_PPWR1/ CAP1[1] P1[20]/ USB_TX_DP1/ PWM1[2]/SCK0 P1[21]/ USB_TX_DM1/ PWM1[3]/SSEL0 P1[22]/ USB_RCV1/ USB_PWRD1/ MAT1[0] P1[23]/ USB_RX_DP1/ PWM1[4]/MISO0 P1[24]/ USB_RX_DM1/ PWM1[5]/MOSI0 P1[25]/ USB_LS1/... -
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NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type P1[26]/ USB_SSPND1/ PWM1[6]/ CAP0[0] P1[27]/ USB_INT1/ USB_OVRCR1/ CAP0[1] P1[28]/ USB_SCL1/ PCAP1[0]/ MAT0[0] P1[29]/ USB_SDA1/ PCAP1[1]/ MAT0[1] P1[30]/ USB_PWRD2/ /AD0[4] P1[31]/ USB_OVRCR2/ SCK1/AD0[5] P2[0] to P2[31] P2[0]/PWM1[1]/ TXD1/ TRACECLK P2[1]/PWM1[2]/ RXD1/... -
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NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type P2[3]/PWM1[4]/ DCD1/ PIPESTAT2 P2[4]/PWM1[5]/ DSR1/ TRACESYNC P2[5]/PWM1[6]/ DTR1/ TRACEPKT0 P2[6]/PCAP1[0]/RI1/ TRACEPKT1 P2[7]/RD2/ RTS1/ TRACEPKT2 P2[8]/TD2/ TXD2/ TRACEPKT3 P2[9]/ USB_CONNECT1/ RXD2/ EXTIN0 P2[10]/EINT0 P2[11]/EINT1/ MCIDAT1/ I2STX_CLK UM10237_2 User manual Chapter 8: LPC24XX Pin configuration Description P2[3] —... -
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NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type P2[12]/EINT2/ MCIDAT2/ I2STX_WS P2[13]/EINT3/ MCIDAT3/ I2STX_SDA P2[16]/CAS P2[17]/RAS P2[18]/ CLKOUT0 P2[19]/ CLKOUT1 P2[20]/DYCS0 P2[21]/DYCS1 P2[24]/ CKEOUT0 P2[25]/ CKEOUT1 P2[28]/ DQMOUT0 P2[29]/ DQMOUT1 P3[0] to P3[31] P3[0]/D0 P3[1]/D1 P3[2]/D2 P3[3]/D3 UM10237_2... -
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NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type P3[4]/D4 P3[5]/D5 P3[6]/D6 P3[7]/D7 P3[8]/D8 P3[9]/D9 P3[10]/D10 P3[11]/D11 P3[12]/D12 P3[13]/D13 P3[14]/D14 P3[15]/D15 P3[23]/CAP0[0]/ PCAP1[0] P3[24]/CAP0[1]/ PWM1[1] P3[25]/MAT0[0]/ PWM1[2] P3[26]/MAT0[1]/ PWM1[3] P4[0] to P4[31] UM10237_2 User manual Chapter 8: LPC24XX Pin configuration Description P3[4] —... -
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NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type P4[0]/A0 P4[1]/A1 P4[2]/A2 P4[3]/A3 P4[4]/A4 P4[5]/A5 P4[6]/A6 P4[7]/A7 P4[8]/A8 P4[9]/A9 P4[10]/A10 P4[11]/A11 P4[12]/A12 P4[13]/A13 P4[14]/A14 P4[15]/A15 P4[16]/A16 P4[17]/A17 P4[18]/A18 P4[19]/A19 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration Description P4[0] — General purpose digital input/output pin. -
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NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type P4[24]/OE P4[25]/WE P4[26]/BLS0 P4[27]/BLS1 P4[28]/MAT2[0]/ TXD3 P4[29]/MAT2[1]/ RXD3 P4[30]/CS0 P4[31]/CS1 ALARM USB_D−2 DBGEN TRST RTCK RSTOUT RESET XTAL1 XTAL2 RTCX1 RTCX2 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration Description P4[24] —... -
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NXP Semiconductors Table 120. Pin description …continued Symbol Ball Type H4, P4, SSIO L9, L13, G13, D13, C11, H3, L8, SSCORE [10] E2, L4, DD(3V3) K8, L11, J14, E12, E10, [11] n.c. H1, L12, [12] G1, N9, DD(DCDC)(3V3) [13] [14]... -
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NXP Semiconductors 4. LPC2460/68 pinning information Table 121. LPC2420/60/68 pin allocation table CAN and Ethernet pins for LPC2460/68 only. Pin Symbol Pin Symbol Row A P3[27]/D27/ CAP1[0]/PWM1[4] P1[4]/ENET_TX_EN P1[9]/ENET_RXD0 P1[17]/ENET_MDIO P1[3]/ENET_TXD3/ MCICMD/PWM0[2] P3[20]/D20/ P1[11]/ENET_RXD2/ PWM0[5]/DSR1 MCIDAT2/PWM0[6] P1[5]/ENET_TX_ER/ MCIPWR/PWM0[3] Row B... -
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NXP Semiconductors Table 121. LPC2420/60/68 pin allocation table CAN and Ethernet pins for LPC2460/68 only. Pin Symbol Pin Symbol P2[1]/PWM1[2]/RXD1/ PIPESTAT0 Row F P0[25]/AD0[2]/ P3[4]/D4 I2SRX_SDA/TXD3 P4[11]/A11 P3[17]/D17/ PWM0[2]/RXD1 Row G P3[5]/D5 P0[24]/AD0[1]/ I2SRX_WS/CAP3[1] P4[27]/BLS1 Row H P0[23]/AD0[0]/ P3[14]/D14 I2SRX_CLK/CAP3[0]... -
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NXP Semiconductors Table 121. LPC2420/60/68 pin allocation table CAN and Ethernet pins for LPC2460/68 only. Pin Symbol Pin Symbol P1[23]/USB_RX_DP1/ PWM1[4]/MISO0 P2[15]/CS3/ P4[17]/A17 CAP2[1]/SCL1 DD(3V3) Row R P0[12]/USB_PPWR2/ P0[13]/USB_UP_LED2/ MISO1/AD0[6] MOSI1/AD0[7] P3[24]/D24/ P0[30]/USB_D−1 CAP0[1]/PWM1[1] P1[26]/USB_SSPND1/ SSIO PWM1[6]/CAP0[0] P2[17]/RAS P0[11]/RXD2/SCL2/ MAT3[1]... -
Page 139: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P0[0] to P0[31] P0[0]/RD1/ TXD3/SDA1 P0[1]/TD1/RXD3/ SCL1 P0[2]/TXD0 P0[3]/RXD0 P0[4]/ I2SRX_CLK/ RD2/CAP2[0] P0[5]/ I2SRX_WS/ TD2/CAP2[1] P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0] P0[7]/ I2STX_CLK/ SCK1/MAT2[1] P0[8]/ I2STX_WS/ MISO1/MAT2[2] UM10237_2 User manual Chapter 8: LPC24XX Pin configuration... -
Page 140: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P0[9]/ I2STX_SDA/ MOSI1/MAT2[3] P0[10]/TXD2/ SDA2/MAT3[0] P0[11]/RXD2/ SCL2/MAT3[1] P0[12]/ USB_PPWR2/ MISO1/AD0[6] P0[13]/ USB_UP_LED2/ MOSI1/AD0[7] P0[14]/ USB_HSTEN2/ USB_CONNECT2/ SSEL1 P0[15]/TXD1/ SCK0/SCK P0[16]/RXD1/ SSEL0/SSEL P0[17]/CTS1/ MISO0/MISO UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued... -
Page 141: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P0[18]/DCD1/ MOSI0/MOSI P0[19]/DSR1/ MCICLK/SDA1 P0[20]/DTR1/ MCICMD/SCL1 P0[21]/RI1/ MCIPWR/RD1 P0[22]/RTS1/ MCIDAT0/TD1 P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0] P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1] P0[25]/AD0[2]/ I2SRX_SDA/ TXD3 [2][3] [2][3] P0[26]/AD0[3]/ AOUT/RXD3 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued... -
Page 142: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P0[27]/SDA0 P0[28]/SCL0 P0[29]/USB_D+1 P0[30]/USB_D−1 P0[31]/USB_D+2 P1[0] to P1[31] P1[0]/ ENET_TXD0 P1[1]/ ENET_TXD1 P1[2]/ ENET_TXD2/ MCICLK/ PWM0[1] P1[3]/ ENET_TXD3/ MCICMD/ PWM0[2] P1[4]/ ENET_TX_EN P1[5]/ ENET_TX_ER/ MCIPWR/ PWM0[3] P1[6]/ ENET_TX_CLK/ MCIDAT0/ PWM0[4] UM10237_2... -
Page 143: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P1[7]/ ENET_COL/ MCIDAT1/ PWM0[5] P1[8]/ ENET_CRS_DV/ ENET_CRS P1[9]/ ENET_RXD0 P1[10]/ ENET_RXD1 P1[11]/ ENET_RXD2/ MCIDAT2/ PWM0[6] P1[12]/ ENET_RXD3/ MCIDAT3/ PCAP0[0] P1[13]/ ENET_RX_DV P1[14]/ ENET_RX_ER P1[15]/ ENET_REF_CLK/ ENET_RX_CLK P1[16]/ ENET_MDC P1[17]/ ENET_MDIO P1[18]/... -
Page 144: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P1[19]/ USB_TX_E1/ USB_PPWR1/ CAP1[1] P1[20]/ USB_TX_DP1/ PWM1[2]/SCK0 P1[21]/ USB_TX_DM1/ PWM1[3]/SSEL0 P1[22]/ USB_RCV1/ USB_PWRD1/ MAT1[0] P1[23]/ USB_RX_DP1/ PWM1[4]/MISO0 P1[24]/ USB_RX_DM1/ PWM1[5]/MOSI0 P1[25]/ USB_LS1/ USB_HSTEN1/ MAT1[1] P1[26]/ USB_SSPND1/ PWM1[6]/ CAP0[0] P1[27]/ USB_INT1/ USB_OVRCR1/... -
Page 145: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P1[29]/ USB_SDA1/ PCAP1[1]/ MAT0[1] P1[30]/ USB_PWRD2/ /AD0[4] P1[31]/ USB_OVRCR2/ SCK1/AD0[5] P2[0] to P2[31] P2[0]/PWM1[1]/ TXD1/ TRACECLK P2[1]/PWM1[2]/ RXD1/ PIPESTAT0 P2[2]/PWM1[3]/ CTS1/ PIPESTAT1 P2[3]/PWM1[4]/ DCD1/ PIPESTAT2 P2[4]/PWM1[5]/ DSR1/ TRACESYNC P2[5]/PWM1[6]/ DTR1/ TRACEPKT0... -
Page 146: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P2[6]/PCAP1[0]/ RI1/TRACEPKT1 P2[7]/RD2/ RTS1/ TRACEPKT2 P2[8]/TD2/ TXD2/ TRACEPKT3 P2[9]/ USB_CONNECT1/ RXD2/ EXTIN0 P2[10]/EINT0 P2[11]/EINT1/ MCIDAT1/ I2STX_CLK P2[12]/EINT2/ MCIDAT2/ I2STX_WS P2[13]/EINT3/ MCIDAT3/ I2STX_SDA P2[14]/CS2/ CAP2[0]/SDA1 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued... -
Page 147: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P2[15]/CS3/ CAP2[1]/SCL1 P2[16]/CAS P2[17]/RAS P2[18]/ CLKOUT0 P2[19]/ CLKOUT1 P2[20]/DYCS0 P2[21]/DYCS1 P2[22]/DYCS2/ CAP3[0]/SCK0 P2[23]/DYCS3/ CAP3[1]/SSEL0 P2[24]/ CKEOUT0 P2[25]/ CKEOUT1 P2[26]/ CKEOUT2/ MAT3[0]/MISO0 P2[27]/ CKEOUT3/ MAT3[1]/MOSI0 P2[28]/ DQMOUT0 P2[29]/ DQMOUT1 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued... -
Page 148: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P2[30]/ DQMOUT2/ MAT3[2]/SDA2 P2[31]/ DQMOUT3/ MAT3[3]/SCL2 P3[0] to P3[31] P3[0]/D0 P3[1]/D1 P3[2]/D2 P3[3]/D3 P3[4]/D4 P3[5]/D5 P3[6]/D6 P3[7]/D7 P3[8]/D8 P3[9]/D9 P3[10]/D10 P3[11]/D11 P3[12]/D12 P3[13]/D13 P3[14]/D14 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued... -
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NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P3[15]/D15 P3[16]/D16/ PWM0[1]/TXD1 P3[17]/D17/ PWM0[2]/RXD1 P3[18]/D18/ PWM0[3]/CTS1 P3[19]/D19/ PWM0[4]/DCD1 P3[20]/D20/ PWM0[5]/DSR1 P3[21]/D21/ PWM0[6]/DTR1 P3[22]/D22/ PCAP0[0]/RI1 P3[23]/D23/ CAP0[0]/ PCAP1[0] UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued Type Description P3[15] — General purpose digital input/output pin. -
Page 150: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P3[24]/D24/ CAP0[1]/ PWM1[1] P3[25]/D25/ MAT0[0]/ PWM1[2] P3[26]/D26/ MAT0[1]/ PWM1[3] P3[27]/D27/ CAP1[0]/ PWM1[4] P3[28]/D28/ CAP1[1]/ PWM1[5] P3[29]/D29/ MAT1[0]/ PWM1[6] P3[30]/D30/ MAT1[1]/ RTS1 P3[31]/D31/ MAT1[2] P4[0] to P4[31] P4[0]/A0 P4[1]/A1 P4[2]/A2 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued... -
Page 151: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P4[3]/A3 P4[4]/A4 P4[5]/A5 P4[6]/A6 P4[7]/A7 P4[8]/A8 P4[9]/A9 P4[10]/A10 P4[11]/A11 P4[12]/A12 P4[13]/A13 P4[14]/A14 P4[15]/A15 P4[16]/A16 P4[17]/A17 P4[18]/A18 P4[19]/A19 P4[20]/A20/ SDA2/SCK1 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued Type Description P4[3] — General purpose digital input/output pin. -
Page 152: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball P4[21]/A21/ SCL2/SSEL1 P4[22]/A22/ TXD2/MISO1 P4[23]/A23/ RXD2/MOSI1 P4[24]/OE P4[25]/WE P4[26]/BLS0 P4[27]/BLS1 P4[28]/BLS2/ MAT2[0]/TXD3 P4[29]/BLS3/ MAT2[1]/RXD3 P4[30]/CS0 P4[31]/CS1 ALARM USB_D−2 DBGEN TRST UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued Type Description P4[21] —... -
Page 153: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 122. LPC2420/60/68 pin description Symbol Ball RTCK RSTOUT RESET XTAL1 XTAL2 RTCX1 RTCX2 33, 63, L3, T5, SSIO 77, 93, 114, P12, 133, N16, 148, H14, 169, E15, 189, A12, B6, A2 32, 84, K4, P10, SSCORE... -
Page 154: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled. 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. -
Page 155: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 123. LPC2470/78 pin allocation table Pin Symbol Pin Symbol P0[7]/I2STX_CLK/ P0[9]/I2STX_SDA/ LCDVD[9]/SCK1/ LCDVD[17]/MOSI1/ MAT2[1] MAT2[3] DD(3V3) Row D TRST P3[28]/D28/ CAP1[1]/PWM1[5] P3[11]/D11 P0[3]/RXD0 P1[2]/ENET_TXD2/ P1[16]/ENET_MDC MCICLK/PWM0[1] P0[6]/I2SRX_SDA/ P1[7]/ENET_COL/ LCDVD[8]/SSEL1/ MCIDAT1/PWM0[5] MAT2[0] P2[4]/PWM1[5]/ DSR1/TRACESYNC/ LCDENAB/LCDM Row E P0[26]/AD0[3]/... -
Page 156: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 123. LPC2470/78 pin allocation table Pin Symbol Pin Symbol P4[22]/A22/ P0[18]/DCD1/ TXD2/MISO1 MOSI0/MOSI Row L P3[7]/D7 RTCX2 P4[26]/BLS0 Row M P3[15]/D15 RESET P4[6]/A6 P4[21]/A21/ SCL2/SSEL1 Row N ALARM P2[31]/DQMOUT3/ MAT3[3]/SCL2 P2[12]/EINT2/ P2[10]/EINT0 LCDVD[4]/LCDVD[8]/ LCDVD[3]/LCDVD[18]/ MCIDAT2/I2STX_WS Row P... -
Page 157: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 123. LPC2470/78 pin allocation table Pin Symbol Pin Symbol P1[24]/USB_RX_DM1/ P1[25]/USB_LS1/ LCDVD[10]/LCDVD[14]/ LCDVD[11]/LCDVD[15]/ PWM1[5]/MOSI0 USB_HSTEN1/MAT1[1] P1[28]/USB_SCL1/ P0[1]/TD1/RXD3/SCL1 LCDVD[14]/LCDVD[22]/ PCAP1[0]/MAT0[0] P2[11]/EINT1/ LCDCLKIN/ MCIDAT1/I2STX_CLK Row U USB_D−2 P3[25]/D25/ MAT0[0]/PWM1[2] P2[23]/DYCS3/ P1[19]/USB_TX_E1/ CAP3[1]/SSEL0 USB_PPWR1/CAP1[1] P4[0]/A0 P4[1]/A1 P1[29]/USB_SDA1/ DD(3V3) LCDVD[15]/LCDVD[23]/ PCAP1[1]/MAT0[1] P4[16]/A16 Table 124. -
Page 158: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P0[4]/I2SRX_CLK/ LCDVD[0]/RD2/ CAP2[0] P0[5]/I2SRX_WS/ LCDVD[1]/TD2/ CAP2[1] P0[6]/I2SRX_SDA/ LCDVD[8]/ SSEL1/MAT2[0] P0[7]/I2STX_CLK/ LCDVD[9]/SCK1/ MAT2[1] P0[8]/I2STX_WS/ LCDVD[16]/ MISO1/MAT2[2] P0[9]/I2STX_SDA/ LCDVD[17]/ MOSI1/MAT2[3] UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued Type Description P0[4] — General purpose digital input/output pin. -
Page 159: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P0[10]/TXD2/ SDA2/MAT3[0] P0[11]/RXD2/ SCL2/MAT3[1] P0[12]/ USB_PPWR2/ MISO1/AD0[6] P0[13]/ USB_UP_LED2/ MOSI1/AD0[7] P0[14]/ USB_HSTEN2/ USB_CONNECT2/ SSEL1 P0[15]/TXD1/ SCK0/SCK P0[16]/RXD1/ SSEL0/SSEL P0[17]/CTS1/ MISO0/MISO P0[18]/DCD1/ MOSI0/MOSI UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued... -
Page 160: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P0[19]/DSR1/ MCICLK/SDA1 P0[20]/DTR1/ MCICMD/SCL1 P0[21]/RI1/ MCIPWR/RD1 P0[22]/RTS1/ MCIDAT0/TD1 P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0] P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1] P0[25]/AD0[2]/ I2SRX_SDA/ TXD3 [2][3] [2][3] P0[26]/AD0[3]/ AOUT/RXD3 P0[27]/SDA0 P0[28]/SCL0 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued... -
Page 161: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P0[29]/USB_D+1 P0[30]/USB_D−1 P0[31]/USB_D+2 P1[0] to P1[31] P1[0]/ ENET_TXD0 P1[1]/ ENET_TXD1 P1[2]/ ENET_TXD2/ MCICLK/ PWM0[1] P1[3]/ ENET_TXD3/ MCICMD/ PWM0[2] P1[4]/ ENET_TX_EN P1[5]/ ENET_TX_ER/ MCIPWR/ PWM0[3] P1[6]/ ENET_TX_CLK/ MCIDAT0/ PWM0[4] P1[7]/ ENET_COL/ MCIDAT1/... -
Page 162: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P1[11]/ ENET_RXD2/ MCIDAT2/ PWM0[6] P1[12]/ ENET_RXD3/ MCIDAT3/ PCAP0[0] P1[13]/ ENET_RX_DV P1[14]/ ENET_RX_ER P1[15]/ ENET_REF_CLK/ ENET_RX_CLK P1[16]/ ENET_MDC P1[17]/ ENET_MDIO P1[18]/ USB_UP_LED1/ PWM1[1]/CAP1[0] P1[19]/ USB_TX_E1/ USB_PPWR1/ CAP1[1] P1[20]/ USB_TX_DP1/ LCDVD[6]/ LCDVD[10]/ PWM1[2]/SCK0... -
Page 163: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P1[22]/USB_RCV1/ LCDVD[8]/ LCDVD[12]/ USB_PWRD1/ MAT1[0] P1[23]/ USB_RX_DP1/ LCDVD[9]/ LCDVD[13]/ PWM1[4]/MISO0 P1[24]/ USB_RX_DM1/ LCDVD[10]/ LCDVD[14]/ PWM1[5]/MOSI0 P1[25]/USB_LS1/ LCDVD[11]/ LCDVD[15]/ USB_HSTEN1/ MAT1[1] P1[26]/ USB_SSPND1/ LCDVD[12]/ LCDVD[20]/ PWM1[6]/CAP0[0] P1[27]/USB_INT1/ LCDVD[13]/ LCDVD[21]/ USB_OVRCR1/ CAP0[1] P1[28]/USB_SCL1/... -
Page 164: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P1[29]/USB_SDA1/ LCDVD[15]/ LCDVD[23]/ PCAP1[1]/MAT0[1] P1[30]/ USB_PWRD2/ /AD0[4] P1[31]/ USB_OVRCR2/ SCK1/AD0[5] P2[0] to P2[31] UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued Type Description P1[29] — General purpose digital input/output pin. -
Page 165: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P2[0]/PWM1[1]/ TXD1/TRACECLK/ LCDPWR P2[1]/PWM1[2]/ RXD1/PIPESTAT0/ LCDLE P2[2]/PWM1[3]/ CTS1/PIPESTAT1/ LCDDCLK P2[3]/PWM1[4]/ DCD1/PIPESTAT2/ LCDFP P2[4]/PWM1[5]/ DSR1/ TRACESYNC/ LCDENAB/LCDM P2[5]/PWM1[6]/ DTR1/ TRACEPKT0/ LCDLP P2[6]/PCAP1[0]/ RI1/ TRACEPKT1/ LCDVD[0]/ LCDVD[4] P2[7]/RD2/ RTS1/ TRACEPKT2/ LCDVD[1]/ LCDVD[5] UM10237_2... -
Page 166: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P2[8]/TD2/TXD2/ TRACEPKT3/ LCDVD[2]/ LCDVD[6] P2[9]/ USB_CONNECT1/ RXD2/EXTIN0/ LCDVD[3]/ LCDVD[7] P2[10]/EINT0 P2[11]/EINT1/ LCDCLKIN/ MCIDAT1/ I2STX_CLK P2[12]/EINT2/ LCDVD[4]/ LCDVD[3]/ LCDVD[8]/ LCDVD[18]/ MCIDAT2/ I2STX_WS P2[13]/EINT3/ LCDVD[5]/ LCDVD[9]/ LCDVD[19]/ MCIDAT3/ I2STX_SDA P2[14]/CS2/ CAP2[0]/SDA1 P2[15]/CS3/ CAP2[1]/SCL1... -
Page 167: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P2[16]/CAS P2[17]/RAS P2[18]/ CLKOUT0 P2[19]/ CLKOUT1 P2[20]/DYCS0 P2[21]/DYCS1 P2[22]/DYCS2/ CAP3[0]/SCK0 P2[23]/DYCS3/ CAP3[1]/SSEL0 P2[24]/ CKEOUT0 P2[25]/ CKEOUT1 P2[26]/ CKEOUT2/ MAT3[0]/MISO0 P2[27]/ CKEOUT3/ MAT3[1]/MOSI0 P2[28]/ DQMOUT0 P2[29]/ DQMOUT1 P2[30]/ DQMOUT2/ MAT3[2]/SDA2 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued... -
Page 168: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P2[31]/ DQMOUT3/ MAT3[3]/SCL2 P3[0] to P3[31] P3[0]/D0 P3[1]/D1 P3[2]/D2 P3[3]/D3 P3[4]/D4 P3[5]/D5 P3[6]/D6 P3[7]/D7 P3[8]/D8 P3[9]/D9 P3[10]/D10 P3[11]/D11 P3[12]/D12 P3[13]/D13 P3[14]/D14 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued Type Description P2[31] —... -
Page 169: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P3[15]/D15 P3[16]/D16/ PWM0[1]/TXD1 P3[17]/D17/ PWM0[2]/RXD1 P3[18]/D18/ PWM0[3]/CTS1 P3[19]/D19/ PWM0[4]/DCD1 P3[20]/D20/ PWM0[5]/DSR1 P3[21]/D21/ PWM0[6]/DTR1 P3[22]/D22/ PCAP0[0]/RI1 P3[23]/D23/ CAP0[0]/ PCAP1[0] UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued Type Description P3[15] — General purpose digital input/output pin. -
Page 170: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P3[24]/D24/ CAP0[1]/ PWM1[1] P3[25]/D25/ MAT0[0]/ PWM1[2] P3[26]/D26/ MAT0[1]/ PWM1[3] P3[27]/D27/ CAP1[0]/ PWM1[4] P3[28]/D28/ CAP1[1]/ PWM1[5] P3[29]/D29/ MAT1[0]/ PWM1[6] P3[30]/D30/ MAT1[1]/ RTS1 P3[31]/D31/ MAT1[2] P4[0] to P4[31] P4[0]/A0 P4[1]/A1 P4[2]/A2 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued... -
Page 171: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P4[3]/A3 P4[4]/A4 P4[5]/A5 P4[6]/A6 P4[7]/A7 P4[8]/A8 P4[9]/A9 P4[10]/A10 P4[11]/A11 P4[12]/A12 P4[13]/A13 P4[14]/A14 P4[15]/A15 P4[16]/A16 P4[17]/A17 P4[18]/A18 P4[19]/A19 P4[20]/A20/ SDA2/SCK1 UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued Type Description P4[3] — General purpose digital input/output pin. -
Page 172: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball P4[21]/A21/ SCL2/SSEL1 P4[22]/A22/ TXD2/MISO1 P4[23]/A23/ RXD2/MOSI1 P4[24]/OE P4[25]/WE P4[26]/BLS0 P4[27]/BLS1 P4[28]/BLS2/ MAT2[0]/LCDVD[6]/ LCDVD[10]/ LCDVD[2]/ TXD3 P4[29]/BLS3/ MAT2[1] LCDVD[7]/ LCDVD[11]/ LCDVD[3]/RXD3 P4[30]/CS0 P4[31]/CS1 ALARM USB_D−2 DBGEN UM10237_2 User manual Chapter 8: LPC24XX Pin configuration …continued... -
Page 173: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 124. LPC2470/78 pin description Symbol Ball TRST RTCK RSTOUT RESET XTAL1 XTAL2 RTCX1 RTCX2 33, 63, L3, T5, SSIO 77, 93, R9, P12, 114, N16, 133, H14, 148, E15, 169, A12, B6, 189, 32, 84, K4, P10,... -
Page 174: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled. -
Page 175: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors the address mirror bit is set in the EMCControl register during POR, see Therefore, the user code residing in the external boot memory must be linked to execute from address location 0x8000 0000 (EMC bank 0 address). Remark: The external boot option is supported only for flashless devices LPC2460 and LPC2470. -
Page 176: Nxp B.v. 2008. All Rights Reserved
UM10237 Chapter 9: LPC24XX Pin connect Rev. 02 — 19 December 2008 1. How to read this chapter The LPC2400 parts have different pin configurations depending on the number of pins. Table 9–126 parts: • Only LPC2470 and LPC2478 have an LCD controller. •... -
Page 177: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors 3. Pin function select register values The PINSEL registers control the functions of device pins as shown below. Pairs of bits in these registers correspond to specific device pins. Table 127. Pin function select register bits PINSEL0 to... -
Page 178: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors Table 129. Summary of pin connect block registers Name PINSEL6 PINSEL7 PINSEL8 PINSEL9 PINSEL10 PINSEL 11 PINMODE0 PINMODE1 PINMODE2 PINMODE3 PINMODE4 PINMODE5 PINMODE6 PINMODE7 PINMODE8 PINMODE9 Reset Value reflects the data stored in used bits only. It does not include reserved bits content. -
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NXP Semiconductors Table 130. Pin function select register 0 (PINSEL0 - address 0xE002 C000) bit description PINSEL0 Pin name P0[3] P0[4] 11:10 P0[5] 13:12 P0[6] 15:14 P0[7] 17:16 P0[8] 19:18 P0[9] 21:20 P0[10] 23:22 P0[11] 25:24 P0[12] 27:26 P0[13] 29:28... -
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NXP Semiconductors Table 131. Pin function select register 1 (PINSEL1 - address 0xE002 C004) bit description PINSEL1 Pin name 27:26 P0[29] 29:28 P0[30] 31:30 P0[31] Pins P027] and P0[28] are open-drain for I 5.3 Pin Function Select register 2 (PINSEL2 - 0xE002 C008) -
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NXP Semiconductors Table 133. Pin function select register 3 (PINSEL3 - address 0xE002 C00C) bit description PINSEL3 Pin name P1[16] P1[17] P1[18] P1[19] P1[20] 11:10 P1[21] 13:12 P1[22] 15:14 P1[23] 17:16 P1[24] 19:18 P1[25] 21:20 P1[26] 23:22 P1[27] 25:24 P1[28]... -
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NXP Semiconductors Table 134. LPC2458 pin function select register 4 (PINSEL4 - address 0xE002 C010) bit PINSEL4 Pin name P2[0] P2[1] P2[2] P2[3] P2[4] 11:10 P2[5] 13:12 P2[6] 15:14 P2[7] 17:16 P2[8] 19:18 P2[9] 21:20 P2[10] 23:22 P2[11] 25:24 P2[12]... -
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NXP Semiconductors Table 135. LPC2420/60/68/70/78 pin function select register 4 (PINSEL4 - address PINSEL4 Pin name 11:10 P2[5] 13:12 P2[6] 15:14 P2[7] 17:16 P2[8] 19:18 P2[9] 21:20 P2[10] 23:22 P2[11] 25:24 P2[12] 27:26 P2[13] 29:28 P2[14] 31:30 P2[15] Section 9–5.11 “Pin Function Select Register 10 (PINSEL10 - 0xE002 ETM functionality. -
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NXP Semiconductors Table 136. LPC2458 pin function select register 5 (PINSEL5 - address 0xE002 C014) bit PINSEL5 Pin name P2[16] P2[17] P2[18] P2[19] P2[20] 11:10 P2[21] 13:12 P2[22] 15:14 P2[23] 17:16 P2[24] 19:18 P2[25] 21:20 P2[26] 23:22 P2[27] 25:24 P2[28]... -
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NXP Semiconductors 5.7 Pin Function Select Register 6 (PINSEL6 - 0xE002 C018) The PINSEL6 register controls the functions of the pins as per the settings listed in Table 9–138. The direction control bit in the FIO3DIR register is effective only when the GPIO function is selected for a pin. -
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NXP Semiconductors Table 139. LPC2458 pin function select register 7 (PINSEL7 - address 0xE002 C01C) bit PINSEL7 Pin name P3[20] 11:10 P3[21] 13:12 P3[22] 15:14 P3[23] 17:16 P3[24] 19:18 P3[25] 21:20 P3[26] 23:22 P3[27] 25:24 P3[28] 27:26 P3[29] 29:28 P3[30]... -
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NXP Semiconductors Table 141. Pin function select register 8 (PINSEL8 - address 0xE002 C020) bit description PINSEL8 Pin name P4[0] P4[1] P4[2] P4[3] P4[4] 11:10 P4[5] 13:12 P4[6] 15:14 P4[7] 17:16 P4[8] 19:18 P4[9] 21:20 P4[10] 23:22 P4[11] 25:24 P4[12]... -
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NXP Semiconductors Table 142. LPC2458 pin function select register 9 (PINSEL9 - address 0xE002 C024) bit PINSEL9 Pin name 21:20 P4[26] 23:22 P4[27] 25:24 P4[28] 27:26 P4[29] 29:28 P4[30] 31:30 P4[31] Table 143. LPC2420/60/68/70/78 pin function select register 9 (PINSEL9 - address... -
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NXP Semiconductors Table 144. Pin function select register 10 (PINSEL10 - address 0xE002 C028) bit description Symbol GPIO/TRACE 31:4 5.12 Pin Function Select Register 11 (PINSEL11 - 0xE002 C02C) This register is used to select the LCD function and the LCD mode on the LPC247x. -
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NXP Semiconductors 5.14 Pin Mode select register 1 (PINMODE1 - 0xE002 C044) This register controls pull-up/pull-down resistor configuration for PORT0 pins 16 to 26. For details see Table 147. Pin Mode select register 1 (PINMODE1 - address 0xE002 C044) bit description... -
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NXP Semiconductors Table 150. Pin Mode select register 4 (PINMODE4 - address 0xE002 C050) bit description PINMODE4 31:30 5.18 Pin Mode select register 5 (PINMODE5 - 0xE002 C054) This register controls pull-up/pull-down resistor configuration for PORT2 pins 16 to 31. For details see Table 151. -
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NXP Semiconductors Table 154. Pin Mode select register 8 (PINMODE8 - address 0xE002 C060) bit description PINMODE8 Symbol 31:30 5.22 Pin Mode select register 9 (PINMODE9 - 0xE002 C064) This register controls pull-up/pull-down resistor configuration for PORT4 pins 16 to 31. For details see Table 155. -
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UM10237 Chapter 10: LPC24XX General Purpose Input/Output (GPIO) Rev. 02 — 19 December 2008 1. How to read this chapter The number of GPIO pins on each port is different for LPC2458 and LPC2460/68/70/78 parts. The available pins are listed in unavailable pins are reserved in all GPIO related registers. -
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NXP Semiconductors – Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. – All GPIO registers are byte and half-word addressable. – Entire port value can be written in one instruction. • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. -
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NXP Semiconductors 5. Pin description Table 157. GPIO pin description Pin Name P0[31:0] P1[31:0] P2[31:0] P3[31:0] P4[31:0] 6. Register description LPC2400 has up to five 32-bit General Purpose I/O ports. PORT0 and PORT1 are controlled via two groups of registers as shown in from them, LPC2400 can have three additional 32-bit ports, PORT2, PORT3 and PORT4. -
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NXP Semiconductors Table 158. Summary of GPIO registers (legacy APB accessible registers) Generic Description Name IOPIN GPIO Port Pin value register. The current state of the GPIO configured port pins can always be read from this register, regardless of pin direction. By writing to this register port’s pins will be set to the desired level instantaneously. -
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NXP Semiconductors Table 159. Summary of GPIO registers (local bus accessible registers - enhanced GPIO features) Generic Description Name FIODIR Fast GPIO Port Direction control register. This register individually controls the direction of each port pin. FIOMASK Fast Mask register for port. Writes, sets, clears, and reads to... -
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NXP Semiconductors Table 160. GPIO interrupt register map Generic Description Name IntEnR GPIO Interrupt Enable for Rising edge. IntEnF GPIO Interrupt Enable for Falling edge. IntStatR GPIO Interrupt Status for Rising edge. IntStatF GPIO Interrupt Status for Falling edge. IntClr GPIO Interrupt Clear. -
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NXP Semiconductors Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 10–163, too. Next to providing the same functions as the FIODIR register, these additional registers allow easier and faster access to the physical port pins. -
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NXP Semiconductors Legacy registers are the IO0SET and IO1SET while the enhanced GPIOs are supported via the FIO0SET, FIO1SET, FIO2SET, FIO3SET, and FIO4SET registers. Access to a port pin via the FIOSET register is conditioned by the corresponding bit of the FIOMASK... -
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NXP Semiconductors Table 166. Fast GPIO port output Set byte and half-word accessible register description Generic Register name FIOxSET3 FIOxSETL FIOxSETU 6.3 GPIO port output Clear register IOCLR and FIOCLR (IO[0/1]CLR - 0xE002 80[0/1]C and FIO[0/1/2/3/4]CLR - 0x3FFF C0[1/3/5/7/9]C) This register is used to produce a LOW level output at port pins configured as GPIO in an OUTPUT mode. -
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NXP Semiconductors Aside from the 32-bit long and word only accessible FIOCLR register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 10–169, too. Next to providing the same functions as the FIOCLR register, these additional registers allow easier and faster access to the physical port pins. -
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NXP Semiconductors Writing to the IOPIN register stores the value in the port output register, bypassing the need to use both the IOSET and IOCLR registers to obtain the entire written value. This feature should be used carefully in an application since it affects the entire port. -
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NXP Semiconductors Table 172. Fast GPIO port Pin value byte and half-word accessible register description Generic Register name FIOxPIN0 FIOxPIN1 FIOxPIN2 FIOxPIN3 FIOxPINL FIOxPINU 6.5 Fast GPIO port Mask register FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF C0[1/3/5/7/9]0) This register is available in the enhanced group of registers only. It is used to select port pins that will and will not be affected by write accesses to the FIOPIN, FIOSET or FIOCLR register. -
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NXP Semiconductors Table 173. Fast GPIO port Mask register (FIO[0/1/2/3/4]MASK - address Symbol 31:0 FP0xMASK, FP1xMASK, FP2xMASK, FP3xMASK FP4xMASK Aside from the 32-bit long and word only accessible FIOMASK register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 10–174, too. -
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NXP Semiconductors 6.6 GPIO interrupt registers The following registers configure the pins of port 0 and port 2 to generate interrupts. 6.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0xE002 8080) This read-only register indicates the presence of interrupt pending on all of the GPIO ports that support GPIO interrupts. -
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NXP Semiconductors 6.6.4 GPIO Interrupt Status for Rising edge register (IO0IntStatR - 0xE002 8084 and IO2IntStatR - 0xE002 80A4) Each bit in these read-only registers indicates the rising edge interrupt status for the corresponding port. Table 178. GPIO Status for Rising edge register (IO0IntStatR - address 0xE002 8084 and... -
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NXP Semiconductors 7. GPIO usage notes 7.1 Example 1: sequential accesses to IOSET and IOCLR affecting the same GPIO pin/bit State of the output configured GPIO pin is determined by writes into the pin’s port IOSET and IOCLR registers. Last of these accesses to the IOSET/IOCLR register will determine the final output of a pin. -
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NXP Semiconductors 7.3 Writing to IOSET/IOCLR vs. IOPIN Write to the IOSET/IOCLR register allows easy change of the port’s selected output pin(s) to high/low level at a time. Only pin/bit(s) in the IOSET/IOCLR written with 1 will be set to high/low level, while those written as 0 will remain unaffected. -
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UM10237 Chapter 11: LPC24XX Ethernet Rev. 02 — 19 December 2008 1. How to read this chapter The Ethernet controller is avialable in parts LPC2458 and LPC2460/68/70/78. 2. Basic configuration The Ethernet controller is configured using the following registers: 1. Power: In the PCONP register Remark: On reset, the Ethernet block is disabled (PCENET = 0). -
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NXP Semiconductors Table 181. Ethernet acronyms, abbreviations, and definitions Acronym or Abbreviation Double-word Fragment Frame Half-word MIIM Octet Packet RMII TCP/IP VLAN Word 4. Features • Ethernet standards support: – Supports 10 or 100 Mbps PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. -
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NXP Semiconductors – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic FCS insertion (CRC) for transmit. – Selectable automatic transmit frame padding. -
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NXP Semiconductors • The host registers module containing the registers in the software view and handling AHB accesses to the Ethernet block. The host registers connect to the transmit and receive datapath as well as the MAC. • The DMA to AHB interface. This provides an AHB master connection that allows the Ethernet block to access the Ethernet SRAM for reading of descriptors, writing of status, and reading and writing data buffers. -
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NXP Semiconductors A receive filter block is used to identify received frames that are not addressed to this Ethernet station, so that they can be discarded. The Rx filters include a perfect address filter and a hash filter. Wake-on-LAN power management support makes it possible to wake the system up from a power-down state -a state in which some of the clocks are switched off -when wake-up frames are received over the LAN. -
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NXP Semiconductors Descriptors, which are stored in memory, contain information about fragments of incoming or outgoing Ethernet frames. A fragment may be an entire frame or a much smaller amount of data. Each descriptor contains a pointer to a memory buffer that holds data associated with a fragment, the size of the fragment buffer, and details of how the fragment will be transmitted or received. -
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NXP Semiconductors PREAMBLE 7 bytes start-of-frame delimiter 1 byte DESTINATION SOURCE ADDRESS ADDRESS DesA DesA DesA DesA oct6 oct5 oct4 oct(0) oct(1) oct(2) oct(3) Fig 27. Ethernet packet fields A packet consists of a preamble, a start-of-frame delimiter and an Ethernet frame. -
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NXP Semiconductors Table 183. Ethernet MII pin descriptions Pin Name ENET_RX_DV ENET_RXD[3:0] ENET_RX_ER ENET_RX_CLK ENET_COL ENET_CRS Table 184. Ethernet RMII pin descriptions Pin Name ENET_TX_EN ENET_TXD[1:0] ENET_RXD[1:0] ENET_RX_ER ENET_CRS ENET_REF_CLK/ ENET_RX_CLK Table 11–185 (MIIM) of the external PHY. Table 185. Ethernet MIIM pin descriptions... -
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NXP Semiconductors Table 186. Summary of Ethernet registers Symbol MAC registers MAC1 MAC2 IPGT IPGR CLRT MAXF SUPP TEST MCFG MCMD MADR MWTD MRDD MIND Control registers Command Status RxDescriptor RxStatus RxDescriptorNumber 0xFFE0 0110 RxProduceIndex RxConsumeIndex TxDescriptor TxStatus TxDescriptorNumber TxProduceIndex... -
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NXP Semiconductors Table 186. Summary of Ethernet registers Symbol FlowControlCounter FlowControlStatus Rx filter registers RxFliterCtrl RxFilterWoLStatus RxFilterWoLClear HashFilterL HashFilterH Module control registers IntStatus IntEnable IntClear IntSet PowerDown The third column in the table lists the accessibility of the register: read-only, write-only, read/write. -
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NXP Semiconductors 7.1.1 MAC Configuration Register 1 (MAC1 - 0xFFE0 0000) The MAC configuration register 1 (MAC1) has an address of 0xFFE0 0000. Its bit definition is shown in Table 187. MAC Configuration register 1 (MAC1 - address 0xFFE0 0000) bit description... -
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NXP Semiconductors Table 188. MAC Configuration register 2 (MAC2 - address 0xFFE0 0004) bit description Symbol Function DELAYED CRC This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. -
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NXP Semiconductors 7.1.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0xFFE0 0008) The Back-to-Back Inter-Packet-Gap register (IPGT) has an address of 0xFFE0 0008. Its bit definition is shown in Table 190. Back-to-back Inter-packet-gap register (IPGT - address 0xFFE0 0008) bit description Symbol... -
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NXP Semiconductors Table 192. Collision Window / Retry register (CLRT - address 0xFFE0 0010) bit description Symbol Function RETRANSMISSION This is a programmable field specifying the number of retransmission attempts MAXIMUM following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). -
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NXP Semiconductors Table 195. Test register (TEST - address 0xFFE0 ) bit description Symbol Function SHORTCUT PAUSE This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. QUANTA TEST PAUSE This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received. -
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NXP Semiconductors Table 198. MII Mgmt Command register (MCMD - address 0xFFE0 0024) bit description Symbol Function READ This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data). -
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NXP Semiconductors Table 202. MII Mgmt Indicators register (MIND - address 0xFFE0 0034) bit description Symbol BUSY SCANNING When ’1’ is returned - indicates a scan operation (continuous MII NOT VALID MII Link Fail When ’1’ is returned - indicates that an MII Mgmt link fail has 31:4 Here are two examples to access PHY via the MII Management Controller. -
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NXP Semiconductors Table 204. Station Address register (SA1 - address 0xFFE0 0044) bit description Symbol STATION ADDRESS, 4th octet 15:8 STATION ADDRESS, 3rd octet 31:16 The station address is used for perfect address filtering and for sending pause control frames. For the ordering of the octets in the packet please refer to 7.1.17 Station Address 2 Register (SA2 - 0xFFE0 0048) -
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NXP Semiconductors Table 206. Command register (Command - address 0xFFE0 0100) bit description Symbol TxFlowControl RMII FullDuplex 31:11 All bits can be written and read. The Tx/RxReset bits are write only, reading will return a 0. 7.2.2 Status Register (Status - 0xFFE0 0104) The Status register (Status) is a Read Only register with an address of 0xFFE0 0104. -
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NXP Semiconductors The receive descriptor base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to ’00’. The register contains the lowest address in the array of descriptors. 7.2.4 Receive Status Base Address Register (RxStatus - 0xFFE0 010C) The receive descriptor base address is a byte address aligned to a word boundary i.e. -
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NXP Semiconductors The receive produce index register defines the descriptor that is going to be filled next by the hardware receive process. After a frame has been received, hardware increments the index. The value is wrapped to 0 once the value of RxDescriptorNumber has been reached. -
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NXP Semiconductors Table 214. Transmit Status Base Address register (TxStatus - address 0xFFE0 0120) bit Symbol 31:2 TxStatus The transmit status base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to ’00’. The register contains the lowest address in the array of statuses. -
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NXP Semiconductors 7.2.12 Transmit Consume Index Register (TxConsumeIndex - 0xFFE0 012C) The Transmit Consume Index register (TxConsumeIndex) is a Read Only register with an address of 0xFFE0 012C. Its bit definition is shown in Table 217. Transmit Consume Index register (TxConsumeIndex - address 0xFFE0 012C) bit... -
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NXP Semiconductors Table 218. Transmit Status Vector 0 register (TSV0 - address 0xFFE0 0158) bit description Symbol Giant Underrun 27:12 Total bytes Control frame Pause Backpressure VLAN The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length... -
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NXP Semiconductors Table 11–220 Table 220. Receive Status Vector register (RSV - address 0xFFE0 0160) bit description Symbol 15:0 Received byte count Packet previously ignored RXDV event previously seen Carrier event previously seen Receive code violation CRC error Length check error... -
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NXP Semiconductors Table 221. Flow Control Counter register (FlowControlCounter - address 0xFFE0 0170) bit Symbol 15:0 MirrorCounter 31:16 PauseTimer 7.2.17 Flow Control Status Register (FlowControlStatus - 0xFFE0 0174) The Flow Control Status register (FlowControlStatus) is a Read Only register with an address of 0xFFE0 8174. -
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NXP Semiconductors Table 223. Receive Filter Control register (RxFilterCtrl - address 0xFFE0 0200) bit Symbol MagicPacketEnWoL RxFilterEnWoL 31:14 - 7.3.2 Receive Filter WoL Status Register (RxFilterWoLStatus - 0xFFE0 0204) The Receive Filter Wake-up on LAN Status register (RxFilterWoLStatus) is a Read Only register with an address of 0xFFE0 0204. -
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NXP Semiconductors Table 225. Receive Filter WoL Clear register (RxFilterWoLClear - address 0xFFE0 0208) bit Symbol AcceptUnicastWoLClr AcceptBroadcastWoLClr AcceptMulticastWoLClr AcceptUnicastHashWoLClr AcceptMulticastHashWoLClr AcceptPerfectWoLClr RxFilterWoLClr MagicPacketWoLClr 31:9 - The bits in this register are write-only; writing resets the corresponding bits in the RxFilterWoLStatus register. -
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NXP Semiconductors Table 228. Interrupt Status register (IntStatus - address 0xFFE0 0FE0) bit description Symbol RxOverrunInt RxErrorInt RxFinishedInt RxDoneInt TxUnderrunInt Interrupt set on a fatal underrun error in the transmit queue. The TxErrorInt TxFinishedInt TxDoneInt 11:8 SoftInt WakeupInt 31:14 The interrupt status register is read-only. Setting can be done via the IntSet register. Reset can be accomplished via the IntClear register. -
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NXP Semiconductors Table 229. Interrupt Enable register (intEnable - address 0xFFE0 0FE4) bit description Symbol TxUnderrunIntEn Enable for interrupt trigger on transmit buffer or descriptor TxErrorIntEn TxFinishedIntEn TxDoneIntEn 11:8 SoftIntEn WakeupIntEn 31:14 7.4.3 Interrupt Clear Register (IntClear - 0xFFE0 0FE8) The Interrupt Clear register (IntClear) is a Write Only register with an address of 0xFFE0 0FE8. -
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NXP Semiconductors Table 231. Interrupt Set register (IntSet - address 0xFFE0 0FEC) bit description Symbol RxOverrunIntSet RxErrorIntSet RxFinishedIntSet RxDoneIntSet TxUnderrunIntSet TxErrorIntSet TxFinishedIntSet TxDoneIntSet 11:8 SoftIntSet WakeupIntSet 31:14 The interrupt set register is write-only. Writing a 1 to a bit of the IntSet register sets the corresponding bit in the status register. -
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NXP Semiconductors RxDescriptor CONTROL CONTROL CONTROL CONTROL CONTROL RxDescriptorNumber CONTROL Fig 28. Receive descriptor memory layout Receive descriptors are stored in an array in memory. The base address of the array is stored in the RxDescriptor register, and should be aligned on a 4 byte address boundary. -
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NXP Semiconductors Each receive descriptor takes two word locations (8 bytes) in memory. Likewise each status field takes two words (8 bytes) in memory. Each receive descriptor consists of a pointer to the data buffer for storing receive data (Packet) and a control word (Control). -
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NXP Semiconductors The StatusInfo word contains flags returned by the MAC and flags generated by the receive datapath reflecting the status of the reception. in the StatusInfo word. Table 237. Receive status information word Symbol 10:0 RxSize 17:11 - ControlFrame... -
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NXP Semiconductors 8.2 Transmit descriptors and statuses Figure 11–29 TxDescriptor CONTROL CONTROL CONTROL CONTROL CONTROL TxDescriptorNumber CONTROL Fig 29. Transmit descriptor memory layout Transmit descriptors are stored in an array in memory. The lowest address of the transmit descriptor array is stored in the TxDescriptor register, and must be aligned on a 4 byte address boundary. -
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NXP Semiconductors Each transmit descriptor takes two word locations (8 bytes) in memory. Likewise each status field takes one word (4 bytes) in memory. Each transmit descriptor consists of a pointer to the data buffer containing transmit data (Packet) and a control word (Control). -
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NXP Semiconductors Table 241. Transmit status information word Symbol 20:0 24:21 CollisionCount Defer ExcessiveDefer ExcessiveCollision Indicates this packet exceeded the maximum collision limit and was LateCollision Underrun NoDescriptor Error For multi-fragment frames, the value of the LateCollision, ExcessiveCollision, ExcessiveDefer, Defer and CollissionCount bits in all but the last fragment in the frame will be 0. -
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NXP Semiconductors data buffer and receive status is returned in the receive descriptor status word. Optionally an interrupt can be generated to notify software that a packet has been received. Note that the DMA manager will prefetch and buffer up to three descriptors. -
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NXP Semiconductors The DMA managers work with arrays of frame descriptors and statuses that are stored in memory. The descriptors and statuses act as an interface between the Ethernet hardware and the device driver software. There is one descriptor array for receive frames and one descriptor array for transmit frames. -
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NXP Semiconductors Ethernet block has finished reading/writing the last descriptor/status of the array (with the highest memory address), the next descriptor/status it reads/writes is the first descriptor/status of the array at the base address of the array. Full and Empty state of descriptor arrays The descriptor arrays can be empty, partially full or full. -
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NXP Semiconductors to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit frames are gathered from multiple fragments in memory and receive frames can be scattered to multiple fragments in memory. By stringing together fragments it is possible to create large frames from small memory areas. -
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NXP Semiconductors be written to the TxDescriptorNumber/RxDescriptorNumber registers using a -1 encoding i.e. the value in the registers is the number of descriptors minus one e.g. if the descriptor array has 4 descriptors the value of the number of descriptors register should be 3. -
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NXP Semiconductors When there is a multi-fragment transmission for fragments other than the last, the Last bit in the descriptor must be set to 0; for the last fragment the Last bit must be set to 1. To trigger an interrupt when the frame has been transmitted and transmission status has been committed to memory, set the Interrupt bit in the descriptor Control field to 1. -
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NXP Semiconductors Each time the Tx DMA manager commits a status word to memory it completes the transmission of a descriptor and it increments the TxConsumeIndex (taking wrap around into account) to hand the descriptor back to the device driver software. Software can re-use the descriptor for new transmissions after hardware has handed it back. -
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NXP Semiconductors IntStatus register is set in the case of a LateCollision, ExcessiveCollision, ExcessiveDefer, or NoDescriptor error; Underrun errors are reported in the TxUnderrun bit of the IntStatus register. Underrun errors can have three causes: • The next fragment in a multi-fragment transmission is not available. This is a nonfatal error. -
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NXP Semiconductors All of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the IntEnable register. Enabling or disabling does not affect the IntStatus register contents, only the propagation of the interrupt status to the CPU (via the Vectored Interrupt Controller). -
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NXP Semiconductors (0x7FE0 11F8) to the TxStatus register. The device driver writes the number of descriptors and statuses minus 1(3) to the TxDescriptorNumber register. The descriptors and statuses in the arrays need not be initialized, yet. At this point, the transmit datapath may be enabled by setting the TxEnable bit in the Command register. -
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NXP Semiconductors Since the Interrupt bit in the descriptor of the last fragment is set, after committing the status of the last fragment to memory the Ethernet block will trigger a TxDoneInt interrupt, which triggers the device driver to inspect the status information. -
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NXP Semiconductors descriptors to be read is determined by the total number of descriptors owned by the hardware: RxConsumeIndex - RxProduceIndex - 1. Block transferring of descriptors minimizes memory load. Read data returned from memory is buffered and consumed as needed. -
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NXP Semiconductors addresses of a packet are calculated once for all the fragments belonging to the same packet and then stored in every StatusHashCRC word of the statuses associated with the corresponding fragments. If the reception reports an error, any remaining data in the receive frame is discarded and the LastFrag bit will be set in the receive status field, so the error flags in all but the last fragment of a frame will always be 0. -
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NXP Semiconductors The receive datapath can generate four different interrupt types: • If the Interrupt bit in the descriptor Control field is set, the Rx DMA will set the RxDoneInt bit in the IntStatus register after receiving a fragment and committing the associated data and status to memory. -
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NXP Semiconductors RxDescriptor 0x7FE010EC 0x7FE010EC PACKET 0x7FE01409 0x7FE010F0 CONTROL 0x7FE010F4 PACKET 0x7FE01411 0x7FE010F8 CONTROL PACKET 0x7FE010FC 0x7FE01419 CONTROL 0x7FE01100 PACKET 0x7FE01104 0x7FE01325 CONTROL 0x7FE01108 descriptor array Fig 31. Receive Example Memory and Registers After reset, the values of the DMA registers will be zero. During initialization, the device driver will allocate the descriptor and status array in memory. -
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NXP Semiconductors continuous memory space; even when a frame is distributed over multiple fragments it will typically be in a linear, continuous memory space; when the descriptors wrap at the end of the descriptor array the frame will not be in a continuous memory space. -
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NXP Semiconductors Each pair of nibbles transferred on the MII interface (or four pairs of bits for RMII) is transferred as a byte on the data write interface after being delayed by 128 or 136 cycles for filtering by the receive filter and buffer modules. The Ethernet block removes preamble, frame start delimiter, and CRC from the data and checks the CRC. -
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NXP Semiconductors The destination address and source address hash CRCs being written in the StatusHashCRC word are the nine most significant bits of the 32 bit CRCs as calculated by the CRC calculator. 9.10 Duplex modes The Ethernet block can operate in full duplex and half duplex mode. Half or full duplex mode needs to be configured by the device driver software during initialization. -
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NXP Semiconductors Transmit flow control is activated by writing 1 to the TxFlowControl bit of the Command register. When the Ethernet block operates in full duplex mode, this will result in transmission of IEEE 802.3/31 pause frames. The flow control continues until a 0 is written to TxFlowControl bit of the Command register. -
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NXP Semiconductors Transmit flow control is enabled via the ‘TX FLOW CONTROL’ bit in the MAC1 configuration register. If the ‘TX FLOW CONTROL’ bit is zero, then the MAC will not transmit pause control frames, software must not initiate pause frame transmissions, and the TxFlowControl bit in the Command register should be zero. -
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NXP Semiconductors In half duplex mode, when the TxFlowControl bit goes high, continuous preamble is sent until TxFlowControl is deasserted. If the medium is idle, the Ethernet block begins transmitting preamble, which raises carrier sense causing all other stations to defer. In the event the transmitting of preamble causes a collision, the backpressure ‘rides through’... -
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NXP Semiconductors Ethernet MAC will stop writing further data in the frame to memory; the FailFilter bit in the status word of the frame will be set to indicate that the software device driver can discard the frame immediately. AcceptUnicastEn... -
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NXP Semiconductors An imperfect filter is available, based on a hash mechanism. This filter applies a hash function to the destination address and uses the hash to access a table that indicates if the frame should be accepted. The advantage of this type of filter is that a small table can cover any possible address. -
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NXP Semiconductors 9.15 Wake-up on LAN Overview The Ethernet block supports power management with remote wake-up over LAN. The host system can be powered down, even including part of the Ethernet block itself, while the Ethernet block continues to listen to packets on the LAN. Appropriately formed packets can be received and recognized by the Ethernet block and used to trigger the host system to wake up from its power-down state. -
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NXP Semiconductors The magic packet detection unit analyzes the Ethernet packets, extracts the packet address and checks the payload for the Magic Packet pattern. The address from the packet is used for matching the pattern (not the address in the SA0/1/2 registers.) A magic... -
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NXP Semiconductors RxEnable = 1 Fig 34. Receive Active/Inactive state machine After a reset, the state machine is in the INACTIVE state. As soon as the RxEnable bit is set in the Command register, the state machine transitions to the ACTIVE state. As soon as the RxEnable bit is cleared, the state machine returns to the INACTIVE state. -
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NXP Semiconductors TxEnable = 1 TxProduceIndex <> TxConsumeIndex Fig 35. Transmit Active/Inactive state machine After reset, the state machine is in the INACTIVE state. As soon as the TxEnable bit is set in the Command register and the Produce and Consume indices are not equal, the state machine transitions to the ACTIVE state. -
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NXP Semiconductors If EPADEN is 1, then small frames will be padded and a CRC will always be added to the padded frames. In this case if ADPEN and VLPEN are both 0, then the frames will be padded to 60 bytes and a CRC will be added creating 64 bytes frames; if VLPEN is 1, the frames will be padded to 64 bytes and a CRC will be added creating 68 bytes frames;... -
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NXP Semiconductors 9.21 Reset The Ethernet block has a hard reset input which is connected to the chip reset, as well as several soft resets which can be activated by setting the appropriate bit(s) in registers. All registers in the Ethernet block have a value of 0 after a hard reset, unless otherwise specified. -
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NXP Semiconductors • RegReset: Resets all of the datapaths and registers in the host registers module, excluding the registers in the MAC. A soft reset of the registers will also abort all AHB transactions of the transmit and receive datapath. The reset bit will be cleared autonomously by the Ethernet block. -
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NXP Semiconductors The flexibility of the descriptors used in the Ethernet block allows the possibility of defining memory buffers in a range of sizes. In order to analyze bus bandwidth requirements, some assumptions must be made about these buffers. The "worst case" is not addressed since that would involve all descriptors pointing to single byte buffers, with most of the memory occupied in holding descriptors and very little data. -
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NXP Semiconductors – Data to be received in an Ethernet frame, the size is variable. – Basic Ethernet rate = 12.5 Mbps. This gives a total rate of 30.5 Mbps for the traffic generated by the Ethernet DMA function. 9.23.2 Types of CPU access •... -
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NXP Semiconductors int crc_calc(char frame_no_fcs[], int frame_len) { char byte; // current byte int q0, q1, q2, q3; crc = 0xFFFFFFFF; for (i = 0; i < frame_len; i++) { return crc; For FCS calculation, this function is passed a pointer to the first byte of the frame and the length of the frame without the FCS. -
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UM10237 Chapter 12: LPC24XX LCD controller Rev. 02 — 19 December 2008 1. How to read this chapter The LCD controller is available on parts LPC2470 and LPC2478 only. 2. Basic configuration The LCD controller is configured using the following registers: 1. -
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NXP Semiconductors • 256 entry, 16-bit palette RAM, arranged as a 128x32-bit RAM. • Frame, line, and pixel clock signals. • AC bias signal for STN, data enable signal for TFT panels. • Supports little and big-endian, and Windows CE data formats. -
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NXP Semiconductors The hardware cursor removes the requirement for this management by providing a completely separate image buffer for the cursor, and superimposing the cursor image on the LCD output stream at the current cursor (X,Y) coordinate. To move the hardware cursor, the software driver supplies a new cursor coordinate. The frame buffer requires no modification. -
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NXP Semiconductors • 16 bpp, direct 4:4:4 RGB, with 4 bpp not being used. 4.6 Monochrome STN panels Monochrome STN panels support one or more of the following modes: • 1 bpp, palettized, 2 gray scales selected from 15. •... -
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NXP Semiconductors Table 243. Pins used for single panel STN displays Pin name LCDLE LCDLP LCDVD[3:0] LCDVD[7:4] LCDVD[23:8] 5.1.2 Signals used for dual panel STN displays The signals used for dual panel STN displays are shown in upper panel data, and LD refers to lower panel data. -
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NXP Semiconductors Table 245. Pins used for TFT displays Pin name LCDVD[9:8] LCDVD[10] LCDVD[11] LCDVD[15:12] LCDVD[17:16] LCDVD[18] LCDVD[19] LCDVD[23:20] 6. LCD controller functional description The LCD controller performs translation of pixel-coded data into the required formats and timings to drive a variety of single or dual panel monochrome and color LCDs. -
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NXP Semiconductors • Bus error. There is also a single combined interrupt that is asserted when any of the individual interrupts become active. Figure 12–36 slave interface Upper panel FIFO Input master FIFO interface control Lower panel FIFO Fig 36. LCD controller block diagram 6.1 AHB interfaces... -
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NXP Semiconductors 6.1.2 AMBA AHB master interface The AHB master interface transfers display data from a selected slave (memory) to the LCD controller DMA FIFOs. It can be configured to obtain data from the 16 kB, on-chip SRAM on AHB1, various types of off-chip static memory, or off-chip SDRAM. -
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NXP Semiconductors Table 12–246 word corresponding to the endianness and bpp combinations. For each of the three supported data formats, the required data for each panel display pixel must be extracted from the data word. Table 246. FIFO bits for Little-endian Byte, Little-endian Pixel order... -
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NXP Semiconductors Table 247. FIFO bits for Big-endian Byte, Big-endian Pixel order FIFO bit UM10237_2 User manual 1 bpp 2 bpp 4 bpp Rev. 02 — 19 December 2008 UM10237 Chapter 12: LPC24XX LCD controller 8 bpp 16 bpp 24 bpp ©... -
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NXP Semiconductors Table 248. FIFO bits for Little-endian Byte, Big-endian Pixel order FIFO bit Table 12–249 UM10237_2 User manual 1 bpp 2 bpp 4 bpp shows the structure of the data in each DMA FIFO word in RGB mode. Rev. 02 — 19 December 2008... -
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NXP Semiconductors Table 249. RGB mode data formats FIFO data 24-bit RGB 6.4 RAM palette The RAM-based palette is a 256 x 16 bit dual-port RAM physically structured as 128 x 32 bits. Two entries can be written into the palette from a single word write access. The Least Significant Bit (LSB) of the serialized pixel data selects between upper and lower halves of the palette RAM. -
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NXP Semiconductors Pixel data values can be written and verified through the AHB slave interface. For information on the supported colors, refer to the section on the related panel type earlier in this chapter. The palette RAM is a dual port RAM with independent controls and addresses for each port. -
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NXP Semiconductors Table 251. Palette data storage for STN color modes. Bit(s) Name (RGB format) G[0] R[4:1] R[0] For monochrome STN mode, only the red palette field bits [4:1] are used. However, in STN color mode the green and blue [4:1] are also used. Only 4 bits per color are used, because the gray scaler only supports 16 different shades per color. -
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NXP Semiconductors When the display point is inside the bounds of the cursor image, the cursor replaces frame buffer pixels with cursor pixels. When the last cursor pixel is displayed, an interrupt is generated that software can use as an indication that it is safe to modify the cursor image. This enables software controlled animations to be performed without flickering for frame synchronized cursors. -
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NXP Semiconductors With FrameSync inactive, the cursor responds immediately to any change in the programmed CRSR_XY value. Some transient smearing effects may be visible if the cursor is moved across the LCD scan line. With FrameSync active, the cursor only updates its position after a vertical synchronization has occurred. -
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NXP Semiconductors 6.5.6 Cursor image format The LCD frame buffer supports three packing formats, but the hardware cursor image requirement has been simplified to support only LBBP. This is little-endian byte, big-endian pixel for Windows CE mode. The Image RAM start address is offset by 0x800 from the LCD base address, as shown in the register description in this chapter. -
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NXP Semiconductors Table 12–255 Table 255. Buffer to pixel mapping for 32 x 32 pixel cursor format Data bits 31:30 29:28 27:26 25:24 23:22 21:20 19:18 17:16 15:14 13:12 11:10 64 by 64 pixel format Only one cursor fits in the memory space in 64 x 64 mode. -
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NXP Semiconductors Table 256. Buffer to pixel mapping for 64 x 64 pixel cursor format Data bits (1, 0) (17, 0) (33, 0) (2, 0) (18, 0) (34, 0) (3, 0) (19, 0) (35, 0) Cursor pixel encoding Each pixel of the cursor requires two bits of information. These are interpreted as Color0, Color1, Transparent, and Transparent inverted. -
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NXP Semiconductors Table 258. Color display driven with 2 2/3 pixel data Byte CLD[7] CLD[6] P2[Green] P2[Red] P5[Red] P4q[Blue] P7[Blue] P7[Green] Each formatter consists of three 3-bit (RGB) shift left registers. RGB pixel data bit values from the gray scaler are concurrently shifted into the respective registers. When enough data is available, a byte is constructed by multiplexing the registered data to the correct bit position to satisfy the RGB data pattern of LCD panel. -
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NXP Semiconductors • Next base address update interrupt. • FIFO underflow interrupt. Each of the four individual maskable interrupts is enabled or disabled by changing the mask bits in the LCD_INT_MSK register. These interrupts are also combined into a single overall interrupt, which is asserted if any of the individual interrupts are both asserted and unmasked. -
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NXP Semiconductors 6.12 LCD power up and power down sequence The LCD controller requires the following power-up sequence to be performed: 1. When power is applied, the following signals are held LOW: • LCDLP • LCDDCLK • LCDFP • LCDENAB/ LCDM •... -
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NXP Semiconductors LCD Power LCDLP, LCDCP, LCDFP, LCDAC, LCDLE Contrast Voltage LCDPWR, LCD[23:0] Display specific delay Fig 40. Power up and power down sequences 7. Register description Table 12–259 their functions. Following the table are details for each register. Table 259. Summary of LCD controller registers... -
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NXP Semiconductors Table 259. Summary of LCD controller registers Address Name 0xFFE1 0C04 CRSR_CFG 0xFFE1 0C08 CRSR_PAL0 0xFFE1 0C0C CRSR_PAL1 0xFFE1 0C10 CRSR_XY 0xFFE1 0C14 CRSR_CLIP 0xFFE1 0C20 CRSR_INTMSK 0xFFE1 0C24 CRSR_INTCLR 0xFFE1 0C28 CRSR_INTRAW 0xFFE1 0C2C CRSR_INTSTAT Reset Value reflects the data stored in used bits only. It does not include reserved bits content. -
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NXP Semiconductors Table 261. Horizontal Timing register (LCD_TIMH, RW - 0xFFE1 0000) Bits Function 31:24 23:16 15:8 reserved 7.2.1 Horizontal timing restrictions DMA requests new data at the start of a horizontal display line. Some time must be allowed for the DMA transfer and for data to propagate down the FIFO path in the LCD interface. -
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NXP Semiconductors • PCD = 5 (LCDCLK / 7) If enough time is given at the start of the line, for example, setting HSW = 6, HBP = 10, data does not corrupt for PCD = 4, the minimum value. -
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NXP Semiconductors Table 262. Vertical Timing register (LCD_TIMV, RW - 0xFFE1 0004) Bits Function 23:16 15:10 7.4 Clock and Signal Polarity register (LCD_POL, RW - 0xFFE1 0008) The LCD_POL register controls various details of clock timing and signal polarity. The contents of the LCD_POL register are described in Table 263. -
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NXP Semiconductors Table 263. Clock and Signal Polarity register (LCD_POL, RW - 0xFFE1 0008) Bits Function reserved UM10237_2 User manual Chapter 12: LPC24XX LCD controller Description Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. -
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NXP Semiconductors Table 263. Clock and Signal Polarity register (LCD_POL, RW - 0xFFE1 0008) Bits Function 10:6 CLKSEL PCD_LO 7.5 Line End Control register (LCD_LE, RW - 0xFFE1 000C) The LCD_LE register controls the enabling of line-end signal LCDLE. When enabled, a positive pulse, four LCDCLK periods wide, is output on LCDLE after a programmable delay, LED, from the last pixel of each display line. -
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NXP Semiconductors Table 264. Line End Control register (LCD_LE, RW - 0xFFE1 000C) Bits Function 31:17 reserved 15:7 reserved 7.6 Upper Panel Frame Base Address register (LCD_UPBASE, RW - 0xFFE1 0010) The LCD_UPBASE register is the color LCD upper panel DMA base address register, and is used to program the base address of the frame buffer for the upper panel. -
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NXP Semiconductors Optionally, the value may be changed mid-frame to create double-buffered video displays. These registers are copied to the corresponding current registers at each LCD vertical synchronization. This event causes the LNBU bit and an optional interrupt to be generated. -
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NXP Semiconductors Table 267. LCD Control register (LCD_CTRL, RW - 0xFFE1 0018) Bits Function BEPO BEBO LcdDual LcdMono8 LcdTFT UM10237_2 User manual Chapter 12: LPC24XX LCD controller Description Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. -
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NXP Semiconductors Table 267. LCD Control register (LCD_CTRL, RW - 0xFFE1 0018) Bits Function LcdBW LcdBpp LcdEn 7.9 Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C) The LCD_INTMSK register controls whether various LCD interrupts occur.Setting bits in this register enables the corresponding raw interrupt LCD_INTRAW status bit values to be passed to the LCD_INTSTAT register for processing as interrupts. -
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NXP Semiconductors Table 268. Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C) Bits Function LNBUIM FUFIM reserved 7.10 Raw Interrupt Status register (LCD_INTRAW, RW - 0xFFE1 0020) The LCD_INTRAW register contains status flags for various LCD controller events. These flags can generate an interrupts if enabled by mask bits in the LCD_INTMSK register. -
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NXP Semiconductors 7.11 Masked Interrupt Status register (LCD_INTSTAT, RW - 0xFFE1 0024) The LCD_INTSTAT register is Read-Only, and contains a bit-by-bit logical AND of the LCD_INTRAW register and the LCD_INTMASK register. A logical OR of all interrupts is provided to the system interrupt controller. -
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NXP Semiconductors Table 271. Interrupt Clear register (LCD_INTCLR, RW - 0xFFE1 0028) Bits Function LNBUIC FUFIC reserved 7.13 Upper Panel Current Address register (LCD_UPCURR, RW - 0xFFE1 002C) The LCD_UPCURR register is Read-Only, and contains an approximate value of the upper panel data DMA address when read. -
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NXP Semiconductors Each word location contains two palette entries. This means that 128 word locations are used for the palette. When configured for little-endian byte ordering, bits [15:0] are the lower numbered palette entry and [31:16] are the higher numbered palette entry. When configured for big-endian byte ordering this is reversed, because bits [31:16] are the low numbered palette entry and [15:0] are the high numbered entry. -
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NXP Semiconductors Table 275. Cursor Image registers (CRSR_IMG, RW - 0xFFE1 0800 to 0xFFE1 0BFC) Bits Function 31:0 CRSR_IMG 7.17 Cursor Control register (CRSR_CTRL, RW - 0xFFE1 0C00) The CRSR_CTRL register provides access to frequently used cursor functions, such as the display on/off control for the cursor, and the cursor number. -
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NXP Semiconductors Table 277. Cursor Configuration register (CRSR_CFG, RW - 0xFFE1 0C04) Bits Function 31:2 reserved FrameSync CrsrSize 7.19 Cursor Palette register 0 (CRSR_PAL0, RW - 0xFFE1 0C08) The cursor palette registers provide color palette information for the visible colors of the cursor. -
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NXP Semiconductors Table 279. Cursor Palette register 1 (CRSR_PAL1, RW - 0xFFE1 0C0C) Bits Function 31:24 reserved 23:16 Blue 15:8 Green 7.21 Cursor XY Position register (CRSR_XY, RW - 0xFFE1 0C10) The CRSR_XY register defines the distance of the top-left edge of the cursor from the top-left side of the cursor overlay. -
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NXP Semiconductors Table 281. Cursor Clip Position register (CRSR_CLIP, RW - 0xFFE1 0C14) Bits Function 31:14 reserved 13:8 CrsrClipY reserved CrsrClipX 7.23 Cursor Interrupt Mask register (CRSR_INTMSK, RW - 0xFFE1 0C20) The CRSR_INTMSK register is used to enable or disable the cursor from interrupting the processor. -
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NXP Semiconductors 7.25 Cursor Raw Interrupt Status register (CRSR_INTRAW, RW - 0xFFE1 0C28) The CRSR_INTRAW register is set to indicate a cursor interrupt. When enabled via the CrsrIM bit in the CRSR_INTMSK register, provides the interrupt to the system interrupt controller. -
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NXP Semiconductors 8. LCD timing diagrams pixel clock (internal) LCD_TIMH (HSW) LCDLP (line synch pulse) suppressed during LCDLP LCDDCLK (panel clock) LCDVD[15:0] (panel data) (1) The active data lines will vary with the type of STN panel (4-bit, 8-bit, color, mono) and with single or dual frames. -
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NXP Semiconductors LCDDCLK (panel clock) LCD_TIMV (VSW) LCDFP (vertical synch pulse) pixel data and horizontal controls for one frame (1) Signal polarities may vary for some displays. Fig 42. Vertical timing for STN displays pixel clock (internal) LCD_TIMH (HSW) LCDLP... -
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NXP Semiconductors LCDDCLK (panel clock) LCDENA (data enable) LCD_TIMV (VSW) LCDFP (vertical synch pulse) pixel data and horizontal control signals for one frame (1) Polarities may vary for some displays. Fig 44. Vertical timing for TFT displays 9. LCD panel signal usage Table 286. -
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NXP Semiconductors Table 286. LCD panel connections for STN single panel mode External pin 4-bit mono STN single panel LPC2478 pin LCD function used LCDVD[8] LCDVD[7] LCDVD[6] LCDVD[5] LCDVD[4] LCDVD[3] P2[9] UD[3] LCDVD[2] P2[8] UD[2] LCDVD[1] P2[7] UD[1] LCDVD[0] P2[6]... -
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NXP Semiconductors Table 287. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel LPC2478 pin LCD function used LCDVD[9] P2[13] LD[1] LCDVD[8] P2[12] LD[0] LCDVD[7] LCDVD[6] LCDVD[5] LCDVD[4] LCDVD[3] P2[9] UD[3] LCDVD[2] P2[8] UD[2]... -
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NXP Semiconductors Table 288. LCD panel connections for TFT panels External TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) LPC2478 pin used function LCDVD[11] - LCDVD[10] - LCDVD[9] LCDVD[8] LCDVD[7] P2[9] RED3 LCDVD[6] P2[8] RED2 LCDVD[5] P2[7] RED1... -
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UM10237 Chapter 13: LPC24XX USB device controller Rev. 02 — 19 December 2008 1. Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register Remark: On reset, the USB block is disabled (PCUSB = 0). 2. -
Page 329: Features
NXP Semiconductors Table 289. USB related acronyms, abbreviations, and definitions used in this chapter Acronym/abbreviation Description EP_RAM SRAM UDCA 3. Features • Fully compliant with the USB 2.0 specification (full speed). • Supports 32 physical (16 logical) endpoints. • Supports Control, Bulk, Interrupt and Isochronous endpoints. -
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NXP Semiconductors Table 290. Fixed endpoint configuration Logical Physical Endpoint type endpoint endpoint Bulk Bulk Isochronous Isochronous Interrupt Interrupt Bulk Bulk Isochronous Isochronous Interrupt Interrupt Bulk Bulk Isochronous Isochronous Interrupt Interrupt Bulk Bulk Isochronous Isochronous Interrupt Interrupt Bulk Bulk Bulk Bulk 5. -
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NXP Semiconductors INTERFACE DMA interface (AHB master) register interface (AHB slave) USB DEVICE BLOCK Fig 45. USB device controller block diagram 5.1 Analog transceiver The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX sends/receives the bi-directional D+ and D- signals of the USB bus. -
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NXP Semiconductors 5.5 DMA engine and bus master interface When enabled for an endpoint, the DMA Engine transfers data between RAM on the AHB bus and the endpoint’s buffer in EP_RAM. A single DMA channel is shared between all endpoints. When transferring data, the DMA Engine functions as a master on the AHB bus through the bus master interface. -
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NXP Semiconductors Once data has been received or sent, the endpoint buffer can be read or written. How this is accomplished depends on the endpoint’s type and operating mode. The two operating modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode. -
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NXP Semiconductors 8.1 Power requirements The USB protocol insists on power management by the device. This becomes very critical if the device draws power from the bus (bus-powered device). The following constraints should be met by a bus-powered device: 1. A device in the non-configured state should draw a maximum of 100 mA from the bus. -
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NXP Semiconductors After entering the suspend state with DEV_CLK_EN and AHB_CLK_EN cleared, the DEV_CLK_ON and AHB_CLK_ON will be cleared when the corresponding clock turns off. When both bits are zero, USB_NEED_CLK will be low, indicating that the chip can be put into Power-down mode by writing to the PCON register. -
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NXP Semiconductors Table 293. Summary of USB device registers Name Description USBEpInd USB Endpoint Index USBMaxPSize USB MaxPacketSize USB transfer registers USBRxData USB Receive Data USBRxPLen USB Receive Packet Length USBTxData USB Transmit Data USBTxPLen USB Transmit Packet Length USBCtrl... -
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NXP Semiconductors Table 294. USB Port Select register (USBPortSel - address 0xFFE0 C110) bit description Symbol PORTSEL 31:2 9.2 Clock control registers 9.2.1 USB Clock Control register (USBClkCtrl - 0xFFE0 CFF4) This register controls the clocking of the USB Device Controller. Whenever software wants to access the device controller registers, both DEV_CLK_EN and AHB_CLK_EN must be set. -
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NXP Semiconductors Table 296. USB Clock Status register (USBClkSt - 0xFFE0 CFF8) bit description Symbol DEV_CLK_ON PORTSEL_CLK_ON AHB_CLK_ON 31:5 9.3 Device interrupt registers 9.3.1 USB Interrupt Status register (USBIntSt - 0xE01F C1C0) The USB Device Controller has three interrupt lines. This register allows software to determine their status with a single read operation. -
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NXP Semiconductors Table 297. USB Interrupt Status register (USBIntSt - address 0xE01F C1C0) bit description Symbol USB_NEED_CLK 30:9 EN_USB_INTS 9.3.2 USB Device Interrupt Status register (USBDevIntSt - 0xFFE0 C200) The USBDevIntSt register holds the status of each interrupt. A 0 indicates no interrupt and 1 indicates the presence of the interrupt. -
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NXP Semiconductors Table 299. USB Device Interrupt Status register (USBDevIntSt - address 0xFFE0 C200) bit description Symbol Description RxENDPKT The current packet in the endpoint buffer is transferred to the CPU. TxENDPKT The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). -
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NXP Semiconductors Table 302. USB Device Interrupt Clear register (USBDevIntClr - address 0xFFE0 C208) bit allocation Reset value: 0x0000 0000 Symbol Symbol Symbol Symbol TxENDPKT ENDPKT Table 303. USB Device Interrupt Clear register (USBDevIntClr - address 0xFFE0 C208) bit description... -
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NXP Semiconductors 9.3.6 USB Device Interrupt Priority register (USBDevIntPri - 0xFFE0 C22C) Writing one to a bit in this register causes the corresponding interrupt to be routed to the USB_INT_REQ_HP interrupt line. Writing zero causes the interrupt to be routed to the USB_INT_REQ_LP interrupt line. -
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NXP Semiconductors Table 308. USB Endpoint Interrupt Status register (USBEpIntSt - address 0xFFE0 C230) bit description Symbol Description EP0RX Endpoint 0, Data Received Interrupt bit. EP0TX Endpoint 0, Data Transmitted Interrupt bit or sent a NAK. EP1RX Endpoint 1, Data Received Interrupt bit. -
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NXP Semiconductors Table 309. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0xFFE0 C234) bit allocation Reset value: 0x0000 0000 Symbol EP15TX EP15RX Symbol EP11TX EP11RX Symbol EP7TX EP7RX Symbol EP3TX EP3RX Table 310. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0xFFE0 C234) bit description... -
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NXP Semiconductors Symbol EP7TX EP7RX Symbol EP3TX EP3RX Table 312. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0xFFE0 C238) bit description Symbol Value Description 31:0 No effect. USBEpIntClr Clears the corresponding bit in USBEpIntSt, by executing the SIE Select bit allocation Endpoint/Clear Interrupt command for this endpoint. -
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NXP Semiconductors Table 315. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0xFFE0 C240) bit allocation Reset value: 0x0000 0000 Symbol EP15TX EP15RX Symbol EP11TX EP11RX Symbol EP7TX EP7RX Symbol EP3TX EP3RX Table 316. USB Endpoint Interrupt Priority register (USBEpIntPri - address 0xFFE0 C240) bit description... -
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NXP Semiconductors Since all the realized endpoints occupy EP_RAM space, the total EP_RAM requirement is where N is the number of realized endpoints. Total EP_RAM space should not exceed 4096 bytes (4 kB, 1 kwords). 9.5.2 USB Realize Endpoint register (USBReEp - 0xFFE0 C244) Writing one to a bit in this register causes the corresponding endpoint to be realized. -
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NXP Semiconductors USBReEp |= (UInt32) ((0x1 << endpt)); /* Load Endpoint index Reg with physical endpoint no.*/ USBEpIn = (UInt32) endpointnumber; /* load the max packet size Register */ USBEpMaxPSize = MPS; /* check whether the EP_RLZED bit in the Device Interrupt Status register is set while (!(USBDevIntSt &... -
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NXP Semiconductors The Endpoint Index is set via the USBEpIn register. MPS_EP0 to MPS_EP31 are accessed via the USBMaxPSize register. Fig 46. USB MaxPacketSize register array indexing 9.6 USB transfer registers The registers in this group are used for transferring data between endpoint buffers and RAM in Slave mode operation. -
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NXP Semiconductors Table 322. USB Receive Packet Length register (USBRxPlen - address 0xFFE0 C220) bit Symbol PKT_LNGTH - PKT_RDY 31:12 - 9.6.3 USB Transmit Data register (USBTxData - 0xFFE0 C21C) For an IN transaction, the CPU writes the endpoint data into this register. Before writing to this register, the WR_EN bit and LOG_ENDPOINT field of the USBCtrl register should be set appropriately, and the packet length should be written to the USBTxPlen register. -
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NXP Semiconductors Table 324. USB Transmit Packet Length register (USBTxPLen - address 0xFFE0 C224) bit Symbol PKT_LNGTH - 31:10 - 9.6.5 USB Control register (USBCtrl - 0xFFE0 C228) This register controls the data transfer operation of the USB device. It selects the endpoint buffer that is accessed by the USBRxData and USBTxData registers, and enables reading and writing them. -
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NXP Semiconductors Table 326. USB Command Code register (USBCmdCode - address 0xFFE0 C210) bit description Symbol Value 15:8 CMD_PHASE 0x01 0x02 0x05 23:16 CMD_CODE/ CMD_WDATA 31:24 - 9.7.2 USB Command Data register (USBCmdData - 0xFFE0 C214) This register contains the data retrieved after executing a SIE command. When the data is ready to be read, the CD_FULL bit of the USBDevIntSt register is set. -
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NXP Semiconductors Symbol EP15 EP14 Symbol Table 329. USB DMA Request Status register (USBDMARSt - address 0xFFE0 C250) bit description Symbol Value Description Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0). Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0). -
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NXP Semiconductors Software can also use this register to initiate a DMA transfer to proactively fill an IN endpoint buffer before an IN token packet is received from the host. USBDMARSet is a write only register. The USBDMARSet bit allocation is identical to the USBDMARSt register Table 331. -
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NXP Semiconductors 9.8.6 USB EP DMA Enable register (USBEpDMAEn - 0xFFE0 C288) Writing one to a bit to this register will enable the DMA operation for the corresponding endpoint. Writing zero has no effect.The DMA cannot be enabled for control endpoints EP0 and EP1. -
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NXP Semiconductors Table 336. USB DMA Interrupt Status register (USBDMAIntSt - address 0xFFE0 C290) bit Symbol NDDR 31:3 - 9.8.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0xFFE0 C294) Writing a one to a bit in this register enables the corresponding bit in USBDMAIntSt to generate an interrupt on the USB_INT_REQ_DMA interrupt line when set. -
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NXP Semiconductors Table 338. USB End of Transfer Interrupt Status register (USBEoTIntSt - address Symbol 31:0 EPxx 9.8.11 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0xFFE0 C2A4) Writing one to a bit in this register clears the corresponding bit in the USBEoTIntSt register. -
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NXP Semiconductors 9.8.14 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0xFFE0 C2B0) Writing one to a bit in this register clears the corresponding bit in the USBNDDRIntSt register. Writing zero has no effect. USBNDDRIntClr is a write only register. -
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NXP Semiconductors Table 345. USB System Error Interrupt Clear register (USBSysErrIntClr - address Symbol 31:0 EPxx 9.8.18 USB System Error Interrupt Set register (USBSysErrIntSet - 0xFFE0 C2C0) Writing one to a bit in this register sets the corresponding bit in the USBSysErrIntSt register. -
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NXP Semiconductors register to request low priority interrupt handling. However, the USBDevIntPri register can route either the FRAME or the EP_FAST bit to the USB_INT_REQ_HP bit in the USBIntSt register. Only one of the EP_FAST and FRAME interrupt events can be routed to the USB_INT_REQ_HP bit. -
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NXP Semiconductors interrupt event on from other Endpoints USBEpIntSt USBEpIntEn[n] USBEpIntPri[n] USBDMARSt to DMA engine USBEoTIntST USBNDDRIntSt USBSysErrIntSt For simplicity, USBDevIntEn and USBDMAIntEn are not shown. Fig 47. Interrupt event handling UM10237_2 User manual Chapter 13: LPC24XX USB device controller... -
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NXP Semiconductors 11. Serial interface engine command description The functions and registers of the Serial Interface Engine (SIE) are accessed using commands, which consist of a command code followed by optional data bytes (read or write action). The USBCmdCode registers are used for these accesses. -
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NXP Semiconductors Table 347. SIE command code table Command name Recipient Device commands Set Address Device Configure Device Device Set Mode Device Read Current Frame Number Device Read Test Register Device Set Device Status Device Get Device Status Device Get Error Code... -
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NXP Semiconductors Table 349. Configure Device Register bit description Symbol Description CONF_DEVICE Device is configured. All enabled non-control endpoints will respond. This bit is cleared by hardware when a bus reset occurs. When set, the UP_LED signal is driven LOW if the device is not in the suspended state (SUS=0). -
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NXP Semiconductors 11.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2 bytes) Returns the frame number of the last successfully received SOF. The frame number is eleven bits wide. The frame number returns least significant byte first. In case the user is only interested in the lower 8 bits of the frame number, only the first byte needs to be read. -
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NXP Semiconductors Table 351. Set Device Status Register bit description Bit Symbol SUS_CH 7:5 - 11.7 Get Device Status (Command: 0xFE, Data: read 1 byte) The Get Device Status command returns the Device Status Register. Reading the device status returns 1 byte of data. The bit field definition is same as the Set Device Status... -
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NXP Semiconductors Table 352. Get Error Code Register bit description Symbol Value 11.9 Read Error Status (Command: 0xFB, Data: read 1 byte) This command reads the 8-bit Error register from the USB device. This register records which error events have recently occurred in the SIE. If any of these bits are set, the ERR_INT bit of USBDevIntSt is set. -
Page 368: Select Endpoint (Command: 0X00 - 0X1F, Data: Read 1 Byte (Optional))
NXP Semiconductors 11.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional)) The Select Endpoint command initializes an internal pointer to the start of the selected buffer in EP_RAM. Optionally, this command can be followed by a data read, which returns some additional information on the packet(s) in the endpoint buffer(s). -
Page 369: Select Endpoint/Clear Interrupt (Command: 0X40 - 0X5F, Data: Read 1 Byte)
NXP Semiconductors Table 354. Select Endpoint Register bit description Bit Symbol B_2_FULL 11.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1 byte) Commands 0x40 to 0x5F are identical to their Select Endpoint equivalents, with the following differences: •... -
Page 370: Clear Buffer (Command: 0Xf2, Data: Read 1 Byte (Optional))
NXP Semiconductors Table 355. Set Endpoint Status Register bit description Bit Symbol RF_MO CND_ST 11.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional)) When an OUT packet sent by the host has been received successfully, an internal hardware FIFO status Buffer_Full flag is set. All subsequent packets will be refused by returning a NAK. -
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NXP Semiconductors Internally, there is a hardware FIFO status flag called Buffer_Full. This flag is set by the Validate Buffer command and cleared when the data has been sent on the USB bus and the buffer is empty. A control IN buffer cannot be validated when its corresponding OUT buffer has the Packet Over-written (PO) bit (see the Clear Buffer Register) set or contains a pending SETUP packet. -
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NXP Semiconductors – Clear all DMA interrupts using USBEoTIntClr, USBNDDRIntClr, and USBSysErrIntClr. – Prepare the UDCA in system memory. – Write the desired address for the UDCA to USBUDCAH (for example 0x7FD0 0000). – Enable the desired endpoints for DMA operation using USBEpDMAEn. -
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NXP Semiconductors endpoints, the next packet will be received irrespective of whether the buffer has been cleared. Any data not read from the buffer before the end of the frame is lost. See Section 13–15 “Double buffered endpoint operation” If the software clears RD_EN before the entire packet is read, reading is terminated, and the data remains in the endpoint’s buffer. -
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NXP Semiconductors 14.2 USB device communication area The CPU and DMA controller communicate through a common area of memory, called the USB Device Communication Area, or UDCA. The UDCA is a 32-word array of DMA Descriptor Pointers (DDPs), each of which corresponds to a physical endpoint. Each DDP points to the start address of a DMA Descriptor, if one is defined for the endpoint. -
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NXP Semiconductors In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT endpoints (INAK_BO and INAK_IO) should be set to 0 using the SIE Set Mode command (Section 13–11.3). 14.4 The DMA descriptor DMA transfers are described by a data structure called the DMA Descriptor (DD). -
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NXP Semiconductors Table 357. DMA descriptor Word Access position (H/W) Write only in ATLE mode Legend: R - Read; W - Write; I - Initialize 14.4.1 Next_DD_pointer Pointer to the memory location from where the next DMA descriptor will be fetched. -
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NXP Semiconductors 14.4.6 DMA_buffer_length This indicates the depth of the DMA buffer allocated for transferring the data. The DMA engine will stop using this descriptor when this limit is reached and will look for the next descriptor. In Normal mode operation, software sets this value for both IN and OUT endpoints. In ATLE mode operation, software sets this value for IN endpoints only. -
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NXP Semiconductors 14.4.11 LS_byte_extracted Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of the transfer length has been extracted. The extracted size is reflected in the DMA_buffer_length field, bits 23:16. 14.4.12 MS_byte_extracted Used in ATLE mode. When set, this bit indicates that the Most Significant Byte (MSB) of the transfer size has been extracted. -
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NXP Semiconductors If a new descriptor has to be read, the DMA engine will calculate the location of the DDP for this endpoint and will fetch the start address of the DD from this location. A DD start address at location zero is considered invalid. In this case the NDDR interrupt is raised. -
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NXP Semiconductors USB transfer end completion - If the current packet is fully transferred and its size is less than the Max_packet_size field, and the end of the DMA buffer is still not reached, the USB transfer end completion occurs. The DD will be written back to the memory with DD_retired set and DD_Status set to the DataUnderrun completion code. -
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NXP Semiconductors The isochronous packet size is stored in memory as shown in figure 32. Each word in the packet size memory shown is divided into fields: Frame_number (bits 31 to 17), Packet_valid (bit 16), and Packet_length (bits 15 to 0). The space allocated for the packet size memory for a given DD should be DMA_buffer_length words in size –... -
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NXP Semiconductors DMA_buffer_length 0x000A Present_DMA_Count after 4 packets 0x000A0010 0x80000035 0x60000010 Fig 49. Isochronous OUT endpoint operation example 14.7 Auto Length Transfer Extraction (ATLE) mode operation Some host drivers such as NDIS (Network Driver Interface Specification) host drivers are capable of concatenating small USB transfers (delta transfers) to form a single large USB transfer. -
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NXP Semiconductors data to be sent by host driver 160 bytes 100 bytes Fig 50. Data transfer in ATLE mode Figure 13–50 concatenates two USB transfers of 160 bytes and 100 bytes, respectively. Given a MaxPacketSize of 64, the device hardware interprets this USB transfer as four packets of 64 bytes and a short packet of 4 bytes. -
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NXP Semiconductors In ATLE mode, the last buffer length to be transferred always ends with a short or empty packet indicating the end of the USB transfer. If the concatenated transfer lengths are such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) host will send an empty packet to mark the end of the USB transfer. -
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NXP Semiconductors 14.7.4 Ending the packet transfer The DMA engine proceeds with the transfer until the number of bytes specified in the field DMA_buffer_length is transferred to or from the USB RAM. Then the EOT interrupt will be generated. If this happens in the middle of the packet, the linked DD will get loaded and the remaining part of the packet gets transferred to or from the address pointed by the new DD. -
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NXP Semiconductors 5. Software sends the SIE Select Endpoint command to read the Select Endpoint Register and test the FE bit. Software finds that the active buffer (B_2) has data (FE=1). Software clears the endpoint interrupt and begins reading the contents of B_2. -
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NXP Semiconductors 11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by software will go into B_2. In DMA mode, switching of the active buffer is handled automatically in hardware. For Bulk IN endpoints, proactively filling an endpoint buffer to take advantage of the double buffering can be accomplished by manually starting a packet transfer using the USBDMARSet register. -
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UM10237 Chapter 14: LPC24XX USB Host controller Rev. 02 — 19 December 2008 1. Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register Remark: On reset, the USB block is disabled (PCUSB = 0). 2. -
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NXP Semiconductors • OpenHCI specifies the operation and interface of the USB Host Controller and SW Driver – USBOperational: Process Lists and generate SOF Tokens. – USBReset: Forces reset signaling on the bus, SOF disabled. – USBSuspend: Monitor USB for wakeup activity. -
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NXP Semiconductors Table 359. USB OTG port pins Pin name Direction Description USB_INT1 OTG ATX interrupt USB_SCL1 USB_SDA1 USB_TX_E1 Transmit enable USB_TX_DP1 D+ transmit data D − transmit data USB_TX_DM1 USB_RCV1 Differential receive data USB_RX_DP1 D+ receive data D − receive data... -
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NXP Semiconductors Table 360. USB Host register address definitions Name Address HcRevision 0xFFE0 C000 HcControl 0xFFE0 C004 HcCommandStatus 0xFFE0 C008 HcInterruptStatus 0xFFE0 C00C HcInterruptEnable 0xFFE0 C010 HcInterruptDisable 0xFFE0 C014 HcHCCA 0xFFE0 C018 HcPeriodCurrentED 0xFFE0 C01C HcControlHeadED 0xFFE0 C020 HcControlCurrentED 0xFFE0 C024... -
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NXP Semiconductors Table 360. USB Host register address definitions Name Address HcRhStatus 0xFFE0 C050 HcRhPortStatus[1] 0xFFE0 C054 HcRhPortStatus[2] 0xFFE0 C058 R/W Module_ID/Ver_Rev_ID 0xFFE0 C0FC The R/W column in Table 14–360 lists the accessibility of the register: a) Registers marked ‘R’ for access will return their current value when read. -
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UM10237 Chapter 15: LPC24XX USB OTG controller Rev. 02 — 19 December 2008 1. Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register Remark: On reset, the USB block is disabled (PCUSB = 0). 2. -
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NXP Semiconductors support an OTG connection. The communication between the register interface and an external OTG transceiver is handled through an I OTG transceiver interrupt signal. For USB connections that use the device or host controller only (not OTG), the ports use an embedded USB Analog Transceiver (ATX). -
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NXP Semiconductors Table 361. USB OTG port 1 pins Pin name Direction Description via its corresponding PINSEL register, it is driven HIGH internally. Port U1 USB_D+1 Positive differential data USB_D − 1 Negative differential data USB_CONNECT1 O SoftConnect control signal... -
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NXP Semiconductors 1. Use the internal USB transceiver for USB signalling and use the external OTG transceiver for OTG functionality only (see internal transceiver in VP/VM mode. 2. Use the external OTG transceiver in VP/VM mode for OTG functionality and USB signalling (see In both cases port U2 is connected as a host. -
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NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 54. USB OTG port configuration: VP_VM mode UM10237_2 User manual Chapter 15: LPC24XX USB OTG controller RESET_N OE_N/INT_N DAT_VP SE0_VM ISP1301 ADR/PSW SPEED SUSPEND INT_N Rev. -
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NXP Semiconductors 6.2 Connecting USB as a two-port host Both ports U1 and U2 are connected as hosts using an embedded USB transceiver. There is no OTG functionality on either port. USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_PPWR2 USB_OVRCR2... -
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NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 Fig 56. USB OTG port configuration: port U1 host, port U2 device 7. Register description The OTG and I The Device and Host registers are explained in USB Device Controller and USB Host (OHCI) Controller chapters. -
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NXP Semiconductors Table 362. USB OTG and I Name OTGIntSet OTGIntClr OTGStCtrl OTGTmr C registers I2C_RX I2C_TX I2C_STS I2C_CTL I2C_CLKHI I2C_CLKLO Clock control registers OTGClkCtrl OTGClkSt Bits 0 and 1 of this register are used to control the routing of the USB pins to ports 1 and 2 in device-only applications (see 7.1 USB Interrupt Status Register (USBIntSt - 0xE01F C1C0) -
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NXP Semiconductors 7.2 OTG Interrupt Status Register (OTGIntSt - 0xE01F C100) Bits is this register are set by hardware when the interrupt event occurs during the HNP handoff sequence. See Table 364. OTG Interrupt Status register (OTGIntSt - address 0xE01F C100) bit description... -
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NXP Semiconductors 2. Free running mode: an interrupt is generated at the end of TIMEOUT_CNT (see Section 15–7.7 “OTG Timer Register (OTGTmr - 0xFFE0 and the timer value is reloaded into the counter. The timer is not disabled in this mode. -
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NXP Semiconductors Fig 57. Port selection for PORT_FUNC bit 0 = 0 and PORT_FUNC bit 1 = 0. Table 366. Port function truth table PORT_FUNC[1] = 0 PORT_FUNC[1] = 1 7.7 OTG Timer Register (OTGTmr - 0xFFE0 C114) Table 367. OTG Timer register (OTGTmr - address 0xFFE0 C114) bit description... -
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NXP Semiconductors Table 368. OTG_clock_control register (OTG_clock_control - address 0xFFE0 CFF4) bit Symbol DEV_CLK_EN I2C_CLK_EN OTG_CLK_EN AHB_CLK_EN 31:5 7.9 OTG Clock Status Register (OTGClkSt - 0xFFE0 CFF8) This register holds the clock availability status. When enabling a clock via OTGClkCtrl, software should poll the corresponding bit in this register. -
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NXP Semiconductors Table 369. OTG_clock_status register (OTGClkSt - address 0xFFE0 CFF8) bit description Symbol AHB_CLK_ON 31:5 7.10 I2C Receive Register (I2C_RX - 0xFFE0 C300) This register is the top byte of the receive FIFO. The receive FIFO is 4 bytes deep. The Rx FIFO is flushed by a hard reset or by a soft reset (I2C_CTL bit 7). -
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NXP Semiconductors Table 372. I2C status register (I2C_STS - address 0xFFE0 C304) bit description Symbol Value Description DRMI DRSI Active UM10237_2 User manual Chapter 15: LPC24XX USB OTG controller Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. -
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NXP Semiconductors Table 372. I2C status register (I2C_STS - address 0xFFE0 C304) bit description Symbol Value Description 31:12 - 7.13 I2C Control Register (I2C_CTL - 0xFFE0 C308) The I2C_CTL register is used to enable interrupts and reset the I Enabled interrupts cause the USB_I2C_INT interrupt output line to be asserted when set. -
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NXP Semiconductors Table 373. I2C Control register (I2C_CTL - address 0xFFE0 C308) bit description Symbol Value Description DRMIE Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low. -
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NXP Semiconductors 7.15 I2C Clock Low Register (I2C_CLKLO - 0xFFE0 C310) The CLK register holds a terminal count for counting 48 MHz clock cycles to create the low period of the slower I Table 375. I2C_CLKLO register (I2C_CLKLO - address 0xFFE0 C310) bit description... -
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NXP Semiconductors 8. HNP support This section describes the hardware support for the Host Negotiation Protocol (HNP) provided by the OTG controller. When two dual-role OTG devices are connected to each other, the plug inserted into the mini-AB receptacle determines the default role of each device. The device with the mini-A plug inserted becomes the default Host (A-device), and the device with the mini-B plug inserted becomes the default Peripheral (B-device). -
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NXP Semiconductors OHCI STACK STACK DEVICE STACK Fig 59. USB OTG controller with software stack 8.1 B-device: peripheral to host switching In this case, the default role of the OTG controller is peripheral (B-device), and it switches roles from Peripheral to Host. -
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NXP Semiconductors disconnect device controller from U1 wait 25 μs for bus to settle connect from A-device detected? set HNP_SUCCESS set PORT_FUNC[0] drive J on internal host controller port and SE0 on U1 Fig 60. Hardware support for B-device switching from peripheral state to host state Figure 15–61... -
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NXP Semiconductors when host sends SET_FEATURE Fig 61. State transitions implemented in software during B-device switching from peripheral to host Note that only the subset of B-device HNP states and state transitions supported by hardware are shown. Software is responsible for implementing all of the HNP states. -
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NXP Semiconductors /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Add D+ pull-up /* Add D+ pull-up through ISP1301 */ OTG_I2C_TX = 0x15A; // Send ISP1301 address, R/W=0 OTG_I2C_TX = 0x006; // Send OTG Control (Set) register address OTG_I2C_TX = 0x201;... -
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NXP Semiconductors bus suspended ? bus reset detected? Fig 62. Hardware support for A-device switching from host state to peripheral state Figure 15–63 the hardware actions setting TMR, HNP_SUCCESS, and HNP_FAILURE. The relationship of the software actions to the Dual-Role A-Device states is also shown. -
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NXP Semiconductors TMR set? clear BDIS_ACON_EN bit in external OTG transceiver discharge V go to a_wait_vfall Fig 63. State transitions implemented in software during A-device switching from host to peripheral Note that only the subset of A-device HNP states and state transitions supported by hardware are shown. -
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NXP Semiconductors Set BDIS_ACON_EN in external OTG transceiver /* Set BDIS_ACON_EN in ISP1301 */ OTG_I2C_TX = 0x15A; // Send ISP1301 address, R/W=0 OTG_I2C_TX = 0x004; // Send Mode Control 1 (Set) register address OTG_I2C_TX = 0x210; // Set BDIS_ACON_EN bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS &... -
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NXP Semiconductors Load and enable OTG timer /* The following assumes that the OTG timer has previously been */ /* configured for a time scale of 1 ms (TMR_SCALE = “10”) /* and monoshot mode (TMR_MODE = 0) /* Load the timeout value to implement the a_aidl_bdis_tmr timer */ the minimum value is 200 ms OTG_TIMER = 200;... -
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NXP Semiconductors cclk PCUSB CLOCK SWITCH CLOCK USB CLOCK SWITCH DIVIDER usbclk (48 MHz) CLOCK SWITCH CLOCK SWITCH CLOCK SWITCH Fig 64. Clocking and power control 9.1 Device clock request signals The Device controller has two clock request signals, dev_need_clk and dev_dma_need_clk. -
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NXP Semiconductors The dev_dma_need_clk signal is asserted on any Device controller DMA access to memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA throughput is not affected by any latency associated with re-enabling ahb_master_clk. -
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NXP Semiconductors 4. Enable the desired USB pin functions by writing to the corresponding PINSEL registers. 5. Follow the appropriate steps in initialize the device controller. 6. Follow the guidelines given in the OpenHCI specification for initializing the host controller. -
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UM10237 Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter (UART) 0/2/3 Rev. 02 — 19 December 2008 1. Basic configuration The UART0/2/3 peripherals are configured using the following registers: 1. Power: In the PCONP register Remark: On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled (PCUART2/3 = 0). -
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NXP Semiconductors 4. Register description Each UART contains registers as shown in (DLAB) is contained in UnLCR7 and enables access to the Divisor Latches. UM10237_2 User manual Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter Table Rev. 02 — 19 December 2008 UM10237 16–377. - Page 424 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 377. UART Register Map Generic Description Bit functions and addresses Name BIT7 BIT6 BIT5 Receiver Buffer (DLAB= Register Transmit (DLAB= Holding Register Divisor Latch (DLAB= Divisor Latch (DLAB= Interrupt Enable (DLAB= Register Interrupt ID Register...
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Page 425: Uart3
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 377. UART Register Map Generic Description Bit functions and addresses Name Line Status TEMT THRE Register FIFO Error Scratch Pad Register Auto-baud Reserved [31:10] Control Register Reserved [7:3] IrDA Control Reserved Register Fractional MulVal... -
Page 426: 0Xe007 C004 When Dlab = 1)
NXP Semiconductors 16.4.1 UARTn Receiver Buffer Register (U0RBR - 0xE000 C000, U2RBR - 0xE007 8000, U3RBR - 0xE007 C000 when DLAB = 0, Read Only) The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface. -
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NXP Semiconductors higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed. The Divisor Latch Access Bit (DLAB) in UnLCR must be one in order to access the UARTn Divisor Latches. -
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NXP Semiconductors 4.5 UARTn Interrupt Identification Register (U0IIR - 0xE000 C008, U2IIR - 0xE007 8008, U3IIR - 0x7008 C008, Read Only) The UnIIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an UnIIR access. If an interrupt occurs during an UnIIR access, the interrupt is recorded for the next UnIIR access. -
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NXP Semiconductors The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches the trigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls below the trigger level. -
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NXP Semiconductors THRE = 1 and there have not been at least two characters in the UnTHR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to UnTHR without a THRE interrupt to decode and service. -
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NXP Semiconductors Table 386: UARTn Line Control Register (U0LCR - address 0xE000 C00C, Bit Symbol 1:0 Word Length Select Stop Bit Select Parity Enable 5:4 Parity Select Break Control Divisor Latch Access Bit (DLAB) 4.8 UARTn Line Status Register (U0LSR - 0xE000 C014, U2LSR -... -
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NXP Semiconductors Table 387: UARTn Line Status Register (U0LSR - address 0xE000 C014, Bit Symbol Parity Error (PE) Framing Error (FE) Break Interrupt (BI) Transmitter Holding Register Empty (THRE)) Transmitter Empty (TEMT) Error in RX FIFO (RXFE) UM10237_2 User manual... -
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NXP Semiconductors 4.9 UARTn Scratch Pad Register (U0SCR - 0xE000 C01C, U2SCR - 0xE007 801C U3SCR - 0xE007 C01C) The UnSCR has no effect on the UARTn operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the UnSCR has occurred. -
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NXP Semiconductors 16.4.10.1 Auto-baud The UARTn auto-baud function can be used to measure the incoming baud-rate based on the ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers UnDLM and UnDLL accordingly. -
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NXP Semiconductors 1. On UnACR Start bit setting, the baud-rate measurement counter is reset and the UARTn UnRSR is reset. The UnRSR baud rate is switch to the highest rate. 2. A falling edge on UARTn Rx pin triggers the beginning of the start bit. The rate measuring counter will start counting pclk cycles optionally pre-scaled by the fractional baud-rate generator. -
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NXP Semiconductors start UARTn RX U1ACR start rate counter 16xbaud_rate 16 cycles b. Mode 1 (only start bit is used for auto-baud) Fig 65. Autobaud a) mode 0 and b) mode 1 waveform 4.11 IrDA Control Register for UART3 Only (U3ICR - 0xE007 C024) The IrDA Control Register enables and configures the IrDA mode for UART3 only. -
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NXP Semiconductors Table 391: IrDA Pulse Width FixPulseEn 4.12 UARTn Fractional Divider Register (U0FDR - 0xE000 C028, U2FDR - 0xE007 8028, U3FDR - 0xE007 C028) The UART0/2/3 Fractional Divider Register (U0/2/3FDR) controls the clock pre-scaler for the baud rate generation and can be read and written at the user’s discretion. This pre-scaler takes the APB clock and generates an output clock according to the specified fractional requirements. -
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NXP Semiconductors The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 0 < MULVAL ≤ 15 2. 0 ≤ DIVADDVAL < 15 3. DIVADDVAL<MULVAL The value of the U0/2/3FDR should not be modified while transmitting/receiving data or data may be lost or corrupted. -
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NXP Semiconductors Pick another FR the range [1.1, 1.9] Fig 66. Algorithm for setting UART dividers UM10237_2 User manual Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an integer? = 1.5 from... -
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NXP Semiconductors Table 393. Fractional Divider setting look-up table DivAddVal/ MulVal 1.000 1.067 1/15 1.071 1/14 1.077 1/13 1.083 1/12 1.091 1/11 1.100 1/10 1.111 1.125 1.133 2/15 1.143 1.154 2/13 1.167 1.182 2/11 1.200 1.214 3/14 1.222 1.231 3/13 4.12.1.1 Example 1: PCLK = 14.7456 MHz, BR = 9600... -
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NXP Semiconductors Table 16–394 Table 394: UARTn Transmit Enable Register (U0TER - address 0xE000 C030, Symbol TXEN 5. Architecture The architecture of the UARTs 0, 2 and 3 are shown below in the block diagram. The APB interface provides a communications link between the CPU or host and the UART. -
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NXP Semiconductors UnINTR PA[2:0] PSEL PSTB PWRITE PD[7:0] PCLK Fig 67. UART0, 2 and 3 block diagram UM10237_2 User manual Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter INTERRUPT UnIER UnIIR UnSCR INTERFACE Rev. 02 — 19 December 2008 UM10237 UnTX NTXRDY... -
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UM10237 Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter (UART) 1 Rev. 02 — 19 December 2008 1. Basic configuration The UART1 peripheral is configured using the following registers: 1. Power: In the PCONP register Remark: On reset, UART1 is enabled (PCUART1 = 1). 2. -
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NXP Semiconductors 3. Pin description Table 395: UART1 Pin Description Type RXD1 Input TXD1 Output Serial Output. Serial transmit data. CTS1 Input DCD1 Input DSR1 Input DTR1 Output Data Terminal Ready. Active low signal indicates that the UART1 is ready to Input RTS1 Output Request To Send. - Page 445 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 396: UART1 register map Name Description Bit functions and addresses BIT7 BIT6 U1RBR Receiver Buffer Register U1THR Transmit Holding Register U1DLL Divisor Latch U1DLM Divisor Latch U1IER Interrupt Enable Register Enable Interrupt U1IIR Interrupt ID...
- Page 446 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 396: UART1 register map …continued Name Description Bit functions and addresses U1ACR Autobaud Control Register U1FDR Fractional Divider Mulval Register U1TER Transmit TXEN Enable Register Reset Value reflects the data stored in used bits only. It does not include reserved bits content. Reserved [31:10] Reserved [7:3] Auto...
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NXP Semiconductors 4.1 UART1 Receiver Buffer Register (U1RBR - 0xE001 0000, when DLAB = 0 Read Only) The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest”... -
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NXP Semiconductors Table 399: UART1 Divisor Latch LSB Register (U1DLL - address 0xE001 0000 when Symbol DLLSB Table 400: UART1 Divisor Latch MSB Register (U1DLM - address 0xE001 0004 when Symbol DLMSB 4.4 UART1 Interrupt Enable Register (U1IER - 0xE001 0004, when DLAB = 0) The U1IER is used to enable the four UART1 interrupt sources. -
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NXP Semiconductors Table 401: UART1 Interrupt Enable Register (U1IER - address 0xE001 0004 when DLAB = 0) Symbol Interrupt Enable ABEOIntEn ABTOIntEn 31:10 - 4.5 UART1 Interrupt Identification Register (U1IIR - 0xE001 0008, Read Only) The U1IIR provides a status code that denotes the priority and source of a pending interrupt. -
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NXP Semiconductors Table 402: UART1 Interrupt Identification Register (U1IIR - address 0xE001 0008, Read Only) Symbol IntId FIFO Enable ABEOInt ABTOInt 31:10 - Bit U1IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud condition. The auto-baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto-baud Control Register. -
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NXP Semiconductors wished to send a 105 character message and the trigger level was 10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters. -
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NXP Semiconductors It is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem input RI will generate a modem interrupt. The source of the modem interrupt can be determined by examining U1MSR[3:0]. -
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NXP Semiconductors Table 405: UART1 Line Control Register (U1LCR - address 0xE001 000C) bit description Symbol Value Description Parity Select Break Control Divisor Latch Access (DLAB) 4.8 UART1 Modem Control Register (U1MCR - 0xE001 0010) The U1MCR enables the modem loopback mode and controls the modem output signals. -
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NXP Semiconductors Table 406: UART1 Modem Control Register (U1MCR - address 0xE001 0010) bit description Symbol RTSen CTSen 4.9 Auto-flow control If auto-RTS mode is enabled the UART1‘s receiver FIFO hardware controls the RTS1 output of the UART1. If the auto-CTS mode is enabled the UART1‘s U1TSR hardware will only start transmitting if the CTS1 input signal is asserted. -
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NXP Semiconductors 17.4.9.2 Auto-CTS The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled the transmitter circuitry in the U1TSR module checks CTS1 input before sending the next data byte. When CTS1 is active (low), the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS1 must be released before the middle of the last stop bit that is currently being sent. -
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NXP Semiconductors 4.10 UART1 Line Status Register (U1LSR - 0xE001 0014, Read Only) The U1LSR is a read-only register that provides status information on the UART1 TX and RX blocks. Table 408: UART1 Line Status Register (U1LSR - address 0xE001 0014, Read Only) bit... -
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NXP Semiconductors Table 408: UART1 Line Status Register (U1LSR - address 0xE001 0014, Read Only) bit Bit Symbol Transmitte r Holding Register Empty (THRE) Transmitte r Empty (TEMT) Error in RX FIFO (RXFE) 4.11 UART1 Modem Status Register (U1MSR - 0xE001 0018) The U1MSR is a read-only register that provides status information on the modem input signals. -
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NXP Semiconductors Table 409: UART1 Modem Status Register (U1MSR - address 0xE001 0018) bit description Bit Symbol Value Description 4.12 UART1 Scratch Pad Register (U1SCR - 0xE001 001C) The U1SCR has no effect on the UART1 operation. This register can be written and/or read at user’s discretion. -
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NXP Semiconductors Table 411: Auto-baud Control Register (U1ACR - address 0xE001 0020) bit description Symbol ABTOIntClr 31:10 - 4.14 Auto-baud The UART1 auto-baud function can be used to measure the incoming baud-rate based on the ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers U1DLM and U1DLL accordingly. -
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NXP Semiconductors ratemin 4.15 Auto-baud modes When the software is expecting an ”AT" command, it configures the UART1 with the expected character format and sets the U1ACR Start bit. The initial values in the divisor latches U1DLM and U1DLM don‘t care. Because of the ”A" or ”a" ASCII coding (”A"... -
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NXP Semiconductors start UARTn RX U0ACR start rate counter 16xbaud_rate 16 cycles a. Mode 0 (start bit and LSB are used for auto-baud) start UARTn RX U1ACR start rate counter 16xbaud_rate 16 cycles b. Mode 1 (only start bit is used for auto-baud) Fig 70. -
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NXP Semiconductors Table 412: UART1 Fractional Divider Register (U1FDR - address 0xE001 0028) bit description Function DIVADDVAL MULVAL 31:8 - This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART1 disabled making sure that UART1 is fully software and hardware compatible with UARTs not equipped with this feature. -
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NXP Semiconductors Pick another FR the range [1.1, 1.9] Fig 71. Algorithm for setting UART dividers UM10237_2 User manual Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an integer? = 1.5 from... -
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NXP Semiconductors Table 413. Fractional Divider setting look-up table DivAddVal/ MulVal 1.000 1.067 1/15 1.071 1/14 1.077 1/13 1.083 1/12 1.091 1/11 1.100 1/10 1.111 1.125 1.133 2/15 1.143 1.154 2/13 1.167 1.182 2/11 1.200 1.214 3/14 1.222 1.231 3/13 4.16.1.1 Example 1: PCLK = 14.7456 MHz, BR = 9600... -
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NXP Semiconductors Although Table 17–414 control, it is strongly suggested to let UART1 hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control. LPC2400’s U1TER enables implementation of software and hardware flow control. When TXEn=1, UART1 transmitter will keep sending data as long as they are available. -
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NXP Semiconductors Status information from the U1TX and U1RX is stored in the U1LSR. Control information for the U1TX and U1RX is stored in the U1LCR. U1INTR PA[2:0] PSEL PSTB PWRITE PD[7:0] PCLK Fig 72. UART1 block diagram UM10237_2 User manual... -
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UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 Rev. 02 — 19 December 2008 1. How to read this chapter The CAN controller in available on parts LPC2458 and LPC2460/68/70/78. 2. Basic configuration The CAN1/2 peripherals are configured using the following registers: 1. -
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NXP Semiconductors 4. Features 4.1 General CAN features • Compatible with CAN specification 2.0B, ISO 11898-1. • Multi-master architecture with non destructive bit-wise arbitration. • Bus access priority determined by the message identifier (11-bit or 29-bit). • Guaranteed latency time for high priority messages. -
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NXP Semiconductors 6. CAN controller architecture The CAN Controller is a complete serial interface with both Transmit and Receive Buffers but without Acceptance Filter. CAN Identifier filtering is done for all CAN channels in a separate block (Acceptance Filter). Except for message buffering and acceptance filtering the functionality is similar to the PeliCAN concept. -
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NXP Semiconductors 6.3 Transmit Buffers (TXB) The TXB represents a Triple Transmit Buffer, which is the interface between the Interface Management Logic (IML) and the Bit Stream Processor (BSP). Each Transmit Buffer is able to store a complete message which can be transmitted over the CAN network. This buffer is written by the CPU and read out by the BSP. -
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NXP Semiconductors 24 23 Frame info unused unused RX Data 4 RX Data 3 RX Data 8 RX Data 7 24 23 Frame info unused ID.28 unused RX Data 4 RX Data 3 RX Data 8 RX Data 7 Fig 75. Receive buffer layout for standard and extended frame format configurations 6.5 Error Management Logic (EML) -
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NXP Semiconductors Both self-tests are using the ‘Self Reception’ feature of the CAN Controller. With the Self Reception Request, the transmitted message is also received and stored in the receive buffer. Therefore the acceptance filter has to be configured accordingly. As soon as the CAN message is transmitted, a transmit and a receive interrupt are generated, if enabled. -
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NXP Semiconductors 7. Memory map of the CAN block The CAN Controllers and Acceptance Filter occupy a number of APB slots, as follows: Table 416. Memory map of the CAN block Address Range 0xE003 8000 - 0xE003 87FF 0xE003 C000 - 0xE003 C017... -
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NXP Semiconductors Table 418. Summary of CAN1 and CAN2 controller registers Generic Description Name Error Warning Limit Status Register Receive frame status Received Identifier Received data bytes 1-4 Received data bytes 5-8 TFI1 Transmit frame info (Tx Buffer 1) TID1... -
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NXP Semiconductors Table 419. Access to CAN1 and CAN2 controller registers Generic Operating Mode Name Read Interrupt Enable Bus Timing Error Warning Limit Status Rx Info and Index Rx Identifier Rx Data Rx Info and Index TFI1 Tx Info1 TID1... -
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NXP Semiconductors Table 420. Mode register (CAN1MOD - address 0xE004 4000, CAN2MOD - address 0xE004 8000) bit description Bit Symbol Value Function [3][6] Self Test Mode. 0(normal) A transmitted message must be acknowledged to be considered successful. 1(self test) The controller will consider a Tx message successful even if there is no acknowledgment received. -
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NXP Semiconductors Table 421. Command Register (CAN1CMR - address 0xE004 4004, CAN2CMR - address 0xE004 8004) bit description Symbol Value [1][2] 0 (absent) 1 (present) [1][3] 0 (no action) 1 (present) 0 (no action) 1 (released) 0 (no action) 1 (clear) -
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NXP Semiconductors If the Transmission Request or the Self-Reception Request bit was set '1' in a previous command, it cannot be cancelled by resetting the bits. The requested transmission may only be cancelled by setting the Abort Transmission bit. The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission, e.g. to transmit a more urgent message before. -
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NXP Semiconductors Table 422. Global Status Register (CAN1GSR - address 0xE004 4008, CAN2GSR - address 0xE004 8008) bit description Symbol Value Function Receive Status. 0 (idle) The CAN controller is idle. 1 (receive) The CAN controller is receiving a message. -
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NXP Semiconductors RX Error Counter = (CANxGSR AND 0x00FF0000) / 0x00010000 Note that a CPU-forced content change of the RX Error Counter is possible only if the Reset Mode was entered previously. An Error Status change (Status Register), an Error Warning or an Error Passive Interrupt forced by the new register content will not occur until the Reset Mode is cancelled again. -
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NXP Semiconductors Bits 24-31 are captured when CAN arbitration is lost. At the same time, if the ALIE bit in CANIER is 1, the ALI bit in this register is set, and a CAN interrupt can occur. Once either of these bytes is captured, its value will remain the same until it is read, at which time it is released to capture a new value. -
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NXP Semiconductors Table 423. Interrupt and Capture Register (CAN1ICR - address 0xE004 400C, CAN2ICR - Symbol 15:11 - UM10237_2 User manual Chapter 18: LPC24XX CAN controllers CAN1/2 address 0xE004 800C) bit description Value Function 0 (reset) ID Ready Interrupt -- this bit is set if the IDIE bit in... -
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NXP Semiconductors Table 423. Interrupt and Capture Register (CAN1ICR - address 0xE004 400C, CAN2ICR - Symbol 20:16 ERRBIT ERRDIR 23:22 ERRC1:0 UM10237_2 User manual Chapter 18: LPC24XX CAN controllers CAN1/2 address 0xE004 800C) bit description Value Function Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. -
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NXP Semiconductors Table 423. Interrupt and Capture Register (CAN1ICR - address 0xE004 400C, CAN2ICR - Symbol 31:24 ALCBIT The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command “Release Receive Buffer” will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. -
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NXP Semiconductors Table 424. Interrupt Enable Register (CAN1IER - address 0xE004 4010, CAN2IER - address Symbol Function TIE1 DOIE WUIE EPIE ALIE BEIE IDIE TIE2 TIE3 31:11 8.6 Bus Timing Register (CAN1BTR - 0xE004 4014, CAN2BTR - 0xE004 8014) This register controls how various CAN timings are derived from the APB clock. It defines the values of the Baud Rate Prescaler (BRP) and the Synchronization Jump Width (SJW). -
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NXP Semiconductors Table 425. Bus Timing Register (CAN1BTR - address 0xE004 4014, CAN2BTR - address Symbol Value Function 13:10 - 15:14 SJW 19:16 TESG1 22:20 TESG2 31:24 - Baud rate prescaler The period of the CAN system clock t bit timing. The CAN system clock t... -
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NXP Semiconductors 8.7 Error Warning Limit Register (CAN1EWL - 0xE004 4018, CAN2EWL - 0xE004 8018) This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read at any time but can only be written if the RM bit in CANmod is 1. The default value (after hardware reset) is 96. -
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NXP Semiconductors Table 427. Status Register (CAN1SR - address 0xE004 401C, CAN2SR - address 0xE004 801C) bit description Symbol Value Function Transmit Status 1. 0(idle) There is no transmission from Tx Buffer 1. 1(transmit) The CAN Controller is transmitting a message from Tx Buffer 1. -
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NXP Semiconductors Table 427. Status Register (CAN1SR - address 0xE004 401C, CAN2SR - address 0xE004 801C) bit description Symbol Value Function Error Status. This bit is identical to the ES bit in the CANxGSR. Bus Status. This bit is identical to the BS bit in the CANxGSR. -
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NXP Semiconductors 8.9.1 ID index field The ID Index is a 10-bit field in the Info Register that contains the table position of the ID Look-up Table if the currently received message was accepted. The software can use this index to simplify message transfers from the Receive Buffer into the Shared Message Memory. -
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NXP Semiconductors Table 431. Receive Data register A (CAN1RDA - address 0xE004 4028, CAN2RDA - address Symbol Function 15:8 Data 2 23:16 Data 3 31:24 Data 4 8.12 Receive Data Register B (CAN1RDB - 0xE004 402C, CAN2RDB - 0xE004 802C) This register contains the 5th through 8th Data bytes of the current received message. -
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NXP Semiconductors Table 433. Transmit Frame Information Register (CAN1TFI[1/2/3] - address Symbol Function PRIO 15:8 19:16 DLC 29:20 - Automatic transmit priority detection To allow uninterrupted streams of transmit messages, the CAN Controller provides Automatic Transmit Priority Detection for all Transmit Buffers. Depending on the selected Transmit Priority Mode, internal prioritization is based on the CAN Identifier or a user defined "local priority". -
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NXP Semiconductors 8.14 Transmit Identifier Register (CAN1TID[1/2/3] - 0xE004 40[34/44/54], CAN2TID[1/2/3] - 0xE004 80[34/44/54]) When the corresponding TBS bit in CANxSR is 1, software can write to one of these registers to define the Identifier field of the next transmit message. Bits not listed read as 0 and should be written as 0. -
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NXP Semiconductors 8.16 Transmit Data Register B (CAN1TDB[1/2/3] - 0xE004 40[3C/4C/5C], CAN2TDB[1/2/3] - 0xE004 80[3C/4C/5C]) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the 5th through 8th data bytes of the next transmit message. The Data Length Code defines the number of transferred data bytes. -
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NXP Semiconductors The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b) software clearing SM in the CAN Mode register. A sleeping CAN Controller, that wakes up in response to bus activity, is not able to receive an initial message, until after it detects Bus_Free (11 consecutive recessive bits). -
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NXP Semiconductors Table 438. Central Transit Status Register (CANTxSR - address 0xE004 0000) bit description Symbol 15:10 - TCS1 17:16 TCS2 31:18 - 10.2 Central Receive Status Register (CANRxSR - 0xE004 0004) Table 439. Central Receive Status Register (CANRxSR - address 0xE004 0004) bit... -
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NXP Semiconductors Table 440. Central Miscellaneous Status Register (CANMSR - address 0xE004 0008) bit Symbol Description 31:10 - 11. Global acceptance filter This block provides lookup for received Identifiers (called Acceptance Filtering in CAN terminology) for all the CAN Controllers. It includes a 512 × 32 (2 kB) RAM in which software maintains one to five tables of Identifiers. -
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NXP Semiconductors 12.2 Acceptance filter Bypass mode The Acceptance Filter Bypass Mode can be used for example to change the acceptance filter configuration during a running system, e.g. change of identifiers in the ID-Look-up Table memory. During this re-configuration, software acceptance filtering has to be used. -
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NXP Semiconductors If Standard (11 bit) Identifiers are used in the application, at least one of 3 tables in Acceptance Filter RAM must not be empty. If the optional “fullCAN mode” is enabled, the first table contains Standard identifiers for which reception is to be handled in this mode. -
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NXP Semiconductors The table of ranges of Extended Identifiers must contain an even number of entries, of the same form as in the individual Extended Identifier table. Like the Individual Extended table, the Extended Range must be arranged in ascending numerical order. The first and second (3rd and 4th …) entries in the table are implicitly paired as an inclusive range of... -
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NXP Semiconductors Table 443. Acceptance Filter Mode Register (AFMR - address 0xE003 C000) bit description Symbol AccOff AccBP eFCAN 31:3 - Acceptance Filter Bypass Mode (AccBP): By setting the AccBP bit in the Acceptance Filter Mode Register, the Acceptance filter is put into the Acceptance Filter Bypass mode. During bypass mode, the internal state machine of the Acceptance Filter is reset and halted. -
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NXP Semiconductors 15.3 Standard Frame Individual Start Address Register (SFF_sa - 0xE003 C004) Table 444. Standard Frame Individual Start Address Register (SFF_sa - address Symbol 10:2 SFF_sa 31:11 - Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. -
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NXP Semiconductors 15.5 Extended Frame Start Address Register (EFF_sa - 0xE003 C00C) Table 446. Extended Frame Start Address Register (EFF_sa - address 0xE003 C00C) bit Symbol 10:2 EFF_sa 31:11 - Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. -
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NXP Semiconductors 15.7 End of AF Tables Register (ENDofTable - 0xE003 C014) Table 448. End of AF Tables Register (ENDofTable - address 0xE003 C014) bit description Symbol 11:2 EndofTable 31:12 - Write access to the look-up table section configuration registers are possible only during the Acceptance filter bypass mode or the Acceptance filter off mode. -
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NXP Semiconductors 15.10 LUT Error Register (LUTerr - 0xE003 C01C) Table 450. LUT Error Register (LUTerr - address 0xE003 C01C) bit description Symbol Description LUTerr 31:1 15.11 Global FullCANInterrupt Enable register (FCANIE - 0xE003 C020) A write access to the Global FullCAN Interrupt Enable register is only possible when the Acceptance Filter is in the off mode. -
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NXP Semiconductors 16. Configuration and search algorithm The CAN Identifier Look-up Table Memory can contain explicit identifiers and groups of CAN identifiers for Standard and Extended CAN Frame Formats. They are organized as a sorted list or table with an increasing order of the Source CAN Channel (SCC) together with CAN Identifier in each section. -
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NXP Semiconductors Message disable bit Index 0, 1 SCC = 1 Index 2, 3 SCC = 2 Index 4, 5 SCC = 4 Index 6, 7 SCC = 6 Index 8, 9 SCC = 1 Index 10, 11 SCC = 2... -
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NXP Semiconductors receive interrupt whenever a CAN message is accepted and received. Software has to move the received message out of the receive buffer from the according CAN controller into the user RAM. To cover dashboard like applications where the controller typically receives data from several CAN channels for further processing, the CAN Gateway block was extended by a so-called FullCAN receive function. -
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NXP Semiconductors 17.1 FullCAN message layout Table 454. Format of automatically stored Rx messages Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0000 [1:0]... -
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NXP Semiconductors clear SEM, write back 1 st word read 2nd and 3rd words most recently read 1 st, 2nd, and 3rd words are from the same Fig 82. Semaphore procedure for reading an auto-stored message UM10237_2 User manual Chapter 18: LPC24XX CAN controllers CAN1/2... -
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NXP Semiconductors 17.2 FullCAN interrupts The CAN Gateway Block contains a 2 kB ID Look-up Table RAM. With this size a maximum number of 146 FullCAN objects can be defined if the whole Look-up Table RAM is used for FullCAN objects only. Only the first 64 FullCAN objects can be configured to participate in the interrupt scheme. -
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NXP Semiconductors Message disable bit Index 0, 1 Index 2, 3 Index 4, 5 Index 6, 7 New: FullCAN Message Interrupt enable bit Fig 83. FullCAN section example of the ID look-up table 17.2.2 Message lost bit and CAN channel number Figure 18–84... -
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NXP Semiconductors 17.2.3 Setting the interrupt pending bits (IntPnd 63 to 0) The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN message and if the interrupt of the according FullCAN Object is enabled (enable bit FCANIntxEn) is set). -
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NXP Semiconductors semaphore bits IntPndx look-up table access MsgLostx Fig 85. Normal case, no messages lost 17.3.2 Scenario 2: Message lost In this scenario a first FullCAN Message is stored and read out by Software (1 write and read). In a second course a second message is stored (2 read out before a third message gets stored (3 of that Object (IntPndx) is already asserted, the Message Lost Signal gets asserted. -
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NXP Semiconductors 17.3.3 Scenario 3: Message gets overwritten indicated by Semaphore bits This scenario is a special case in which the lost message is indicated by the existing semaphore bits. The scenario is entered, if during a Software read of a message object another new message gets stored by the message handler. -
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NXP Semiconductors semaphore bits IntPndx write write write write look-up table access 1st Object write MsgLostx Fig 88. Message overwritten indicated by semaphore bits and message lost 17.3.5 Scenario 3.2: Message gets overwritten indicated by Message Lost This scenario is a sub-case to Scenario 3 in which the lost message is indicated by Message Lost. -
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NXP Semiconductors semaphore bits IntPndx look-up write write write write table access 1st Object write MsgLostx Fig 89. Message overwritten indicated by message lost 17.3.6 Scenario 4: Clearing Message Lost bit This scenario is a special case in which the lost message bit of an object gets set during... -
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NXP Semiconductors semaphore bits IntPndx write write write look-up table access 1st Object write MsgLostx Fig 90. Clearing message lost 18. Examples of acceptance filter tables and ID index values 18.1 Example 1: only one section is used SFF_sa SFF_GRP_sa <... -
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NXP Semiconductors In cases where explicit identifiers as well as groups of the identifiers are programmed, a CAN identifier search has to start in the explicit identifier section first. If no match is found, it continues the search in the group of identifier section. By this order it can be guaranteed... -
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NXP Semiconductors 000 d := 000 h := 0 0000 0000 b SFF_sa APB base + address 00d = 00h 04d = 04h 44d = 2Ch 48d = 30h 52d = 34h SFF_GRP_sa 52 d := 034 h := 0 0011 0100 b... -
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NXP Semiconductors Table 457. Used ID-Look-up Table sections ID-Look-up Table Section FullCAN Explicit Standard Frame Format Group of Standard Frame Format Explicit Extended Frame Format Group of Extended Frame Format Explicit standard frame format identifier section (11-bit CAN ID): The start address of the Explicit Standard Frame Format section is defined in the SFF_sa register with the value of 0x00. -
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NXP Semiconductors Message disable bit SFF_sa = 0x00 Explicit Standard Frame Format Identifier Section SFF_GRP_sa = 0x10 Group of Standard Frame Format Identifier Section EFF_sa = 0x20 Explicit Extended Frame Format Identifier Section EFF_GRP_sa = 0x30 Group of Extended Frame... -
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NXP Semiconductors FullCAN explicit standard frame format identfier section (11-bit CAN ID) The start address of the FullCAN Explicit Standard Frame Format Identifier section is (automatically) set to 0x00. The end of this section is defined in the SFF_sa register. In the FullCAN ID section only identifiers of FullCAN Object are stored for acceptance filtering. -
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NXP Semiconductors Message Disable bit FullCAN Explicit Standard Frame Format Identifier Section SFF_sa = 0x10 Explicit Standard Frame Format Identifier Section ENDofTable = SFF_GRP_sa = EFF_sa = FullCAN EFF_GRP_sa = Message 0x20 Object section Section Fig 93. ID Look-up table configuration example (FullCAN activated and enabled) 18.8 Look-up table programming guidelines... -
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NXP Semiconductors • Each section has to be organized as a sorted list or table with an increasing order of the Source CAN Channel (SCC) in conjunction with the CAN Identifier (there is no exception for disabled identifiers). • The upper and lower bound in a Group of Identifiers definition has to be from the same Source CAN Channel. -
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UM10237 Chapter 19: LPC24XX SPI Rev. 02 — 19 December 2008 1. Basic configuration The SPI is configured using the following registers: 1. Power: In the PCONP register Remark: On reset, the SPI is enabled (PCSPI = 1). 2. Clock: In PCLK_SEL0 select PCLK_SPI (see must be scaled down (see 3. -
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NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) SSEL CPHA = 0 Cycle # CPHA = 0 BIT 1 MOSI (CPHA = 0) BIT 1 MISO (CPHA = 0) CPHA = 1 Cycle # CPHA = 1 MOSI (CPHA = 1) MISO (CPHA = 1) Fig 94. -
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NXP Semiconductors When a device is a slave and CPHA is set to 0, the transfer starts when the SSEL signal goes active, and ends when SSEL goes inactive. When a device is a slave, and CPHA is set to 1, the transfer starts on the first clock edge when the slave is selected, and ends on the last clock edge where data is sampled. -
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NXP Semiconductors 5. Read the SPI status register. 6. Read the received data from the SPI data register (optional). 7. Go to step 3 if more data is required to transmit. Note: A read or write of the SPI data register is required in order to clear the SPIF status bit. -
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NXP Semiconductors If the SSEL signal goes active, when the SPI block is a master, this indicates another master has selected the device to be a slave. This condition is known as a mode fault. When a mode fault is detected, the mode fault (MODF) bit in the status register will be activated, the SPI signal drivers will be de-activated, and the SPI mode will be changed to be a slave. -
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NXP Semiconductors 7. Register description The SPI contains 5 registers as shown in and word accessible. Table 461. SPI register map Name S0SPCR S0SPSR S0SPDR S0SPCCR SPI Clock Counter Register. This register S0SPINT Reset Value reflects the data stored in used bits only. It does not include reserved bits content. -
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NXP Semiconductors Table 462: SPI Control Register (S0SPCR - address 0xE002 0000) bit description Symbol MSTR LSBF SPIE 11:8 BITS 15:12 7.2 SPI Status Register (S0SPSR - 0xE002 0004) The S0SPSR register controls the operation of the SPI0 as per the configuration bits setting. -
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NXP Semiconductors Table 463: SPI Status Register (S0SPSR - address 0xE002 0004) bit description Symbol ROVR WCOL SPIF 7.3 SPI Data Register (S0SPDR - 0xE002 0008) This bi-directional data register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI by writing to this register. Data received by the SPI can be read from this register. -
Page 534: Spi Test Status Register (Sptsr - 0Xe)
NXP Semiconductors Table 466: SPI Test Control Register (SPTCR - address 0xE002 0010) bit description Symbol Test 7.6 SPI Test Status Register (SPTSR - 0xE002 0014) Note: The bits in this register are intended for functional verification only. This register should not be used for normal operation. -
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NXP Semiconductors SPI Interrupt SPI REGISTER INTERFACE APB Bus Fig 95. SPI block diagram UM10237_2 User manual SPI SHIFT REGISTER SPI CLOCK GENERATOR & DETECTOR SPI STATE CONTROL OUTPUT ENABLE LOGIC Rev. 02 — 19 December 2008 UM10237 Chapter 19: LPC24XX SPI... -
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UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 Rev. 02 — 19 December 2008 1. Basic configuration The SSP0/1 interfaces are configured using the following registers: 1. Power: In the PCONP register Remark: On reset, both SSP interfaces are enabled (PCSSP0/1 = 1). 2. -
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NXP Semiconductors 4. Pin descriptions Table 469. SSP pin descriptions Type Name SCK0/1 SSEL0/1 I/O MISO0/1 I/O MOSI0/1 I/O 5. Bus description 5.1 Texas Instruments synchronous serial frame format Figure 20–96 supported by the SSP module. UM10237_2 User manual Chapter 20: LPC24XX SSP interface SSP0/1... -
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NXP Semiconductors DX/DR a. Single frame transfer DX/DR b. Continuous/back-to-back frames transfer Fig 96. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two Frames Transfer For device configured as a master in this mode, CLK and FS are forced LOW, and the transmit data line DX is tristated whenever the SSP is idle. -
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NXP Semiconductors The CPHA control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the CPHA phase control bit is LOW, data is captured on the first clock edge transition. -
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NXP Semiconductors In the case of a single word transmission, after all bits of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. -
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NXP Semiconductors SSEL MOSI MISO a. Single transfer with CPOL=1 and CPHA=0 SSEL MOSI MISO 4 to 16 bits b. Continuous transfer with CPOL=1 and CPHA=0 Fig 99. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer) In this configuration, during idle periods: •... -
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NXP Semiconductors 5.2.5 SPI format with CPOL = 1,CPHA = 1 The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in Figure 20–100, which covers both single and continuous transfers. Fig 100. SPI Frame Format with CPOL = 1 and CPHA = 1 In this configuration, during idle periods: •... -
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NXP Semiconductors Fig 101. Microwire frame format (single transfer) Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8 bit control word that is transmitted from the SSP to the off-chip slave device. -
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NXP Semiconductors Fig 102. Microwire frame format (continuos transfers) 5.3.1 Setup and hold time requirements on CS with respect to SK in Microwire mode In the Microwire mode, the SSP slave samples the first bit of receive data on the rising edge of SK after CS has gone LOW. -
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NXP Semiconductors Table 470. SSP Register Map Generic Name Description Control Register 0. Selects the serial clock rate, bus type, and data size. Control Register 1. Selects master/slave and other modes. Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. -
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NXP Semiconductors Table 471: SSPn Control Register 0 (SSP0CR0 - address 0xE006 8000, SSP1CR0 - Symbol Value CPOL CPHA 15:8 6.2 SSPn Control Register 1 (SSP0CR1 - 0xE006 8004, SSP1CR1 - 0xE003 0004) This register controls certain aspects of the operation of the SSP controller. -
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NXP Semiconductors Table 472: SSPn Control Register 1 (SSP0CR1 - address 0xE006 8004, SSP1CR1 - Symbol 6.3 SSPn Data Register (SSP0DR - 0xE006 8008, SSP1DR - 0xE003 0008) Software can write data to be transmitted to this register, and read data that has been received. -
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NXP Semiconductors 6.4 SSPn Status Register (SSP0SR - 0xE006 800C, SSP1SR - 0xE003 000C) This read-only register reflects the current status of the SSP controller. Table 474: SSPn Status Register (SSP0SR - address 0xE006 800C, SSP1SR - 0xE003 000C) Symbol 6.5 SSPn Clock Prescale Register (SSP0CPSR - 0xE006 8010, SSP1CPSR... -
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NXP Semiconductors Table 476: SSPn Interrupt Mask Set/Clear register (SSP0IMSC - address 0xE006 8014, Symbol RORIM RTIM RXIM TXIM 6.7 SSPn Raw Interrupt Status Register (SSP0RIS - 0xE006 8018, SSP1RIS - 0xE003 0018) This read-only register contains a 1 for each interrupt condition that is asserted, regardless of whether or not the interrupt is enabled in the SSPnIMSC. -
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NXP Semiconductors Table 478: SSPn Masked Interrupt Status register (SSPnMIS -address 0xE006 801C, Symbol RORMIS RTMIS RXMIS TXMIS 6.9 SSPn Interrupt Clear Register (SSP0ICR - 0xE006 8020, SSP1ICR - 0xE003 0020) Software can write one or more one(s) to this write-only register, to clear the corresponding interrupt condition(s) in the SSP controller. -
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UM10237 Chapter 21: LPC24XX SD/MMC card interface Rev. 02 — 19 December 2008 1. Basic configuration The SD/MMC is configured using the following registers: 1. Power: In the PCONP register Remark: On reset, the SD/MMC is disabled (PCMCI = 0). 2. -
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NXP Semiconductors There is one additional signal needed in the interface, a power control line MCIPWR, but it can be sourced from any GPIO signal. 5. Functional overview The MCI may be used as a multimedia card bus host (see card”) or a secure digital memory card bus host (see... -
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NXP Semiconductors Fig 105. Secure digital memory card connection 5.2.1 Secure digital memory card bus signals The following signals are used on the secure digital memory card bus: • CLK Host to card clock signal • CMD Bidirectional command/response signal •... -
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NXP Semiconductors 5.3.1 Adapter register block The adapter register block contains all system registers. This block also generates the signals that clear the static flags in the multimedia card. The clear signals are generated when 1 is written into the corresponding bit location of the MCIClear register. -
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NXP Semiconductors Enabled and Pending command Disabled PEND LastData Fig 107. Command path state machine When the WAIT state is entered, the command timer starts running. If the timeout reached before the CPSM moves to the RECEIVE state, the timeout flag is set and the IDLE state is entered. -
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NXP Semiconductors 5.3.5 Command format The command path operates in a half-duplex mode, so that commands and responses can either be sent or received. If the CPSM is not in the SEND state, the MCICMD output is in HI-Z state, as shown in MCICLK edge. -
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NXP Semiconductors Table 485. Command path status flags Flag CmdRespEnd CmdCrcFail CmdSent CmdTimeOut CmdActive The CRC generator calculates the CRC checksum for all bits before the CRC code. This includes the start bit, transmitter bit, command index, and command argument (or card status). -
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NXP Semiconductors Disabled or FIFO underrun or end of data or CRC fail BUSY End of packet SEND Fig 109. Data path state machine • IDLE: The data path is inactive, and the MCIDAT[3:0] outputs are in HI-Z. When the... -
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NXP Semiconductors Note: The DPSM remains in the WAIT_S state for at least two clock periods to meet Nwr timing constraints. • SEND: The DPSM starts sending data to a card. Depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream: –... -
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NXP Semiconductors MCICLK MCICMD cmd state MCIDAT0 data counter CmdPend Fig 110. Pending command start The data block counter determines the end of a data block. If the counter is zero, the end-of-data condition is TRUE (see 0xE008 C02C)” 5.3.9 Bus mode In wide bus mode, all four data signals (MCIDAT[3:0]) are used to transfer data, and the CRC code is calculated separately for each data signal. -
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NXP Semiconductors 5.3.11 Status flags Table 21–487 (MCIStatus - 0xE008 C034)” on page 569 Table 487. Data path status flags Flag TxFifoFull TxFifoEmpty TxFifoHalfEmpty TxDataAvlbl TxUnderrun RxFifoFull RxFifoEmpty RxFifoHalfFull RxDataAvlbl RxOverrun DataBlockEnd StartBitErr DataCrcFail DataEnd DataTimeOut TxActive RxActive 5.3.12 CRC generator The CRC generator calculates the CRC checksum only for the data bits in a single block, and is bypassed in data stream mode. -
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NXP Semiconductors • The receive FIFO refers to the receive logic and data buffer when RxActive is asserted (see 5.3.14 Transmit FIFO Data can be written to the transmit FIFO through the APB interface once the MCI is enabled for transmission. -
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NXP Semiconductors Table 489. Receive FIFO status flags Symbol RxFifoFull RxFifoEmpty RxHalfFull RxDataAvlbl RxOverrun 5.3.16 APB interfaces The APB interface generates the interrupt and DMA requests, and accesses the MCI adapter registers and the data FIFO. It consists of a data path, register decoder, and interrupt/DMA logic. -
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NXP Semiconductors Table 490. Summary of MCI registers Name MCIMask0 MCIFifoCnt MCIFIFO Reset Value reflects the data stored in used bits only. It does not include reserved bits content. 6.1 Power Control Register (MCI Power - 0xE008 C000) The MCIPower register controls an external power supply. Power can be switched on and off, and adjust the output voltage. -
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NXP Semiconductors Table 492: Clock Control register (MCIClock - address 0xE008 C004) bit description Symbol ClkDiv Enable PwrSave Bypass WideBus 31:12 While the MCI is in identification mode, the MCICLK frequency must be less than 400 kHz. The clock frequency can be changed to the maximum card bus frequency when relative card addresses are assigned to all cards. -
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NXP Semiconductors Table 494: Command register (MCICommand - address 0xE008 C00C) bit description Symbol CmdIndex Command index. Response If set, CPSM waits for a response. LongRsp Interrupt Pending Enable 31:11 Note: After a data write, data cannot be written to this register for three MCLK clock periods plus two PCLK clock periods. -
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NXP Semiconductors Table 497: Response registers (MCIResponse0-3 - addresses 0xE008 0014, 0xE008 C018, Symbol 31:0 Status The card status size can be 32 or 127 bits, depending on the response type (see Table 21–498). Table 498: Response Register Type Description... -
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NXP Semiconductors 6.9 Data Control Register (MCIDataCtrl - 0xE008 C02C) The MCIDataCtrl register controls the DPSM. the MCIDataCtrl register. Table 501: Data Control register (MCIDataCtrl - address 0xE008 C02C) bit description Symbol Enable Direction Mode DMAEnable BlockSize 31:8 - Note: After a data write, data cannot be written to this register for three MCLK clock periods plus two PCLK clock periods. -
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NXP Semiconductors Table 503: Data Counter register (MCIDataCnt - address 0xE008 C030) bit description Symbol 15:0 DataCount Remaining data 31:16 Note: This register should be read only when the data transfer is complete. 6.11 Status Register (MCIStatus - 0xE008 C034) The MCIStatus register is a read-only register. -
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NXP Semiconductors Table 504: Status register (MCIStatus - address 0xE008 C034) bit description Symbol TxDataAvlbl RxDataAvlbl 31:22 6.12 Clear Register (MCIClear - 0xE008 C038) The MCIClear register is a write-only register. The corresponding static status flags can be cleared by writing a 1 to the corresponding bit in the register. -
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NXP Semiconductors Table 506: Interrupt Mask registers (MCIMask0 - address 0xE008 C03C) bit description Symbol Mask8 Mask9 Mask10 Mask11 Mask12 Mask13 Mask14 Mask15 Mask16 Mask17 Mask18 Mask19 Mask20 Mask21 31:22 6.14 FIFO Counter Register (MCIFifoCnt - 0xE008 C048) The MCIFifoCnt register contains the remaining number of words to be written to or read from the FIFO. -
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UM10237 Chapter 22: LPC24XX I Rev. 02 — 19 December 2008 1. Basic configuration The I C0/1/2 interfaces are configured using the following registers: 1. Power: In the PCONP register Remark: On reset, all I 2. Clock: In PCLK_SEL0 select PCLK_I2C0; in PCLK_SEL1 select PCLK_I2C1/2 (see Section 3. -
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NXP Semiconductors • Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. -
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NXP Semiconductors 5. Pin description Table 509. I SDA0,1, 2 SCL0,1, 2 6. I C operating modes In a given application, the I mode, the I one of these addresses is detected, an interrupt is requested. If the processor wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave operation is not interrupted. -
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NXP Semiconductors SLAVE ADDRESS from Master to Slave from Slave to Master Fig 112. Format in the Master Transmitter mode 6.2 Master Receiver mode In the master receiver mode, data is received from a slave transmitter. The transfer is initiated in the same way as in the master transmitter mode. When the START condition... -
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NXP Semiconductors From master to slave From slave to master Fig 114. A master receiver switch to master Transmitter after sending repeated START 6.3 Slave Receiver mode In the slave receiver mode, data bytes are received from a master transmitter. To initialize... -
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NXP Semiconductors 6.4 Slave Transmitter mode The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via SDA while the serial clock is input through SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. -
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NXP Semiconductors INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE I2CONSET I2CONCLR I2SCLH I2SCLL STATUS status DECODER Fig 117. I C Bus serial interface block diagram UM10237_2 User manual Chapter 22: LPC24XX I ADDRESS REGISTER I2ADR COMPARATOR SHIFT REGISTER BIT COUNTER/ ARBITRATION &... -
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NXP Semiconductors 7.2 Address Register I2ADDR This register may be loaded with the 7 bit slave address (7 most significant bits) to which the I C block will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable general call address (0x00) recognition. -
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NXP Semiconductors The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device. If two or more master devices generate clock pulses, the “mark” duration is determined by the device that generates the shortest “marks,” and the “space”... -
Page 581: Not Used
NXP Semiconductors The contents of the I will set bits in the I Conversely, writing to I2CONCLR will clear bits in the I to ones in the value written. 7.9 Status decoder and status register The status decoder takes all of the internal status bits and compresses them into a 5 bit code. -
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NXP Semiconductors Table 512. Summary of I C registers Generic Description Name I2SCLH SCH Duty Cycle Register High Half Word. Determines the high time of the I I2SCLL SCL Duty Cycle Register Low Half Word. Determines the low time of the I... -
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NXP Semiconductors When STA is 1 and the I checks the bus and generates a START condition if the bus is free. If the bus is not free, it waits for a STOP condition (which will free the bus) and generates a START condition after a delay of a half clock period of the internal clock generator. -
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NXP Semiconductors 8.2 I C Control Clear Register (I2C[0/1/2]CONCLR: 0xE001 C018, 0xE005 C018, 0xE008 0018) The I2CONCLR registers control clearing of bits in the I2CON register that controls operation of the I corresponding bit in the I Table 514. I... -
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NXP Semiconductors 8.4 I C Data Register (I2C[0/1/2]DAT - 0xE001 C008, 0xE005 C008, 0xE008 0008) This register contains the data to be transmitted or the data just received. The CPU can read and write to this register only while it is not in the process of shifting a byte, when the SI bit is set. -
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NXP Semiconductors The values for I2SCLL and I2SCLH should not necessarily be the same. Software can set different duty cycles on SCL by setting these two registers. For example, the I specification defines the SCL low time and high time at different values for a 400 kHz I rate. -
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NXP Semiconductors Table 521. Abbreviations used to describe an I Abbreviation Data In Figures numbers in the circles show the status code held in the I2STAT register. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. -
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NXP Semiconductors 9.2 Master Receiver mode In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure the start condition has been transmitted, the interrupt service routine must load I2DAT with the 7 bit slave address and the data direction bit (SLA+R). The SI bit in I2CON must then be cleared before the serial transfer can continue. -
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NXP Semiconductors If the AA bit is reset during a transfer, the I to SDA after the next received data byte. While AA is reset, the I respond to its own slave address or a general call address. However, the I monitored and address recognition may be resumed at any time by setting AA. -
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NXP Semiconductors successful transmission to a Slave Receiver next transfer started with a Repeated Start condition Acknowledge received after the Slave address Acknowledge received after a Data byte arbitration lost in Slave address or Data byte arbitration lost addressed as... -
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NXP Semiconductors successful transmission to a Slave transmitter next transfer started with a Repeated Start condition Not Acknowledge received after the Slave address arbitration lost in Slave address or Acknowledge bit arbitration lost and addressed as Slave from Master to Slave... -
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NXP Semiconductors reception of the own Slave address and one or more Data bytes all are acknowledged last data byte received is Not acknowledged arbitration lost as Master and addressed as Slave reception of the General Call address and one or more Data... -
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NXP Semiconductors reception of the own Slave address and one or more Data bytes all are acknowledged arbitration lost as Master and addressed as Slave last data byte transmitted. Switched to Not Addressed Slave (AA bit in I2CON = “0”) -
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NXP Semiconductors Table 525. Master Transmitter mode Status Status of the I C bus Application software response Code and hardware To/From I2DAT (I2CSTAT) 0x08 A START condition Load SLA+W has been transmitted. Clear STA 0x10 A repeated START Load SLA+W or... -
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NXP Semiconductors Table 526. Master Receiver mode Status Status of the I C bus Application software response Code and hardware To/From I2DAT (I2CSTAT) 0x08 A START condition Load SLA+R has been transmitted. 0x10 A repeated START Load SLA+R or condition has been Load SLA+W transmitted. -
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NXP Semiconductors Table 527. Slave Receiver Mode Status Status of the I C bus Application software response Code and hardware To/From I2DAT (I2CSTAT) 0x60 Own SLA+W has No I2DAT action been received; ACK has been returned. No I2DAT action 0x68... -
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NXP Semiconductors Table 527. Slave Receiver Mode Status Status of the I C bus Application software response Code and hardware To/From I2DAT (I2CSTAT) 0x98 Previously addressed Read data byte or 0 with General Call; DATA byte has been received; NOT ACK Read data byte or 0 has been returned. -
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NXP Semiconductors Table 528. Tad_105: Slave Transmitter mode Status Status of the I C bus Application software response Code and hardware To/From I2DAT (I2CSTAT) 0xA8 Own SLA+R has been Load data byte or received; ACK has been returned. Load data byte... -
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NXP Semiconductors 9.5 Miscellaneous states There are two I2STAT codes that do not correspond to a defined I Table 22–529). These are discussed below. 22.9.5.1 I2STAT = 0xF8 This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set. -
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NXP Semiconductors Table 529. Miscellaneous states Status Status of the I C bus Application software response Code and hardware To/From I2DAT (I2CSTAT) 0xF8 No relevant state No I2DAT action information available; SI = 0. 0x00 Bus error during MST No I2DAT action... -
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NXP Semiconductors If an uncontrolled source generates a superfluous START or masks a STOP condition, then the I C bus stays busy indefinitely. If the STA flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the I possible. -
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NXP Semiconductors STA flag STO flag SDA line SCL line Fig 125. Forced access to a busy I (1) Unsuccessful attempt to send a start condition. (2) SDA line is released. (3) Successful attempt to send a start condition. State 08H is entered. -
Page 603: Not Used
NXP Semiconductors The I C hardware now begins checking the I call. If the general call or the own slave address is detected, an interrupt is requested and I2STAT is loaded with the appropriate state information. 9.12.2 I C interrupt service When the I the 26 state services to be executed. -
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NXP Semiconductors 2. Set up the Slave Address to which data will be transmitted, and add the Read bit. 3. Write 0x20 to I2CONSET to set the STA bit. 4. Set up the Master Receive buffer. 5. Initialize the Master data counter to match the length of the message to be received. -
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NXP Semiconductors 4. Set up Master Transmit mode data buffer. 5. Set up Master Receive mode data buffer. 6. Initialize Master data counter. 7. Exit 10.7 Master Transmitter states 10.7.1 State : 0x18 Previous state was State 8 or State 10, Slave Address + Write has been transmitted, ACK has been received. -
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NXP Semiconductors 10.7.5 State : 0x38 Arbitration has been lost during Slave Address + Write or data. The bus has been released and not addressed Slave mode is entered. A new Start condition will be transmitted when the bus is free again. -
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NXP Semiconductors 1. Read data byte from I2DAT into Master Receive buffer. 2. Write 0x14 to I2CONSET to set the STO and AA bits. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Exit 10.9 Slave Receiver states 10.9.1 State : 0x60... -
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NXP Semiconductors 3. Set up Slave Receive mode data buffer. 4. Initialize Slave data counter. 5. Exit 10.9.5 State : 0x80 Previously addressed with own Slave Address. Data has been received and ACK has been returned. Additional data will be read. -
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NXP Semiconductors 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit 10.10 Slave Transmitter States 10.10.1 State : 0xA8 Own Slave Address + Read has been received, ACK has been returned. Data will be transmitted, ACK bit will be received. -
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NXP Semiconductors 3. Exit 10.10.5 State : 0xC8 The last data byte has been transmitted, ACK has been received. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. -
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UM10237 Chapter 23: LPC24XX I Rev. 02 — 19 December 2008 1. Basic configuration The I S interface is configured using the following registers: 1. Power: In the PCONP register Remark: On reset, the I 2. Clock: In PCLK_SEL1 select PCLK_I2S, see 3. -
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NXP Semiconductors next falling edge of the transmitting clock after a WS change. In stereo mode when WS is low left data is transmitted and right data when WS is high. In mono mode the same data is transmitted twice, once when WS is low and again when WS is high. -
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NXP Semiconductors SCK: serial clock TRANSMITTER WS: word select (MASTER) SD: serial data word n-1 right channel Fig 127. Simple I S configurations and bus timing 5. Register description Table 23–531 their functions. Following the table are details for each register. -
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NXP Semiconductors Table 531. Summary of I Name I2SIRQ I2STXRATE I2SRXRATE Receive bit rate divider. This register determines Reset Value reflects the data stored in used bits only. It does not include reserved bits content. 5.1 Digital Audio Output Register (I2SDAO - 0xE008 8000) -
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NXP Semiconductors Table 533: Digital Audio Input register (I2SDAI - address 0xE008 8004) bit description Symbol wordwidth mono stop reset ws_sel 14:6 ws_halfperiod Unused 5.3 Transmit FIFO Register (I2STXFIFO - 0xE008 8008) The I2STXFIFO register provides access to the transmit FIFO. The function of bits in... -
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NXP Semiconductors Table 536: Status Feedback register (I2SSTATE - address 0xE008 8010) bit description Symbol 15:8 rx_level 23:16 tx_level 31:24 - 5.6 DMA Configuration Register 1 (I2SDMA1 - 0xE008 8014) The I2SDMA1 register controls the operation of DMA request 1. The function of bits in I2SDMA1 are shown in chapter for details of DMA operation. -
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NXP Semiconductors Table 539: Interrupt Request Control register (I2SIRQ - address 0xE008 801C) bit description Symbol rx_Irq_enable tx_Irq_enable Unused 15:8 rx_depth_Irq 23:16 tx_depth_Irq 31:24 5.9 Transmit Clock Rate Register (I2STXRATE - 0xE008 8020) The bit rate for the I The value depends on the audio sample rate desired, and the data size and format (stereo/mono) used. -
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NXP Semiconductors • Data word length is determined by the wordwidth value in the configuration register. There is a separate wordwidth value for the receive channel and the transmit channel. – 0: word is considered to contain four 8 bits data words. -
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NXP Semiconductors Table 542. Conditions for FIFO level comparison Level Comparison dmareq_tx_1 dmareq_rx_1 dmareq_tx_2 dmareq_rx_2 irq_tx irq_rx System signaling occurs when a level detection is true and enabled. Table 543. DMA and interrupt request generation System Signaling dmareq[0] dmareq[1] Table 544. Status feedback in the I2SSTATE register... -
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NXP Semiconductors Mono 8-bit data mode N + 3 Stereo 8-bit data mode LEFT + 1 Mono 16-bit data mode N + 1 Stereo 16-bit data mode LEFT Mono 32-bit data mode Stereo 32-bit data mode Fig 128. FIFO contents for various I... -
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UM10237 Chapter 24: LPC24XX Timer0/1/2/3 Rev. 02 — 19 December 2008 1. Basic configuration The Timer0/1/2/3 peripherals are configured using the following registers: 1. Power: In the PCONP register Remark: On reset, Timer0/1 are enabled (PCTIM0/1 = 1), and Timer2/3 are disabled (PCTIM2/3 = 0). -
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NXP Semiconductors • Free running timer. 4. Description The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally-supplied clock, and can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. -
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NXP Semiconductors Table 546. Summary of timer/counter registers Generic Description Name Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. Timer Control Register. The TCR is used to control the Timer Counter functions. -
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NXP Semiconductors Table 546. Summary of timer/counter registers Generic Description Name Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn[0] (CAP0[0], CAP1[0], CAP2[0], CAP3[0]) inputs. Capture Register 1. CR1 is loaded with the... -
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NXP Semiconductors Table 548: Timer Control Register (TCR, TIMERn: TnTCR - addresses 0xE000 4004, Symbol Counter Enable When one, the Timer Counter and Prescale Counter are Counter Reset 6.3 Count Control Register (T[0/1/2/3]CTCR - 0xE000 4070, 0xE000 8070, 0xE007 0070, 0xE007 4070) The Count Control Register (CTCR) is used to select between Timer and Counter mode, and in Counter mode to select the pin and edge(s) for counting. -
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NXP Semiconductors Table 549: Count Control Register (T[0/1/2/3]CTCR - addresses 0xE000 4070, 0xE000 8070, Symbol Count Input Select 6.4 Timer Counter registers (T0TC - T3TC, 0xE000 4008, 0xE000 8008, 0xE007 0008, 0xE007 4008) The 32-bit Timer Counter register is incremented when the prescale counter reaches its terminal count. -
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NXP Semiconductors 6.8 Match Control Register (T[0/1/2/3]MCR - 0xE000 4014, 0xE000 8014, 0xE007 0014, 0xE007 4014) The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter. The function of each of the bits is shown Table 24–550. -
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NXP Semiconductors 6.9 Capture Registers (CR0 - CR3) Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin. The settings in the Capture Control Register register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges. -
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NXP Semiconductors 6.11 External Match Register (T[0/1/2/3]EMR - 0xE000 403C, 0xE000 803C, 0xE007 003C, 0xE007 403C) The External Match Register provides both control and status of the external match pins. In the descriptions below, “n” represents the Timer number, 0,1, 2, or 3, and “m” represent a Match number, 0 through 3. -
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NXP Semiconductors 7. Example timer operation Figure 24–129 match. The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle where the match occurs, the timer count is reset. This gives a full length cycle to the match value. -
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NXP Semiconductors Fig 131. Timer block diagram UM10237_2 User manual MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER CONTROL MAT[3:0] INTERRUPT CAP[3:0] STOP ON MATCH RESET ON MATCH... -
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UM10237 Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 Rev. 02 — 19 December 2008 1. Basic configuration The PWM is configured using the following registers: 1. Power: In the PCONP register Remark: On reset, the both PWMs are enabled (PCPWM0/1 = 1). 2. -
Page 633: Nxp B.v. 2008. All Rights Reserved
NXP Semiconductors 3. Description The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the microcontroller. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. -
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NXP Semiconductors SHADOW REGISTER 0 MATCH REGISTER 0 LOAD ENABLE MATCH REGISTER 1 SHADOW REGISTER 1 LOAD ENABLE SHADOW REGISTER 2 MATCH REGISTER 2 LOAD ENABLE MATCH REGISTER 3 SHADOW REGISTER 3 LOAD ENABLE MATCH REGISTER 4 SHADOW REGISTER 4... -
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NXP Semiconductors 3.1 Rules for single edge controlled PWM outputs 1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0. 2. Each PWM output will go low when its match value is reached. If no match occurs (i.e. -
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NXP Semiconductors 5. The maximum number of match registers is increased to 7 in order to allow support for up to 3 double edge PWM channels. This includes the necessary match outputs, control bits, etc. for each match register: – Three new Match registers are added, creating Match channels 4 through 6. -
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NXP Semiconductors Table 554. Set and reset inputs for PWM flip-flops PWM Channel Identical to single edge mode in this case since Match 0 is the neighboring match register. Essentially, PWM1 cannot be a double edged output. It is generally not advantageous to use PWM channels 3 and 5 for double edge PWM outputs because it would reduce the number of double edge PWM outputs that are possible. -
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NXP Semiconductors Table 557. PWM0 and PWM1 register map Generic Description Name Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. Timer Control Register. The TCR is used to control the Timer Counter functions. -
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NXP Semiconductors Table 557. PWM0 and PWM1 register map Generic Description Name Match Register 4. MR4 can be enabled in the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt when it matches the TC. In addition, a match between this value and the TC clears PWM4 in either edge mode, and sets PWM5 if it’s in double-edge mode. -
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NXP Semiconductors Table 558: PWM Interrupt Register (PWM0IR - address 0xE001 4000 and PWM1IR address Symbol PWMMR5 Interrupt Interrupt flag for PWM match channel 5. PWMMR6 Interrupt Interrupt flag for PWM match channel 6. 15:11 - 6.2 PWM Timer Control Register (PWM0TCR - 0xE001 4004 and... -
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NXP Semiconductors 6.3 PWM Count Control Register (PWM0CTCR - 0xE001 4070 and PWM1CTCR 0xE001 8070) The Count Control Register (CTCR) is used to select between Timer and Counter mode, and in Counter mode to select the pin and edge(s) for counting. The function of each of... -
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NXP Semiconductors Table 561: Match Control Register (PWM0MCR - address 0xE000 4014 and PWM1MCR - Symbol PWMMR1I PWMMR1R 1 PWMMR1S 1 PWMMR2I PWMMR2R 1 PWMMR2S 1 PWMMR3I PWMMR3R 1 PWMMR3S 1 PWMMR4I PWMMR4R 1 PWMMR4S 1 PWMMR5I UM10237_2 User manual... -
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NXP Semiconductors Table 561: Match Control Register (PWM0MCR - address 0xE000 4014 and PWM1MCR - Symbol PWMMR5R 1 PWMMR5S 1 PWMMR6I PWMMR6R 1 PWMMR6S 1 31:21 - 6.5 PWM Capture Control Register (PWM0CCR - 0xE001 4028 and PWM1CCR 0xE001 8028) -
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NXP Semiconductors Table 562: PWM Capture Control Register (PWM0CCR - address 0xE001 4028 and PWM1CCR Symbol Capture on PCAPn.1 rising edge Capture on PCAPn.1 falling edge Interrupt on PCAPn.1 event 31:6 - Reserved for PWM0. 6.6 PWM Control Registers (PWM0PCR - 0xE001 404C and PWM1PCR 0xE001 804C) The PWM Control registers are used to enable and select the type of each PWM channel. -
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NXP Semiconductors 6.7 PWM Latch Enable Register (PWM0LER - 0xE001 4050 and PWM1LER 0xE001 8050) The PWM Latch Enable registers are used to control the update of the PWM Match registers when they are used for PWM generation. When software writes to the location of a PWM Match register while the Timer is in PWM mode, the value is actually held in a shadow register and not used immediately. -
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NXP Semiconductors Table 564: PWM Latch Enable Register (PWM0LER - address 0xE001 4050 and PWM1LER Bit Symbol Enable PWM Match 5 Latch Enable PWM Match 6 Latch UM10237_2 User manual Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 address 0xE001 8050) bit description Description PWM MR5 register update control. -
Page 647: Battery Ram
UM10237 Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM Rev. 02 — 19 December 2008 1. Basic configuration The RTC is configured using the following registers: 1. Power: In the PCONP register Remark: On reset, the RTC is enabled. See 2. -
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NXP Semiconductors and resume operation. The alarm output has a nominal voltage swing of 1.8 V. Note that the PLL is disabled when waking up from power down. See start-up procedure. 4. Architecture CLOCK GENERATOR CLK1 TIME COUNTERS counter enables Fig 134. -
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NXP Semiconductors 6. Register description The RTC includes a number of registers. The address space is split into four sections by functionality. The first eight addresses are the Miscellaneous Register Group (Section 26–6.2). The second set of eight locations are the Time Counter Group (Section 26–6.4). -
Page 650: Interrupt Location Register (Ilr - 0Xe)
NXP Semiconductors Registers in the RTC other than those that are part of the Prescaler are not affected by chip Reset. These registers must be initialized by software if the RTC is enabled. Reset Value reflects the data stored in used bits only. -
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NXP Semiconductors Table 568. Interrupt Location Register (ILR - address 0xE002 4000) bit description Symbol RTCCIF RTCALF When one, the alarm registers generated an interrupt. Writing a one to RTSSF 6.2.2 Clock Tick Counter Register (CTCR - 0xE002 4004) The Clock Tick Counter is read only. It can be reset to zero through the Clock Control Register (CCR). -
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NXP Semiconductors Table 570. Clock Control Register (CCR - address 0xE002 4008) bit description Symbol CLKSRC 6.2.4 Counter Increment Interrupt Register (CIIR - 0xE002 400C) The Counter Increment Interrupt Register (CIIR) gives the ability to generate an interrupt every time a counter is incremented. This interrupt remains valid until cleared by writing a one to bit zero of the Interrupt Location Register (ILR[0]). -
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NXP Semiconductors Table 572. Counter Increment Select Mask register (CISS - address 0xE002 4040) bit description Bit Symbol Value Description 2:0 SubSecSel SubSecSelSub-Second Select. This field selects a count for the sub-second interrupt as follows: An interrupt is generated on every 16 counts of the Clock Tick Counter. At 32.768 kHz, this generates an interrupt approximately every 488 microseconds. -
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NXP Semiconductors 6.3 Consolidated time registers The values of the Time Counters can optionally be read in a consolidated format which allows the programmer to read all time counters with only three read operations. The various registers are packed into 32 bit values as shown in Table 26–576. -
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NXP Semiconductors Table 576. Consolidated Time register 2 (CTIME2 - address 0xE002 401C) bit description Symbol 11:0 Day of Year 31:12 6.4 Time Counter Group The time value consists of the eight counters shown in These counters can be read or written at the locations shown in Table 577. -
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NXP Semiconductors 7. Alarm register group The alarm registers are shown in compared with the time counters. If all the unmasked (See Register (AMR - 0xE002 4010)” on page time counters then an interrupt is generated. The interrupt is cleared when a one is written to bit one of the Interrupt Location Register (ILR[1]). -
Page 657: Reference Clock Divider (Prescaler)
NXP Semiconductors during system operation (by reconfiguring the PLL, the APB divider, or the RTC prescaler) will result in some form of accumulated time error. Accumulated time errors may occur in case RTC clock source is switched between the PCLK to the RTCX pins, too. -
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NXP Semiconductors PREINT = int (PCLK/32768) - 1. The value of PREINT must be greater than or equal to 1. Table 581: Prescaler Integer register (PREINT - address 0xE002 4080) bit description Symbol 12:0 Prescaler Integer Contains the integer portion of the RTC prescaler value. -
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NXP Semiconductors 13 BIT INTEGER COUNTER 13 BIT RELOAD INTEGER Fig 135. RTC prescaler block diagram 10.5 Prescaler operation The Prescaler block labelled "Combination Logic" in decrement of the 13 bit PREINT counter is extended by one PCLK. In order to both insert the correct number of longer cycles, and to distribute them evenly, the combinatorial Logic associates each bit in PREFRAC with a combination in the 15 bit Fraction Counter. -
Page 660: Battery Ram
NXP Semiconductors Table 583. Prescaler cases where the Integer Counter reload value is incremented Fraction Counter --- ---- ---- ---1 --- ---- ---- --10 --- ---- ---- -100 --- ---- ---- 1000 --- ---- ---1 0000 --- ---- --10 0000... -
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NXP Semiconductors Fig 136. RTC 32 kHz crystal oscillator circuit Table 26–584 capacitance of the crystal and is usually specified by the crystal manufacturer. The actual influences oscillation frequency. When using a crystal that is manufactured for a different load capacitance, the circuit will oscillate at a slightly different frequency (depending on the quality of the crystal) compared to the specified one. -
Page 662: Chapter 27: Lpc24Xx Watchdog Timer (Wdt)
UM10237 Chapter 27: LPC24XX WatchDog Timer (WDT) Rev. 02 — 19 December 2008 1. Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be disabled. -
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NXP Semiconductors When the Watchdog counter underflows, the program counter will start from 0x0000 0000 as in the case of external reset. The Watchdog time-out flag (WDTOF) can be examined to determine if the Watchdog has caused the reset condition. The WDTOF flag must be cleared by software. -
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NXP Semiconductors Table 586. Watchdog operating modes selection WDEN Once the WDEN and/or WDRESET bits are set they can not be cleared by software. Both flags are cleared by an external reset or a Watchdog timer underflow. WDTOF The Watchdog time-out flag is set when the Watchdog times out. This flag is cleared by software. -
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NXP Semiconductors errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing 0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled. The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence. -
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NXP Semiconductors 5. Block diagram The block diagram of the Watchdog is shown below in the synchronization logic (PCLK - WDCLK) is not shown in the block diagram. RTC oscillator internal RC oscillator Fig 137. Watchdog block diagram UM10237_2 User manual... -
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UM10237 Chapter 28: LPC24XX Analog-to Digital Converter (ADC) Rev. 02 — 19 December 2008 1. Basic configuration The ADC is configured using the following registers: 1. Power: In the PCONP register Remark: On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit, and then enable the ADC in the AD0CR register (bit PDN) the ADC, first clear the PDN bit, and then clear the PCADC bit. -
Page 668: Not Used
NXP Semiconductors Table 592. ADC pin description Type Description AD0[7:0] Input Analog Inputs. The A/D converter cell can measure the voltage on any of these input signals. Note that these analog inputs are always connected to their pins, even if the Pin Multiplexing Register assigns them to port pins. -
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NXP Semiconductors Table 593. Summary of ADC registers Name AD0DR3 AD0DR4 AD0DR5 AD0DR6 AD0DR7 Reset Value reflects the data stored in used bits only. It does not include reserved bits content. 5.1 A/D Control Register (AD0CR - 0xE003 4000) The A/D Control Register provides bits to select A/D channels to be converted, A/D timing, A/D modes, and the A/D start trigger. -
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NXP Semiconductors Table 594: A/D Control Register (AD0CR - address 0xE003 4000) bit description Symbol Value Description 19:17 CLKS This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). -
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NXP Semiconductors Table 595: A/D Global Data Register (AD0GDR - address 0xE003 4004) bit description Symbol Unused 15:6 23:16 Unused 26:24 CHN 29:27 Unused OVERU DONE 5.3 A/D Status Register (AD0STAT - 0xE003 4030) The A/D Status register allows checking the status of all A/D channels simultaneously. -
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NXP Semiconductors 5.4 A/D Interrupt Enable Register (AD0INTEN - 0xE003 400C) This register allows control over which A/D channels generate an interrupt when a conversion is complete. For example, it may be desirable to use some A/D channels to monitor sensors by continuously performing conversions on them. The most recent results are read by the application program whenever they are needed. -
Page 673: Hardware-Triggered Conversion
NXP Semiconductors 6. Operation 6.1 Hardware-triggered conversion If the BURST bit in the ADCR is 0 and the START field contains 010-111, the A/D converter will start a conversion when a transition occurs on a selected pin or Timer Match signal. -
Page 674: Chapter 29: Lpc24Xx Digital-To Analog Converter (Dac)
UM10237 Chapter 29: LPC24XX Digital-to Analog Converter (DAC) Rev. 02 — 19 December 2008 1. Basic configuration The DAC is configured using the following registers: 1. Power: The DAC is always on. 2. Clock: In the PCLK_SEL0 register 3. Pins: Select the DAC pin and pin mode in registers PINSEL1 and PINMODE1 (see Section 2. -
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NXP Semiconductors Table 600: D/A Converter Register (DACR - address 0xE006 C000) bit description Symbol Value 15:6 VALUE BIAS 31:17 - 5. Operation Bits 21:20 of the PINSEL1 register (PINSEL1 - 0xE002 C004)” on page controlling the state of pin P0.26/AD0.3/AOUT/RXD3. When these bits are 10, the DAC is powered on and active. -
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UM10237 Chapter 30: LPC24XX Flash memory programming firmware Rev. 02 — 19 December 2008 1. How to read this chapter Remark: This chapter applies to parts LPC2458, LPC2468, and LPC2478. 2. Flash boot loader The Boot Loader controls initial operation after reset, and also provides the means to accomplish programming of the Flash memory. -
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NXP Semiconductors When ISP mode is entered after a power on reset, the IRC and PLL are used to generate CCLK of 14.748 MHz. This may not be the case when ISP is invoked by the user application (see 5.1 Memory map after any reset The Flash portion of the boot block is 8 kB in size and resides in the top portion (starting from 0x0007 E000) of the on-chip Flash memory. -
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NXP Semiconductors If the signature is not valid, the auto-baud routine synchronizes with the host via serial port 0. The host should send a ’?’ (0x3F) as a synchronization character and wait for a response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity. -
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NXP Semiconductors A description of UU-encode is available at the wotsit webpage. 5.2.4 ISP flow control A software XON/XOFF flow control scheme is used to prevent data loss due to buffer overrun. When the data arrives rapidly, the ASCII control character DC3 (stop) is sent to stop the flow of data. -
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NXP Semiconductors 6. Boot process flowchart RESET INITIALIZE CRP1/2/3 ENABLED? WATCHDOG FLAG SET? CRP3 ENABLED? USER CODE VALID? (1) For details on handling the crystal frequency, see (2) For details on available ISP commands based on the CRP settings see Fig 139. -
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NXP Semiconductors 7. Sector numbers Some IAP and ISP commands operate on "sectors" and specify sector numbers. The following table indicate the correspondence between sector numbers and memory addresses for LPC2400 devices. IAP, ISP, and RealMonitor routines are located in the boot block. -
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NXP Semiconductors 8. Code Read Protection (CRP) Code Read Protection is a mechanism that allows user to enable different levels of security in the system so that access to the on-chip Flash and use of the ISP can be restricted. When needed, CRP is invoked by programming a specific pattern in Flash location at 0x000001FC. -
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NXP Semiconductors Table 603. Code Read Protection hardware/software interaction CRP option CRP1 CRP1 CRP2 CRP2 CRP3 CRP1 CRP2 CRP3 In case a CRP mode is enabled and access to the chip is allowed via the ISP, an unsupoorted or restricted ISP command will be terminated with return code CODE_READ_PROTECTION_ENABLED. -
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NXP Semiconductors Table 604. ISP command summary ISP Command Read Part ID Read Boot code version K Compare 9.1 Unlock <Unlock code> Table 605. ISP Unlock command Command Input Return Code Description Example 9.2 Set Baud Rate <Baud Rate> <stop bit>... -
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NXP Semiconductors 9.3 Echo <setting> Table 608. ISP Echo command Command Input Return Code Description Example 9.4 Write to RAM <start address> <number of bytes> The host should send the data only after receiving the CMD_SUCCESS return code. The host should send the check-sum after transmitting 20 UU-encoded lines. The checksum is generated by adding raw data (before UU-encoding) bytes and is reset after transmitting 20 UU-encoded lines. -
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NXP Semiconductors "OK<CR><LF>" to continue further transmission. If the check-sum does not match then the host should respond with "RESEND<CR><LF>". In response the ISP command handler sends the data again. Table 610. ISP Read Memory command Command Input Return Code... -
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NXP Semiconductors 9.7 Copy RAM to Flash <Flash address> <RAM address> <no of bytes> Table 612. ISP Copy command Command Input Return Code CMD_SUCCESS | Description Example 9.8 Go <address> <mode> Table 613. ISP Go command Command Input Return Code CMD_SUCCESS |... -
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NXP Semiconductors 9.9 Erase sector(s) <start sector number> <end sector number> Table 614. ISP Erase sector command Command Input Return Code CMD_SUCCESS | Description Example 9.10 Blank check sector(s) <sector number> <end sector number> Table 615. ISP Blank check sector command... -
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NXP Semiconductors Table 617. LPC24xx part Identification numbers Device LPC2458 LPC2468 LPC2478 9.12 Read Boot code version number Table 618. ISP Read Boot Code version number command Command Input Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format. -
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NXP Semiconductors Table 620. ISP Return Codes Summary Return Mnemonic Code DST_ADDR_ERROR SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR INVALID_SECTOR SECTOR_NOT_BLANK SECTOR_NOT_PREPARED_FOR_ WRITE_OPERATION COMPARE_ERROR BUSY PARAM_ERROR ADDR_ERROR ADDR_NOT_MAPPED CMD_LOCKED INVALID_CODE INVALID_BAUD_RATE INVALID_STOP_BIT CODE_READ_PROTECTION_ ENABLED 10. IAP commands For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters. -
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NXP Semiconductors Define the IAP location entry point. Since the 0th bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address. #define IAP_LOCATION 0x7ffffff1 Define data structure or pointers to pass IAP command table and result table to the IAP function: unsigned long command[5];... -
Page 692: Prepare Sector(S) For Write Operation
NXP Semiconductors The Flash memory is not accessible during a write or erase operation. IAP commands, which results in a Flash write/erase operation, use 32 bytes of space in the top portion of the on-chip RAM for execution. The user program should not be use this space if IAP Flash programming is permitted in the application. -
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NXP Semiconductors Table 622. IAP Prepare sector(s) for write operation command Command Input Return Code Result Description 10.2 Copy RAM to Flash Table 623. IAP Copy RAM to Flash command Command Input Return Code Result Description UM10237_2 User manual Chapter 30: LPC24XX Flash memory programming firmware... -
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NXP Semiconductors 10.3 Erase Sector(s) Table 624. IAP Erase Sector(s) command Command Input Return Code Result Description 10.4 Blank check sector(s) Table 625. IAP Blank check sector(s) command Command Input Return Code Result Description 10.5 Read Part Identification number Table 626. IAP Read Part Identification command... -
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NXP Semiconductors 10.6 Read Boot code version number Table 627. IAP Read Boot Code version number command Command Input Return Code Result Description 10.7 Compare <address1> <address2> <no of bytes> Table 628. IAP Compare command Command Input Return Code Result Description 10.8 Reinvoke ISP... -
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NXP Semiconductors Table 629. Reinvoke ISP Command Return Code Result Description 10.9 IAP Status Codes Table 630. IAP Status Codes Summary Status Mnemonic Code CMD_SUCCESS INVALID_COMMAND SRC_ADDR_ERROR DST_ADDR_ERROR SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR INVALID_SECTOR SECTOR_NOT_BLANK SECTOR_NOT_PREPARED_ FOR_WRITE_OPERATION COMPARE_ERROR BUSY 11. JTAG Flash programming interface Debug tools can write parts of the Flash image to the RAM and then execute the IAP call "Copy RAM to Flash"... -
Page 697: Chapter 31: Lpc24Xx On-Chip Bootloader For Flashless Parts
UM10237 Chapter 31: LPC24XX On-chip bootloader for flashless parts Rev. 02 — 19 December 2008 1. How to read this chapter Remark: This chapter describes the boot process for flashless parts LPC2420/60 and LPC2470. It does not apply to parts LPC2458, LPC2468, and LPC2478. The on-chip bootloader version 3.4 controls the boot process for flashless LPC2400 parts LPC2420/60 and LPC2470. -
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NXP Semiconductors Pin P2.10 that is used as hardware request for ISP requires special attention. Since P2.10 is in high impedance mode after reset, it is important that the user provides external hardware (a pull-up resistor or other device) to put the pin in a defined state. Otherwise unintended entry into ISP mode may occur. -
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NXP Semiconductors 4.2.1 ISP command format "Command Parameter_0 Parameter_1 ... Parameter_n<CR><LF>" "Data" (Data only for Write commands). 4.2.2 ISP response format "Return_Code<CR><LF>Response_0<CR><LF>Response_1<CR><LF> ... Response_n<CR><LF>" "Data" (Data only for Read commands). 4.2.3 ISP data format The data stream is in UU-encode format. The UU-encode algorithm converts 3 bytes of binary data in to 4 bytes of printable ASCII character set. -
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NXP Semiconductors 4.2.9 RAM used by IAP command handler IAP programming commands use the top 32 bytes of on-chip RAM. The maximum stack usage in the user allocated stack space is 128 bytes and it grows downwards. 4.2.10 RAM used by RealMonitor The RealMonitor uses on-chip RAM from 0x4000 0040 to 0x4000 011F. -
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NXP Semiconductors 6. ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format. -
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NXP Semiconductors Table 633. ISP Set Baud Rate command Command Return Code Description Example Table 634. Correlation between possible ISP baudrates and CCLK frequency (in MHz) ISP Baudrate .vs. CCLK Frequency 10.0000 11.0592 12.2880 14.7456 15.3600 18.4320 19.6608 24.5760 25.0000 ISP entry after reset uses the on chip IRC and PLL to run the device at CCLK = 14.748 MHz... -
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NXP Semiconductors continue further transmission. If the check-sum does not match, the ISP command handler responds with "RESEND<CR><LF>". In response the host should retransmit the bytes. Table 636. ISP Write to RAM command Command Input Return Code Description Example 6.5 Read Memory <address> <no. of bytes>... -
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NXP Semiconductors 6.6 Go <address> <mode> Table 638. ISP Go command Command Input Return Code CMD_SUCCESS | Description Example 6.7 Read Part Identification number Table 639. ISP Read Part Identification command Command Input Return Code CMD_SUCCESS followed by part identification number in ASCII (see Description Table 640. -
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NXP Semiconductors 6.9 Compare <address1> <address2> <no of bytes> Table 642. ISP Compare command Command Input Return Code CMD_SUCCESS | (Source and destination data are equal) Description Example 6.10 ISP Return Codes Table 643. ISP Return Codes Summary Return Mnemonic... -
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NXP Semiconductors Table 643. ISP Return Codes Summary Return Mnemonic Code ADDR_NOT_MAPPED CMD_LOCKED INVALID_CODE INVALID_BAUD_RATE INVALID_STOP_BIT 7. IAP commands For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters. Result of the IAP command is returned in the result table pointed to by register r1. -
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NXP Semiconductors Setting function pointer: iap_entry=(IAP) IAP_LOCATION; Whenever you wish to call IAP you could use the following statement. iap_entry (command, result); The IAP call could be simplified further by using the symbol definition file feature supported by ARM Linker in ADS (ARM Developer Suite). You could also call the IAP routine using assembly code. -
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NXP Semiconductors Fig 143. IAP parameter passing 7.1 Read Part Identification number Table 645. IAP Read Part Identification command Command Input Return Code Result Description 7.2 Read Boot code version number Table 646. IAP Read Boot Code version number command... -
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NXP Semiconductors 7.3 Compare <address1> <address2> <no of bytes> Table 647. IAP Compare command Command Input Return Code Result Description 7.4 Reinvoke ISP Table 648. Reinvoke ISP Command Input Return Code Result Description 7.5 IAP Status Codes Table 649. IAP Status Codes Summary... -
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NXP Semiconductors Table 649. IAP Status Codes Summary Status Mnemonic Code DST_ADDR_ERROR SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR COMPARE_ERROR BUSY UM10237_2 User manual Chapter 31: LPC24XX On-chip bootloader for flashless parts Description Destination address is not on a correct boundary. Source address is not mapped in the memory map. -
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UM10237 Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Rev. 02 — 19 December 2008 1. Basic configuration The GPDMA is configured using the following registers: 1. Power: In the PCONP register Remark: On reset, the GPDMA is disabled (PCGPDMA = 0). 2. -
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NXP Semiconductors • Supports 8, 16, and 32 bit wide transactions. • Big-endian and little-endian support. The GPDMA defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. -
Page 713: Dma Request And Response Interface
NXP Semiconductors example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. Figure 32–144... -
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NXP Semiconductors 4.2.4 Channel Logic and Channel Register Bank The channel logic and channel register bank contains registers and logic required for each DMA channel. 4.2.5 Interrupt Request The interrupt request generates interrupts to the ARM processor. 4.2.6 AHB Master Interface The GPDMA contains a full AHB master. -
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NXP Semiconductors Table 32–651 Table 651. Endian behavior Source Destination Source Endian Endian Width Little Little Little Little Little Little Little Little Little Little Little Little Little Little Little Little Little Little UM10237_2 User manual Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller shows endian behavior for different source and destination combinations. -
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NXP Semiconductors Table 651. Endian behavior Source Destination Source Endian Endian Width 4.2.9 Error conditions An error during a DMA transfer is flagged directly by the peripheral by asserting an Error response on the AHB bus during the transfer. The GPDMA automatically disables the DMA stream after the current transfer has completed, and can optionally generate an error interrupt to the CPU. -
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NXP Semiconductors 4.2.10 Channel hardware Each stream is supported by a dedicated hardware channel, including source and destination controllers, and a FIFO. This enables better latency than a DMA controller with only a single hardware channel shared between several DMA streams and simplifies the control logic. -
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NXP Semiconductors Table 652. DMA Connections Peripheral Function DMA Single SSP1 Rx SD/MMC S channel 0 S channel 1 5. Programming the GPDMA The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream is configured to provide unidirectional DMA transfers for a single source and destination. -
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NXP Semiconductors 5.3 Enabling a DMA channel To enable the DMA channel set the Channel Enable bit in the relevant DMA channel Configuration Register ( (DMACC0Configuration - 0xFFE0 4110 and DMACC1Configuration - 0xFFE0 Note: The channel must be fully initialized before it is enabled. Additionally, you must set the Enable bit of the GPDMA before any channels are enabled. -
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NXP Semiconductors 5.9 Programming a DMA channel To program a DMA channel: 1. Choose a free DMA channel with the priority required. DMA channel 0 has the highest priority and DMA channel 1 the lowest priority. 2. Clear any pending interrupts on the channel to be used by writing to the... -
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NXP Semiconductors Table 653. Summary of GPDMA registers Name DMACEnbldChns DMACSoftBReq DMACSoftSReq DMACSoftLBReq DMACSoftLSReq DMACConfiguration DMACSync Channel 0 Registers DMACC0SrcAddr DMACC0DestAddr DMACC0LLI DMACC0Control DMACC0Configuration Channel 1 Registers DMACC1SrcAddr DMACC1DestAddr DMACC1LLI DMACC1Control DMACC1Configuration Reset Value reflects the data stored in used bits only. It does not include reserved bits content. -
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NXP Semiconductors Table 654. Interrupt Status register (DMACIntStatus - address 0xFFE0 4000) bit description Symbol IntStatus0 IntStatus1 31:2 6.1.2 Interrupt Terminal Count Status Register (DMACIntTCStatus - 0xFFE0 4004) The DMACIntTCStatus Register is read-only and indicates the status of the terminal count after masking. -
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NXP Semiconductors Table 657. Interrupt Error Status register (DMACIntErrorStatus - address 0xFFE0 400C) bit Symbol IntErrorStatus0 IntErrorStatus1 31:2 6.1.5 Interrupt Error Clear Register (DMACIntErrClr - 0xFFE0 4010) The DMACIntErrClr Register is write-only and clears the error interrupt requests. When writing to this register, each data bit that is HIGH causes the corresponding bit in the status register to be cleared. -
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NXP Semiconductors Table 660. Raw Error Interrupt Status register (DMACRawIntErrorStatus - address Symbol RawIntErrorStatus0 Status of the error interrupt for channel 0 prior to masking. RawIntErrorStatus1 Status of the error interrupt for channel 1 prior to masking. 31:2 6.1.8 Enabled Channel Register (DMACEnbldChns - 0xFFE0 401C) The DMACEnbldChns Register is read-only and indicates which DMA channels are enabled, as indicated by the Enable bit in the DMACCxConfiguration Register. -
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NXP Semiconductors 6.1.10 Software Single Request Register (DMACSoftSReq - 0xFFE0 4024) The DMACSoftSReq Register is read/write and enables DMA single requests to be generated by software. A DMA request can be generated for each source by writing a 1 to the corresponding register bit. -
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NXP Semiconductors Table 665. Software Last Single Request register (DMACSoftLSReq - address 0xFFE0 402C) Symbol SoftLSReqSDMMC 31:5 6.1.13 Configuration Register (DMACConfiguration - 0xFFE0 4030) The DMACConfiguration Register is read/write and configures the operation of the GPDMA. The endianness of the AHB master interface can be altered by writing to the M bit of this register. -
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NXP Semiconductors 6.2 Channel registers The channel registers are used to program the two DMA channels. These registers consist of: • Two DMACCxSrcAddr Registers • Two DMACCxDestAddr Registers • Two DMACCxLLI Registers • Two DMACCxControl Registers • Two DMACCxConfiguration Registers When performing scatter/gather DMA the first four registers are automatically updated. -
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NXP Semiconductors Table 669. Channel Destination Address registers (DMACC0DestAddr - address Symbol 31:0 DestAddr 6.2.3 Channel Linked List Item Registers (DMACC0LLI - 0xFFE0 4108 and DMACC1LLI - 0xFFE0 4128) The two read/write DMACCxLLI Registers contain a word-aligned address of the next Linked List Item (LLI). -
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NXP Semiconductors Table 671. Channel Control registers (DMACC0Control - address 0xFFE0 410C and Symbol 11:0 TransferSize Transfer size. A write to this field sets the size of the transfer 14:12 SBSize 17:15 DBsize 20:18 SWidth 23:21 DWidth 25:24 - 30:28 Prot Table 32–672... -
Page 730: Protection And Access Information
NXP Semiconductors Table 672. Source or destination burst size Bit value of DBSize or SBSize Table 32–673 transfer width. Table 673. Source or destination transfer width Bit value of DBWidth or SBWidth 011 and 1xxx 6.2.5 Protection and Access Information AHB access information is provided to the source and destination peripherals when a transfer occurs. -
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NXP Semiconductors Table 674. Protection bits DMACC1Control 6.2.6 Channel Configuration Registers (DMACC0Configuration - 0xFFE0 4110 and DMACC1Configuration - 0xFFE0 4130) The two DMACCxConfiguration Registers are read/write with the exception of bit[17] which is read-only. Used these to configure the DMA channel. The registers are not updated when a new LLI is requested. -
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NXP Semiconductors Table 675. Channel Configuration registers (DMACC0Configuration - address 0xFFE0 4110 and DMACC1Configuration - address 0xFFE0 4130) bit description Symbol Value Description SrcPeripheral Source peripheral. This value selects the DMA source request peripheral.This field is ignored if the source of the transfer is from memory. -
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NXP Semiconductors There are situations when the GPDMA asserts the lock for source transfers followed by destination transfers. This is possible when internal conditions in the GPDMA permit it to perform a source fetch followed by a destination drain back-to-back. -
Page 734: Programming The Gpdma For Scatter/Gather Dma
NXP Semiconductors 8.2 Programming the GPDMA for scatter/gather DMA To program the GPDMA for scatter/gather DMA: 1. Write the LLIs for the complete DMA transfer to memory. Each linked list item contains four words: – Source address. – Destination address. -
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NXP Semiconductors • Source start address 0x0A200. • Destination address set to the destination peripheral address. • Transfer width, word (32 bit). • Transfer size, 3 072 bytes (0XC00). • Source and destination burst sizes, 16 transfers. • Next LLI address, 0x20010. -
Page 736: Hardware Interrupt Sequence Flow
NXP Semiconductors 9.1 Hardware interrupt sequence flow When a DMA interrupt request occurs, the Interrupt Service Routine needs to: 1. Read the DMACIntStatus Register to determine which channel generated the interrupt. If more than one request is active it is recommended that the highest priority channels be checked first. -
Page 737: Peripheral-To-Peripheral Dma Flow
NXP Semiconductors Table 677. DMA request signal usage Transfer Direction Memory-to-peripheral Memory-to-peripheral Peripheral-to-memory Peripheral-to-memory Memory-to-memory Source peripheral to destination peripheral Source peripheral to destination peripheral Source peripheral to destination peripheral 10.1 Peripheral-to-memory, or Memory-to-peripheral DMA flow For a peripheral-to-memory or memory-to-peripheral DMA flow the following sequence occurs: 1. -
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NXP Semiconductors – The DMA stream has the highest pending priority. – The GPDMA is the bus master of the AHB bus. 4. If an error occurs while transferring the data an error interrupt is generated, then finishes. 5. Decrement the transfer count if the GPDMA is performing the flow control. -
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NXP Semiconductors 11. Flow control The peripheral that controls the length of the packet is known as the flow controller. The flow controller is usually the GPDMA where the packet length is programmed by software before the DMA channel is enabled. If the packet length is unknown when the DMA channel is enabled, either the source or destination peripherals can be used as the flow controller. -
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UM10237 Chapter 33: LPC24XX EmbeddedICE Rev. 02 — 19 December 2008 1. Features • No target resources are required by the software debugger in order to start the debugging session. • Allows the software debugger to talk via a JTAG (Joint Test Action Group) port directly to the core. -
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NXP Semiconductors trigger on an access to a peripheral and the second to trigger on the code segment that performs the task switching. Therefore when the breakpoints trigger the information regarding which task has switched out will be ready for examination. -
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NXP Semiconductors 5. JTAG function select Remark: JTAG access to the LPC2400 is only possible if no code read protection is selected, see The JTAG port may be used either for debug or for boundary scan. The state of the DBGEN pin determines which function is available. -
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NXP Semiconductors host running debugger Fig 147. EmbeddedICE debug environment block diagram UM10237_2 User manual JTAG PORT serial parallel EMBEDDED ICE interface INTERFACE PROTOCOL CONVERTER TARGET BOARD Rev. 02 — 19 December 2008 UM10237 Chapter 33: LPC24XX EmbeddedICE EMBEDDED ICE ARM7TDMI-S ©... -
Page 744: Chapter 34: Lpc24Xx Embedded Trace Module (Etm)
UM10237 Chapter 34: LPC24XX Embedded Trace Module (ETM) Rev. 02 — 19 December 2008 1. Features • Closely track the instructions that the ARM core is executing. • One external trigger input. • 10 pin interface. • All registers are programmed through JTAG interface. •... -
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NXP Semiconductors Table 680. ETM configuration Resource number/type External Inputs External Outputs FIFOFULL Present FIFO depth Trace Packet Width For details refer to ARM documentation "Embedded Trace Macrocell Specification (ARM IHI 0014E)". 4. Pin description Table 681. ETM pin description... -
Page 746: Reset State Of Multiplexed Pins
NXP Semiconductors Table 682. ETM Registers Name ETM Control ETM Configuration Code Trigger Event Memory Map Decode Control Eight bit register, used to statically configure ETM Status System Configuration Trace Enable Control 3 Trace Enable Control 2 Trace Enable Event... -
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NXP Semiconductors 7. Block diagram The block diagram of the ETM debug environment is shown below in Host running debugger Fig 148. ETM debug environment block diagram UM10237_2 User manual Chapter 34: LPC24XX Embedded Trace Module (ETM) CONNECTOR TRACE PORT... -
Page 748: Chapter 35: Lpc24Xx Realmonitor
UM10237 Chapter 35: LPC24XX RealMonitor Rev. 02 — 19 December 2008 1. Features Remark: RealMonitor is a configurable software module which enables real time debug. RealMonitor is developed by ARM Inc. Information presented in this chapter is taken from the ARM document RealMonitor Target Integration Guide (ARM DUI 0142A). It applies to a specific configuration of RealMonitor software programmed in the on-chip ROM boot memory of this device. -
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NXP Semiconductors processor context saving and restoring. RealMonitor is pre-programmed in the on-chip ROM memory (boot sector). When enabled It allows user to observe and debug while parts of application continue to run. Refer to page 751 for details. 3.1 RealMonitor components... -
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NXP Semiconductors 3.2 How RealMonitor works In general terms, the RealMonitor operates as a state machine, as shown in Figure 35–150. RealMonitor switches between running and stopped states, in response to packets received by the host, or due to asynchronous events on the target. RMTarget supports the triggering of only one breakpoint, watchpoint, stop, or semihosting SWI at a time. -
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NXP Semiconductors – Undef exception caused by the undefined instructions in user foreground application. This indicates an error in the application being debugged. RealMonitor stops the user application until a "Go" packet is received from the host. When one of these exceptions occur that is not handled by user application, the following happens: •... -
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NXP Semiconductors 4.5 Prefetch Abort mode RealMonitor uses four words on entry to its Prefetch abort interrupt handler. 4.6 Data Abort mode RealMonitor uses four words on entry to its data abort interrupt handler. 4.7 User/System mode RealMonitor makes no use of this stack. -
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NXP Semiconductors RESET UNDEF PREFETCH ABORT DATA ABORT RESERVED Fig 151. Exception handlers 4.10 RMTarget initialization While the processor is in a privileged mode, and IRQs are disabled, user must include a line of code within the start-up sequence of application to call rm_init_entry(). -
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NXP Semiconductors NOP ; Insert User code valid signature here. LDR pc, [pc, #-0x120] ;Load IRQ vector from VIC LDR PC, FIQ_Address Reset_Address Undefined_Address SWI_Address Prefetch_Address Abort_Address FIQ_Address AREA init_code, CODE ram_end EQU 0x4000xxxx ; Top of on-chip RAM. __init ;... -
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NXP Semiconductors ; /********************************************************************* ; * Setup Vectored Interrupt controller. DCC Rx and Tx interrupts ; * generate Non Vectored IRQ request. rm_init_entry is aware ; * of the VIC and it enables the DBGCommRX and DBGCommTx interrupts. ; * Default vector address register is programmed with the address of ;... -
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NXP Semiconductors ;is not aware of the VIC interrupt priority hardware so trick ;rm_irqhandler2 to return here STMFD sp!, {ip,pc} ;rm_irqhandler2 returns here STMFD sp!, {r0} LDMFD sp!, {r12,r14,r0} SUBS pc, r14, #4 5. RealMonitor build options RealMonitor was built with the following options:... -
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NXP Semiconductors RM_OPT_READBYTES=TRUE RM_OPT_WRITEBYTES=TRUE RM_OPT_READHALFWORDS=TRUE RM_OPT_WRITEHALFWORDS=TRUE RM_OPT_READWORDS=TRUE RM_OPT_WRITEWORDS=TRUE Enables/Disables support for 8/16/32 bit read/write. RM_OPT_EXECUTECODE=FALSE Enables/Disables support for executing code from "execute code" buffer. The code must be downloaded first. RM_OPT_GETPC=TRUE This option enables or disables support for the RealMonitor GetPC packet. Useful in code profiling when real monitor is used in interrupt mode. -
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NXP Semiconductors This option specifies the size, in words, of the data logging FIFO buffer. CHAIN_VECTORS=FALSE This option allows RMTarget to support vector chaining through µHAL (ARM HW abstraction API). UM10237_2 User manual Chapter 35: LPC24XX RealMonitor Rev. 02 — 19 December 2008 UM10237 ©... -
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UM10237 Chapter 36: LPC24XX Supplementary information Rev. 02 — 19 December 2008 1. Abbreviations Table 684. Acronyms and abbreviations Acronym AMBA GPIO JTAG RMII UART UM10237_2 User manual Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Byte Lane Select BrownOut Detection Controller Area Network... -
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Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. -
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NXP Semiconductors 3. Tables Table 1. LPC24XX overview..... . .3 Table 2. Differences between LPC2400 parts ..4 Table 3. -
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NXP Semiconductors 0xFFE0 8028) bit description ....81 Table 74. Dynamic Memory Percentage Command Period register (EMCDynamictRP - address 0xFFE0 8030) bit description ....82 Table 75. -
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NXP Semiconductors Interrupt Controller ..... 115 Table 117. Interrupt sources bit allocation table ..117 Table 118. -
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NXP Semiconductors Table 175.GPIO overall Interrupt Status register (IOIntStatus - address 0xE002 8080) bit description ..206 Table 176.GPIO Interrupt Enable for Rising edge register (IO0IntEnR - address 0xE002 8090 and IO2IntEnR - address 0xE002 80B0) bit description ......206 Table 177.GPIO Interrupt Enable for Falling edge register... -
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NXP Semiconductors Table 228.Interrupt Status register (IntStatus - address 0xFFE0 0FE0) bit description ... . .238 Table 229.Interrupt Enable register (intEnable - address 0xFFE0 0FE4) bit description ... . .238 Table 230.Interrupt Clear register (IntClear - address... -
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NXP Semiconductors (USBDevIntSt - address 0xFFE0 C200) bit allocation ......339 Table 299.USB Device Interrupt Status register (USBDevIntSt - address 0xFFE0 C200) bit description . -
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NXP Semiconductors description ......358 Table 345.USB System Error Interrupt Clear register (USBSysErrIntClr - address 0xFFE0 C2BC) bit description . -
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NXP Semiconductors Table 401:UART1 Interrupt Enable Register (U1IER - address 0xE001 0004 when DLAB = 0) bit description ......448... -
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NXP Semiconductors Table 452.FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0xE003 C024) bit description ......505 Table 453.FullCAN Interrupt and Capture register 1... -
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NXP Semiconductors Table 514.I C Control Set Register (I2C[0/1/2]CONCLR - addresses 0xE001 C018, 0xE005 C018, 0xE008 0018) bit description ... . .584 Table 515.I C Status Register (I2C[0/1/2]STAT - addresses 0xE001 C004, 0xE005 C004, 0xE008 0004) bit description . -
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NXP Semiconductors Table 573.Alarm Mask Register (AMR - address 0xE002 4010) bit description ... . .653 Table 574.Consolidated Time register 0 (CTIME0 - address 0xE002 4014) bit description ... . .654 Table 575.Consolidated Time register 1 (CTIME1 - address... -
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NXP Semiconductors Table 656.Interrupt Terminal Count Clear register (DMACIntClear - address 0xFFE0 4008) bit description ......722 Table 657.Interrupt Error Status register... -
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NXP Semiconductors 4. Figures Fig 1. LPC2458 block diagram ....11 Fig 2. LPC2460 block diagram ....12 Fig 3. -
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NXP Semiconductors Fig 88. Message overwritten indicated by semaphore bits and message lost......516 Fig 89. Message overwritten indicated by message lost517 Fig 90. -
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NXP Semiconductors 5. Contents Chapter 1: LPC24XX Introductory information Introduction ......3 How to read this manual ....3 LPC2400 features. -
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NXP Semiconductors 3.2.14 PLL setup sequence ....56 Clock dividers ......56 3.3.1... -
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NXP Semiconductors 10.26 Static Memory Write Delay registers (EMCStaticWaitwr0-3 - 0xFFE0 8214, 234, 254, 274) ....... . 94 10.27... -
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NXP Semiconductors Pin Function Select Register 8 (PINSEL8 - 0xE002 C020)......186 5.10 Pin Function Select Register 9 (PINSEL9 - 0xE002 C024). -
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NXP Semiconductors 7.1.8 Test Register (TEST - 0xFFE0 001C)..223 7.1.9 MII Mgmt Configuration Register (MCFG - 0xFFE0 0020) ......224 7.1.10... -
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NXP Semiconductors Programmable parameters ....281 Hardware cursor support ....281 Types of LCD panels supported ..282 TFT panels . -
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NXP Semiconductors Pin description ......333 USB device usage note ....333 Clocking and power management . -
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NXP Semiconductors 11.5 Read Test Register (Command: 0xFD, Data: read 2 bytes) ......365 11.6... -
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NXP Semiconductors OTG Interrupt Enable Register (OTGIntEn - 0xFFE0 C104) ..... . . 401 OTG Interrupt Set Register (OTGIntSet - 0xFFE0 C20C) . -
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NXP Semiconductors UART1 Receiver Buffer Register (U1RBR - 0xE001 0000, when DLAB = 0 Read Only) . 447 UART1 Transmitter Holding Register (U1THR - 0xE001 0000 when DLAB = 0, Write Only) . 447 UART1 Divisor Latch LSB and MSB Registers (U1DLL - 0xE001 0000 and U1DLM - 0xE001 0004, when DLAB = 1) . -
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NXP Semiconductors Interrupts......495 Transmit priority ..... . 495 Centralized CAN registers. -
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NXP Semiconductors SPI Clock Counter Register (S0SPCCR - 0xE002 000C)......533 SPI Test Control Register (SPTCR - 0xE002 0010) . -
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NXP Semiconductors 6.14 FIFO Counter Register (MCIFifoCnt - 0xE008 C048)......571 Chapter 22: LPC24XX I C interfaces I Basic configuration . -
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NXP Semiconductors Description ......611 Pin descriptions ..... . . 612 Register description . -
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NXP Semiconductors Pin description ......648 Register description ....649 RTC interrupts . -
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NXP Semiconductors 5.2.4 ISP flow control..... . . 679 5.2.5 ISP command abort ....679 5.2.6... -
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NXP Semiconductors Programming the GPDMA....718 Enabling the GPDMA ....718 Disabling the GPDMA. -
Page 792: Chapter 36: Lpc24Xx Supplementary Information
NXP Semiconductors 3.1.1 RMHost......749 3.1.2 RMTarget ......749 How RealMonitor works .
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