NXP Semiconductors freescale MK30DN512ZVMB10 Manuals

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NXP Semiconductors freescale MK30DN512ZVMB10 Reference Manual

NXP Semiconductors freescale MK30DN512ZVMB10 Reference Manual (1547 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 17 MB

Table of Contents

Table of Contents
3
About this Document
51
Overview
51
Purpose
51
Audience
51
Conventions
51
Numbering Systems
51
Typographic Notation
52
Special Terms
52
Introduction
53
Overview
53
K30 Family Introduction
53
Module Functional Categories
53
ARM Cortex-M4 Core Modules
54
System Modules
55
Memories and Memory Interfaces
56
Clocks
57
Security and Integrity Modules
57
Analog Modules
57
Timer Modules
58
Communication Interfaces
59
Human-Machine Interfaces
60
Orderable Part Numbers
60
Chip Configuration
61
Introduction
61
Core Modules
61
ARM Cortex-M4 Core Configuration
61
Nested Vectored Interrupt Controller (NVIC) Configuration
64
Asynchronous Wake-Up Interrupt Controller (AWIC) Configuration
70
JTAG Controller Configuration
71
System Modules
72
SIM Configuration
72
Mode Controller Configuration
73
PMC Configuration
73
Low-Leakage Wake-Up Unit (LLWU) Configuration
74
MCM Configuration
76
Crossbar Switch Configuration
76
Memory Protection Unit (MPU) Configuration
78
Peripheral Bridge Configuration
81
DMA Request Multiplexer Configuration
83
DMA Controller Configuration
86
External Watchdog Monitor (EWM) Configuration
87
Watchdog Configuration
88
Clock Modules
89
MCG Configuration
89
OSC Configuration
90
RTC OSC Configuration
91
Memories and Memory Interfaces
91
Flash Memory Configuration
91
Flash Memory Controller Configuration
94
SRAM Configuration
95
SRAM Controller Configuration
98
System Register File Configuration
99
VBAT Register File Configuration
100
Ezport Configuration
100
Security
102
CRC Configuration
102
Analog
102
16-Bit SAR ADC with PGA Configuration
102
CMP Configuration
110
12-Bit DAC Configuration
112
VREF Configuration
113
Timers
114
PDB Configuration
114
Flextimer Configuration
117
PIT Configuration
121
Low-Power Timer Configuration
122
CMT Configuration
124
RTC Configuration
125
Communication Interfaces
126
CAN Configuration
126
SPI Configuration
128
I2C Configuration
131
UART Configuration
132
SDHC Configuration
134
I2S Configuration
135
Human-Machine Interfaces (HMI)
137
GPIO Configuration
137
TSI Configuration
138
Segment LCD Configuration
140
Memory Map
143
Introduction
143
System Memory Map
143
Aliased Bit-Band Regions
144
Flash Memory Map
145
Alternate Non-Volatile IRC User Trim Description
146
SRAM Memory Map
146
Peripheral Bridge (AIPS-Lite0 and AIPS-Lite1) Memory Maps
146
Peripheral Bridge 0 (AIPS-Lite 0) Memory Map
147
Peripheral Bridge 1 (AIPS-Lite 1) Memory Map
151
Private Peripheral Bus (PPB) Memory Map
155
Clock Distribution
157
Introduction
157
Programming Model
157
High-Level Device Clocking Diagram
157
Clock Definitions
158
Device Clock Summary
159
Internal Clocking Requirements
160
Clock Divider Values after Reset
161
VLPR Mode Clocking
162
Clock Gating
162
Module Clocks
162
PMC 1-Khz LPO Clock
164
WDOG Clocking
164
Debug Trace Clock
165
PORT Digital Filter Clocking
165
LPTMR Clocking
166
Flexcan Clocking
166
UART Clocking
167
SDHC Clocking
167
I2S Clocking
168
TSI Clocking
168
Reset and Boot
171
Introduction
171
Reset
171
Power-On Reset (POR)
172
System Resets
172
Debug Resets
176
Boot
177
Boot Sources
177
Boot Options
177
FOPT Boot Options
177
Boot Sequence
178
Power Management
181
Introduction
181
Power Modes
181
Entering and Exiting Power Modes
183
Power Mode Transitions
184
Power Modes Shutdown Sequencing
185
Module Operation in Low Power Modes
185
Clock Gating
188
Security
189
Introduction
189
Flash Security
189
Security Interactions with Other Modules
190
Security Interactions with Ezport
190
Security Interactions with Debug
190
Introduction
191
References
193
The Debug Port
193
JTAG-To-SWD Change Sequence
194
JTAG-To-Cjtag Change Sequence
194
Debug Port Pin Descriptions
195
System TAP Connection
195
IR Codes
196
JTAG Status and Control Registers
196
MDM-AP Control Register
197
MDM-AP Status Register
199
Debug Resets
200
Ahb-Ap
201
Itm
202
Core Trace Connectivity
202
Embedded Trace Macrocell V3.5 (ETM)
202
Coresight Embedded Trace Buffer (ETB)
203
Performance Profiling with the ETB
203
ETB Counter Control
204
Tpiu
204
Dwt
204
Debug in Low Power Modes
205
Debug Module State in Low Power Modes
206
Debug & Security
206
Signal Multiplexing and Signal Descriptions
207
Introduction
207
Signal Multiplexing Integration
207
Port Control and Interrupt Module Features
208
Clock Gating
208
Signal Multiplexing Constraints
208
Pinout
209
K30 Signal Multiplexing and Pin Assignments
209
K30 Pinouts
214
Module Signal Description Tables
215
Core Modules
216
System Modules
216
Clock Modules
217
Memories and Memory Interfaces
217
Analog
218
Communication Interfaces
219
Human-Machine Interfaces (HMI)
222
Port Control and Interrupts (PORT)
225
Introduction
225
Overview
225
Features
225
Modes of Operation
226
External Signal Description
227
Detailed Signal Descriptions
227
Memory Map and Register Definition
227
Pin Control Register N (Portx_Pcrn)
234
Global Pin Control Low Register (Portx_Gpclr)
236
Global Pin Control High Register (Portx_Gpchr)
237
Interrupt Status Flag Register (Portx_Isfr)
237
Digital Filter Enable Register (Portx_Dfer)
238
Digital Filter Clock Register (Portx_Dfcr)
239
Digital Filter Width Register (Portx_Dfwr)
239
Functional Description
240
Pin Control
240
Global Pin Control
240
External Interrupts
241
Digital Filter
242
System Integration Module (SIM)
243
Introduction
243
Features
243
Modes of Operation
243
SIM Signal Descriptions
244
Memory Map and Register Definition
244
System Options Register 1 (SIM_SOPT1)
246
System Options Register 2 (SIM_SOPT2)
248
System Options Register 4 (SIM_SOPT4)
250
System Options Register 5 (SIM_SOPT5)
252
System Options Register 6 (SIM_SOPT6)
253
System Options Register 7 (SIM_SOPT7)
254
System Device Identification Register (SIM_SDID)
256
System Clock Gating Control Register 1 (SIM_SCGC1)
258
System Clock Gating Control Register 2 (SIM_SCGC2)
258
System Clock Gating Control Register 3 (SIM_SCGC3)
259
System Clock Gating Control Register 4 (SIM_SCGC4)
260
System Clock Gating Control Register 5 (SIM_SCGC5)
263
System Clock Gating Control Register 6 (SIM_SCGC6)
265
System Clock Gating Control Register 7 (SIM_SCGC7)
267
System Clock Divider Register 1 (SIM_CLKDIV1)
268
System Clock Divider Register 2 (SIM_CLKDIV2)
270
Flash Configuration Register 1 (SIM_FCFG1)
271
Flash Configuration Register 2 (SIM_FCFG2)
272
Unique Identification Register High (SIM_UIDH)
273
Unique Identification Register MID-High (SIM_UIDMH)
274
Unique Identification Register MID Low (SIM_UIDML)
274
Unique Identification Register Low (SIM_UIDL)
275
Functional Description
275
Mode Controller
277
Introduction
277
Features
277
Modes of Operation
277
MCU Reset
288
Mode Control Memory Map/Register Definition
291
System Reset Status Register High (MC_SRSH)
292
System Reset Status Register Low (MC_SRSL)
293
Power Mode Protection Register (MC_PMPROT)
294
Power Mode Control Register (MC_PMCTRL)
296
Power Management Controller
299
Introduction
299
Features
299
Low-Voltage Detect (LVD) System
299
LVD Reset Operation
300
LVD Interrupt Operation
300
Low-Voltage Warning (LVW) Interrupt Operation
300
PMC Memory Map/Register Definition
301
Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)
301
Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)
302
Regulator Status and Control Register (PMC_REGSC)
304
Low-Leakage Wake-Up Unit (LLWU)
305
Introduction
305
Features
306
Modes of Operation
306
Block Diagram
307
LLWU Signal Descriptions
308
Memory Map/Register Definition
309
LLWU Pin Enable 1 Register (LLWU_PE1)
309
LLWU Pin Enable 2 Register (LLWU_PE2)
310
LLWU Pin Enable 3 Register (LLWU_PE3)
312
LLWU Pin Enable 4 Register (LLWU_PE4)
313
LLWU Module Enable Register (LLWU_ME)
314
LLWU Flag 1 Register (LLWU_F1)
315
LLWU Flag 2 Register (LLWU_F2)
317
LLWU Flag 3 Register (LLWU_F3)
319
LLWU Control and Status Register (LLWU_CS)
320
Functional Description
321
LLS Mode
322
VLLS Modes
322
Initialization
323
Low Power Mode Recovery
323
Miscellaneous Control Module (MCM)
325
Introduction
325
Features
325
Memory Map/Register Descriptions
325
Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
326
Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
326
SRAM Arbitration and Protection (MCM_SRAMAP)
327
Interrupt Status Register (MCM_ISR)
328
ETB Counter Control Register (MCM_ETBCC)
329
ETB Reload Register (MCM_ETBRL)
330
ETB Counter Value Register (MCM_ETBCNT)
331
Functional Description
331
Interrupts
331
Crossbar Switch (AXBS)
333
Introduction
333
Features
333
Memory Map / Register Definition
334
Priority Registers Slave (Axbs_Prsn)
335
Control Register (Axbs_Crsn)
338
Master General Purpose Control Register (Axbs_Mgpcrn)
340
Functional Description
341
General Operation
341
Register Coherency
342
Arbitration
342
Initialization/Application Information
345
Memory Protection Unit (MPU)
347
Introduction
347
Overview
347
Block Diagram
347
Features
348
Memory Map/Register Definition
349
Control/Error Status Register (MPU_CESR)
352
Error Address Register, Slave Port N (Mpu_Earn)
354
Error Detail Register, Slave Port N (Mpu_Edrn)
355
Region Descriptor N, Word 0 (Mpu_Rgdn_Word0)
356
Region Descriptor N, Word 1 (Mpu_Rgdn_Word1)
357
Region Descriptor N, Word 2 (Mpu_Rgdn_Word2)
357
Region Descriptor N, Word 3 (Mpu_Rgdn_Word3)
360
Region Descriptor Alternate Access Control N (Mpu_Rgdaacn)
361
Functional Description
363
Access Evaluation Macro
363
Putting It All Together and Error Terminations
364
Power Management
365
Initialization Information
365
Application Information
365
Peripheral Bridge (AIPS-Lite)
369
Introduction
369
Features
369
General Operation
369
Memory Map/Register Definition
370
Master Privilege Register a (Aipsx_Mpra)
371
Peripheral Access Control Register (Aipsx_Pacrn)
375
Peripheral Access Control Register (Aipsx_Pacrn)
380
Functional Description
385
Access Support
385
Direct Memory Access Multiplexer (DMAMUX)
387
Introduction
387
Overview
387
Features
388
Modes of Operation
388
External Signal Description
389
Memory Map/Register Definition
389
Channel Configuration Register (Dmamux_Chcfgn)
390
Functional Description
391
DMA Channels with Periodic Triggering Capability
391
DMA Channels with no Triggering Capability
394
Always Enabled" DMA Sources
394
Initialization/Application Information
395
Reset
395
Enabling and Configuring Sources
395
Direct Memory Access Controller (Edma)
399
Introduction
399
Block Diagram
399
Block Parts
400
Features
402
Modes of Operation
403
Memory Map/Register Definition
403
Control Register (DMA_CR)
418
Error Status Register (DMA_ES)
420
Enable Request Register (DMA_ERQ)
422
Enable Error Interrupt Register (DMA_EEI)
424
Clear Enable Error Interrupt Register (DMA_CEEI)
426
Set Enable Error Interrupt Register (DMA_SEEI)
427
Clear Enable Request Register (DMA_CERQ)
428
Set Enable Request Register (DMA_SERQ)
429
Clear DONE Status Bit Register (DMA_CDNE)
430
Set START Bit Register (DMA_SSRT)
431
Clear Error Register (DMA_CERR)
432
Clear Interrupt Request Register (DMA_CINT)
433
Interrupt Request Register (DMA_INT)
433
Error Register (DMA_ERR)
436
Hardware Request Status Register (DMA_HRS)
438
Channel N Priority Register (Dma_Dchprin)
440
TCD Source Address (Dma_Tcdn_Saddr)
441
TCD Signed Source Address Offset (Dma_Tcdn_Soff)
442
TCD Transfer Attributes (Dma_Tcdn_Attr)
442
TCD Minor Byte Count (Minor Loop Disabled) (Dma_Tcdn_Nbytes_Mlno)
443
TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (Dma_Tcdn_Nbytes_Mloffno)
444
TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
445
(Dma_Tcdn_Nbytes_Mloffyes)
445
TCD Last Source Address Adjustment (Dma_Tcdn_Slast)
446
TCD Destination Address (Dma_Tcdn_Daddr)
446
TCD Signed Destination Address Offset (Dma_Tcdn_Doff)
447
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Citer_Elinkyes)
447
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Citer_Elinkno)
448
TCD Last Destination Address Adjustment/Scatter Gather Address (Dma_Tcdn_Dlastsga)
449
TCD Control and Status (Dma_Tcdn_Csr)
450
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Biter_Elinkyes)
452
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
453
(Dma_Tcdn_Biter_Elinkno)
453
Functional Description
454
Edma Basic Data Flow
454
Error Reporting and Handling
457
Channel Preemption
459
Performance
459
Initialization/Application Information
464
Edma Initialization
464
Programming Errors
466
Arbitration Mode Considerations
466
Performing DMA Transfers
467
Monitoring Transfer Descriptor Status
471
Channel Linking
473
Dynamic Programming
474
External Watchdog Monitor (EWM)
477
Introduction
477
Features
477
Modes of Operation
478
Block Diagram
479
EWM Signal Descriptions
480
Memory Map/Register Definition
480
Control Register (EWM_CTRL)
480
Service Register (EWM_SERV)
481
Compare Low Register (EWM_CMPL)
482
Compare High Register (EWM_CMPH)
482
Functional Description
483
The Ewm_Out Signal
483
The Ewm_In Signal
484
EWM Counter
484
EWM Compare Registers
484
EWM Refresh Mechanism
485
Watchdog Timer (WDOG)
487
Introduction
487
Features
487
Functional Overview
489
Unlocking and Updating the Watchdog
490
The Watchdog Configuration Time (WCT)
491
Refreshing the Watchdog
492
Windowed Mode of Operation
492
Watchdog Disabled Mode of Operation
492
Low Power Modes of Operation
493
Debug Modes of Operation
493
Testing the Watchdog
494
Quick Test
494
Byte Test
494
Backup Reset Generator
496
Generated Resets and Interrupts
496
Memory Map and Register Definition
497
Watchdog Status and Control Register High (WDOG_STCTRLH)
498
Watchdog Status and Control Register Low (WDOG_STCTRLL)
500
Watchdog Time-Out Value Register High (WDOG_TOVALH)
500
Watchdog Time-Out Value Register Low (WDOG_TOVALL)
501
Watchdog Window Register High (WDOG_WINH)
501
Watchdog Window Register Low (WDOG_WINL)
502
Watchdog Refresh Register (WDOG_REFRESH)
502
Watchdog Unlock Register (WDOG_UNLOCK)
502
Watchdog Timer Output Register High (WDOG_TMROUTH)
503
Watchdog Timer Output Register Low (WDOG_TMROUTL)
503
Watchdog Reset Count Register (WDOG_RSTCNT)
504
Watchdog Prescaler Register (WDOG_PRESC)
504
Watchdog Operation with 8-Bit Access
504
General Guideline
505
Refresh and Unlock Operations with 8-Bit Access
505
Restrictions on Watchdog Operation
506
Multipurpose Clock Generator (MCG)
509
Introduction
509
Features
509
Modes of Operation
512
External Signal Description
513
Memory Map/Register Definition
513
MCG Control 1 Register (MCG_C1)
514
MCG Control 2 Register (MCG_C2)
515
MCG Control 3 Register (MCG_C3)
516
MCG Control 4 Register (MCG_C4)
517
MCG Control 5 Register (MCG_C5)
518
MCG Control 6 Register (MCG_C6)
520
MCG Status Register (MCG_S)
521
MCG Auto Trim Control Register (MCG_ATC)
523
MCG Auto Trim Compare Value High Register (MCG_ATCVH)
523
MCG Auto Trim Compare Value Low Register (MCG_ATCVL)
524
Functional Description
524
MCG Mode State Diagram
524
Low Power Bit Usage
529
MCG Internal Reference Clocks
529
External Reference Clock
530
MCG Fixed Frequency Clock
530
MCG PLL Clock
531
MCG Auto TRIM (ATM)
531
Initialization / Application Information
532
MCG Module Initialization Sequence
532
Using a 32.768 Khz Reference
534
MCG Mode Switching
535
Oscillator (OSC)
545
Introduction
545
Features and Modes
545
Block Diagram
546
OSC Signal Descriptions
546
External Crystal / Resonator Connections
547
External Clock Connections
548
Memory Map/Register Definitions
549
OSC Memory Map/Register Definition
549
Functional Description
550
OSC Module States
551
OSC Module Modes
552
Counter
554
Reference Clock Pin Requirements
554
Reset
554
Low Power Modes Operation
555
Interrupts
555
RTC Oscillator
557
Introduction
557
Features and Modes
557
Block Diagram
557
RTC Signal Descriptions
558
EXTAL32 - Oscillator Input
558
XTAL32 - Oscillator Output
558
External Crystal Connections
559
Memory Map/Register Descriptions
559
Functional Description
559
Reset Overview
560
Interrupts
560
Flash Memory Controller (FMC)
561
Introduction
561
Overview
561
Features
561
Modes of Operation
562
External Signal Description
562
Memory Map and Register Descriptions
562
Flash Access Protection Register (FMC_PFAPR)
569
Flash Bank 0 Control Register (FMC_PFB0CR)
572
Flash Bank 1 Control Register (FMC_PFB1CR)
574
Cache Tag Storage (Fmc_Tagvdw0Sn)
576
Cache Tag Storage (Fmc_Tagvdw1Sn)
577
Cache Tag Storage (Fmc_Tagvdw2Sn)
578
Cache Tag Storage (Fmc_Tagvdw3Sn)
579
Cache Data Storage (Upper Word) (Fmc_Dataw0Snu)
580
Cache Data Storage (Lower Word) (Fmc_Dataw0Snl)
581
Cache Data Storage (Upper Word) (Fmc_Dataw1Snu)
582
Cache Data Storage (Lower Word) (Fmc_Dataw1Snl)
583
Cache Data Storage (Upper Word) (Fmc_Dataw2Snu)
584
Cache Data Storage (Lower Word) (Fmc_Dataw2Snl)
585
Cache Data Storage (Upper Word) (Fmc_Dataw3Snu)
586
Cache Data Storage (Lower Word) (Fmc_Dataw3Snl)
587
Functional Description
587
Flash Memory Module (FTFL)
589
Introduction
589
Features
590
Block Diagram
590
Glossary
591
External Signal Description
592
Memory Map and Registers
593
Flash Configuration Field Description
593
Program Flash IFR Map
593
Register Descriptions
594
Functional Description
603
Program Flash Memory Swap
603
Interrupts
604
Flash Operation in Low-Power Modes
604
Functional Modes of Operation
605
Flash Reads and Ignored Writes
605
Read While Write (RWW)
605
Flash Program and Erase
605
FTFL Command Operations
606
Margin Read Commands
611
FTFL Command Description
612
Security
634
Reset Sequence
636
Overview
637
Introduction
637
Features
638
Modes of Operation
638
External Signal Description
639
Ezport Clock (EZP_CK)
639
Ezport Chip Select (EZP_CS)
639
Ezport Serial Data in (EZP_D)
640
Ezport Serial Data out (EZP_Q)
640
Command Definition
640
Command Descriptions
641
Flash Memory Map for Ezport Access
645
Cyclic Redundancy Check (CRC)
647
Introduction
647
Features
647
Block Diagram
648
Modes of Operation
648
Memory Map and Register Descriptions
648
CRC Data Register (CRC_CRC)
649
CRC Polynomial Register (CRC_GPOLY)
650
CRC Control Register (CRC_CTRL)
651
Functional Description
652
CRC Initialization/Re-Initialization
652
CRC Calculations
652
Transpose Feature
653
CRC Result Complement
655
Analog-To-Digital Converter (ADC)
657
Introduction
657
Features
657
Block Diagram
658
ADC Signal Descriptions
659
Analog Power (VDDA)
660
Analog Ground (VSSA)
660
Voltage Reference Select
660
Analog Channel Inputs (Adx)
661
Differential Analog Channel Inputs (Dadx)
661
Register Definition
661
ADC Status and Control Registers 1 (Adcx_Sc1N)
664
ADC Configuration Register 1 (Adcx_Cfg1)
667
Configuration Register 2 (Adcx_Cfg2)
669
ADC Data Result Register (Adcx_Rn)
670
Compare Value Registers (Adcx_Cvn)
671
Status and Control Register 2 (Adcx_Sc2)
672
Status and Control Register 3 (Adcx_Sc3)
674
ADC Offset Correction Register (Adcx_Ofs)
675
ADC Plus-Side Gain Register (Adcx_Pg)
676
ADC Minus-Side Gain Register (Adcx_Mg)
676
ADC Plus-Side General Calibration Value Register (Adcx_Clpd)
677
ADC Plus-Side General Calibration Value Register (Adcx_Clps)
678
ADC Plus-Side General Calibration Value Register (Adcx_Clp4)
678
ADC Plus-Side General Calibration Value Register (Adcx_Clp3)
679
ADC Plus-Side General Calibration Value Register (Adcx_Clp2)
679
ADC Plus-Side General Calibration Value Register (Adcx_Clp1)
680
ADC Plus-Side General Calibration Value Register (Adcx_Clp0)
680
ADC PGA Register (Adcx
681
ADC Minus-Side General Calibration Value Register (Adcx_Clmd)
682
ADC Minus-Side General Calibration Value Register (Adcx_Clms)
683
ADC Minus-Side General Calibration Value Register (Adcx_Clm4)
683
ADC Minus-Side General Calibration Value Register (Adcx_Clm3)
684
ADC Minus-Side General Calibration Value Register (Adcx_Clm2)
684
ADC Minus-Side General Calibration Value Register (Adcx_Clm1)
685
ADC Minus-Side General Calibration Value Register (Adcx_Clm0)
685
Functional Description
686
PGA Functional Description
686
Clock Select and Divide Control
687
Voltage Reference Selection
687
Hardware Trigger and Channel Selects
688
Conversion Control
689
Automatic Compare Function
696
Calibration Function
697
User Defined Offset Function
699
Temperature Sensor
700
MCU Wait Mode Operation
700
MCU Normal Stop Mode Operation
701
MCU Low Power Stop Mode Operation
702
Initialization Information
702
ADC Module Initialization Example
703
Application Information
705
External Pins and Routing
705
Sources of Error
707
Comparator (CMP)
713
Introduction
713
CMP Features
713
6-Bit DAC Key Features
714
ANMUX Key Features
715
CMP, DAC, and ANMUX Diagram
715
CMP Block Diagram
716
Memory Map/Register Definitions
718
CMP Control Register 0 (Cmpx_Cr0)
719
CMP Control Register 1 (Cmpx_Cr1)
720
CMP Filter Period Register (Cmpx_Fpr)
721
CMP Status and Control Register (Cmpx_Scr)
722
DAC Control Register (Cmpx_Daccr)
723
MUX Control Register (Cmpx_Muxcr)
724
CMP Functional Description
725
CMP Functional Modes
726
Power Modes
735
Startup and Operation
736
Low Pass Filter
737
CMP Interrupts
739
CMP DMA Support
739
Digital to Analog Converter Block Diagram
739
DAC Functional Description
740
Voltage Reference Source Select
740
DAC Resets
740
DAC Clocks
740
DAC Interrupts
741
12-Bit Digital-To-Analog Converter (DAC)
743
Introduction
743
Features
743
Block Diagram
743
Memory Map/Register Definition
744
DAC Data Low Register (Dacx_Datnl)
746
DAC Data High Register (Dacx_Datnh)
747
DAC Status Register (Dacx_Sr)
747
DAC Control Register (Dacx_C0)
748
DAC Control Register 1 (Dacx_C1)
749
DAC Control Register 2 (Dacx_C2)
750
Functional Description
750
DAC Data Buffer Operation
751
DMA Operation
752
Resets
752
Low Power Mode Operation
752
Voltage Reference (VREFV1)
755
Introduction
755
Overview
756
Features
756
Modes of Operation
757
VREF Signal Descriptions
757
Memory Map and Register Definition
757
VREF Trim Register (VREF_TRM)
758
VREF Status and Control Register (VREF_SC)
759
Functional Description
760
Voltage Reference Disabled, SC[VREFEN] = 0
760
Voltage Reference Enabled, SC[VREFEN] = 1
760
Initialization/Application Information
761
Programmable Delay Block (PDB)
763
Introduction
763
Features
763
Implementation
764
Back-To-Back Acknowledgement Connections
765
DAC External Trigger Input Connections
765
Block Diagram
765
Modes of Operation
767
PDB Signal Descriptions
767
Memory Map and Register Definition
767
Status and Control Register (Pdbx_Sc)
769
Modulus Register (Pdbx_Mod)
771
Counter Register (Pdbx_Cnt)
772
Interrupt Delay Register (Pdbx_Idly)
772
Channel N Control Register 1 (Pdbx_Chnc1)
773
Channel N Status Register (Pdbx_Chns)
774
Channel N Delay 0 Register (Pdbx_Chndly0)
775
Channel N Delay 1 Register (Pdbx_Chndly1)
775
DAC Interval Trigger N Control Register (Pdbx_Dacintcn)
776
DAC Interval N Register (Pdbx_Dacintn)
776
Pulse-Out N Enable Register (Pdbx_Poen)
777
Pulse-Out N Delay Register (Pdbx_Pondly)
777
Functional Description
778
PDB Pre-Trigger and Trigger Outputs
778
PDB Trigger Input Source Selection
780
DAC Interval Trigger Outputs
780
Pulse-Out's
781
Updating the Delay Registers
781
Interrupts
783
Dma
783
Application Information
783
Impact of Using the Prescaler and Multiplication Factor on Timing Resolution
783
Flextimer (FTM)
785
Introduction
785
Flextimer Philosophy
785
Features
786
Modes of Operation
787
Block Diagram
788
FTM Signal Descriptions
790
EXTCLK - FTM External Clock
790
Chn - FTM Channel (N) I/O Pin
790
Faultj - FTM Fault Input
790
PHA - FTM Quadrature Decoder Phase a Input
791
PHB - FTM Quadrature Decoder Phase B Input
791
Memory Map and Register Definition
791
Module Memory Map
791
Register Descriptions
792
Status and Control (Ftmx_Sc)
798
Counter (Ftmx_Cnt)
799
Modulo (Ftmx_Mod)
800
Channel (N) Status and Control (Ftmx_Cnsc)
801
Channel (N) Value (Ftmx_Cnv)
804
Counter Initial Value (Ftmx_Cntin)
805
Capture and Compare Status (Ftmx_Status)
805
Features Mode Selection (Ftmx_Mode)
808
Synchronization (Ftmx_Sync)
809
Initial State for Channels Output (Ftmx_Outinit)
812
Output Mask (Ftmx_Outmask)
813
Function for Linked Channels (Ftmx_Combine)
815
Deadtime Insertion Control (Ftmx_Deadtime)
820
FTM External Trigger (Ftmx_Exttrig)
821
Channels Polarity (Ftmx_Pol)
823
Fault Mode Status (Ftmx_Fms)
825
Input Capture Filter Control (Ftmx_Filter)
827
Fault Control (Ftmx_Fltctrl)
829
Quadrature Decoder Control and Status (Ftmx_Qdctrl)
831
Configuration (Ftmx_Conf)
833
FTM Fault Input Polarity (Ftmx_Fltpol)
834
Synchronization Configuration (Ftmx_Synconf)
836
FTM Inverting Control (Ftmx_Invctrl)
838
FTM Software Output Control (Ftmx_Swoctrl)
839
FTM PWM Load (Ftmx_Pwmload)
841
Functional Description
843
Clock Source
843
Prescaler
844
Counter
844
Input Capture Mode
849
Output Compare Mode
852
Edge-Aligned PWM (EPWM) Mode
853
Center-Aligned PWM (CPWM) Mode
855
Combine Mode
857
Complementary Mode
864
Registers Updated from Write Buffers
865
PWM Synchronization
867
Inverting
883
Software Output Control
884
Deadtime Insertion
886
Output Mask
889
Fault Control
890
Polarity Control
893
Initialization
894
Features Priority
894
Channel Trigger Output
895
Initialization Trigger
896
Capture Test Mode
898
Dma
899
Dual Edge Capture Mode
900
Quadrature Decoder Mode
907
BDM Mode
912
Intermediate Load
913
Global Time Base (GTB)
915
Reset Overview
916
FTM Interrupts
918
Timer Overflow Interrupt
918
Channel (N) Interrupt
918
Fault Interrupt
919
Introduction
921
Block Diagram
921
Features
922
Signal Description
922
Periodic Interrupt Timer (PIT)
923
Memory Map/Register Description
923
PIT Module Control Register (PIT_MCR)
924
Timer Load Value Register (Pit_Ldvaln)
925
Current Timer Value Register (Pit_Cvaln)
925
Timer Control Register (Pit_Tctrln)
926
Timer Flag Register (Pit_Tflgn)
926
Functional Description
927
General
927
Interrupts
928
Initialization and Application Information
929
Low Power Timer (LPTMR)
931
Introduction
931
Features
931
Modes of Operation
931
LPTMR Signal Descriptions
932
Detailed Signal Descriptions
932
Memory Map and Register Definition
933
Low Power Timer Control Status Register (Lptmrx_Csr)
934
Low Power Timer Prescale Register (Lptmrx_Psr)
935
Low Power Timer Compare Register (Lptmrx_Cmr)
937
Low Power Timer Counter Register (Lptmrx_Cnr)
937
Functional Description
938
LPTMR Power and Reset
938
LPTMR Clocking
938
LPTMR Prescaler/Glitch Filter
939
LPTMR Compare
940
LPTMR Counter
940
LPTMR Hardware Trigger
941
LPTMR Interrupt
941
Carrier Modulator Transmitter (CMT)
943
Introduction
943
Features
943
Block Diagram
944
Modes of Operation
945
Wait Mode Operation
946
Stop Mode Operation
946
CMT External Signal Descriptions
947
CMT_IRO - Infrared Output
947
Memory Map/Register Definition
947
CMT Carrier Generator High Data Register 1 (CMT_CGH1)
948
CMT Carrier Generator Low Data Register 1 (CMT_CGL1)
949
CMT Carrier Generator High Data Register 2 (CMT_CGH2)
950
CMT Carrier Generator Low Data Register 2 (CMT_CGL2)
950
CMT Output Control Register (CMT_OC)
951
CMT Modulator Status and Control Register (CMT_MSC)
952
CMT Modulator Data Register Mark High (CMT_CMD1)
953
CMT Modulator Data Register Mark Low (CMT_CMD2)
954
CMT Modulator Data Register Space High (CMT_CMD3)
954
CMT Modulator Data Register Space Low (CMT_CMD4)
955
CMT Primary Prescaler Register (CMT_PPS)
955
CMT Direct Memory Access (CMT_DMA)
956
Functional Description
957
Clock Divider
957
Carrier Generator
957
Modulator
960
Extended Space Operation
964
CMT Interrupts and DMA
965
Real Time Clock (RTC)
967
Introduction
967
Features
967
Modes of Operation
967
RTC Signal Descriptions
968
Register Definition
968
RTC Time Seconds Register (RTC_TSR)
969
RTC Time Prescaler Register (RTC_TPR)
970
RTC Time Alarm Register (RTC_TAR)
970
RTC Time Compensation Register (RTC_TCR)
971
RTC Control Register (RTC_CR)
972
RTC Status Register (RTC_SR)
974
RTC Lock Register (RTC_LR)
975
RTC Interrupt Enable Register (RTC_IER)
976
RTC Write Access Register (RTC_WAR)
977
RTC Read Access Register (RTC_RAR)
978
Functional Description
979
Power, Clocking and Reset
979
Time Counter
980
Compensation
981
Time Alarm
982
Update Mode
982
Register Lock
982
Access Control
983
Interrupt
983
CAN (Flexcan)
985
Introduction
985
Overview
986
Flexcan Module Features
987
Modes of Operation
988
Flexcan Signal Descriptions
990
CAN Rx
990
CAN Tx
990
Memory Map/Register Definition
990
Flexcan Memory Mapping
990
Module Configuration Register (Canx_Mcr)
994
Control 1 Register (Canx_Ctrl1)
999
Free Running Timer (Canx_Timer)
1002
Rx Mailboxes Global Mask Register (Canx_Rxmgmask)
1003
Rx 14 Mask Register (Canx_Rx14Mask)
1004
Rx 15 Mask Register (Canx_Rx15Mask)
1005
Error Counter (Canx_Ecr)
1005
Error and Status 1 Register (Canx_Esr1)
1007
Interrupt Masks 2 Register (Canx_Imask2)
1011
Interrupt Masks 1 Register (Canx_Imask1)
1012
Interrupt Flags 2 Register (Canx_Iflag2)
1012
Interrupt Flags 1 Register (Canx_Iflag1)
1013
Control 2 Register (Canx_Ctrl2)
1015
Error and Status 2 Register (Canx_Esr2)
1019
CRC Register (Canx_Crcr)
1020
Rx FIFO Global Mask Register (Canx_Rxfgmask)
1020
Rx FIFO Information Register (Canx_Rxfir)
1021
Rx Individual Mask Registers (Canx_Rximrn)
1022
Message Buffer Structure
1023
Rx FIFO Structure
1030
Functional Description
1033
Transmit Process
1033
Arbitration Process
1034
Receive Process
1038
Matching Process
1040
Move Process
1044
Data Coherence
1046
Rx FIFO
1050
CAN Protocol Related Features
1051
Modes of Operation Details
1058
Interrupts
1062
Bus Interface
1063
Initialization/Application Information
1064
Flexcan Initialization Sequence
1064
Spi (Dspi)
1067
Introduction
1067
Block Diagram
1067
Features
1068
DSPI Configurations
1069
Modes of Operation
1070
DSPI Signal Descriptions
1072
PCS0/SS - Peripheral Chip Select/Slave Select
1072
PCS1 - PCS3 - Peripheral Chip Selects 1 - 3
1072
PCS4 - Peripheral Chip Select 4
1073
PCS5/PCSS - Peripheral Chip Select 5/Peripheral Chip Select Strobe
1073
SIN - Serial Input
1073
SOUT - Serial Output
1073
SCK - Serial Clock
1073
Memory Map/Register Definition
1074
DSPI Module Configuration Register (Spix_Mcr)
1076
DSPI Transfer Count Register (Spix_Tcr)
1079
DSPI Clock and Transfer Attributes Register (in Master Mode) (Spix_Ctarn)
1079
DSPI Clock and Transfer Attributes Register (in Slave Mode) (Spix_Ctarn_Slave)
1084
DSPI Status Register (Spix_Sr)
1085
DSPI Dma/Interrupt Request Select and Enable Register (Spix_Rser)
1088
DSPI PUSH TX FIFO Register in Master Mode (Spix_Pushr)
1090
DSPI PUSH TX FIFO Register in Slave Mode (Spix_Pushr_Slave)
1091
DSPI POP RX FIFO Register (Spix_Popr)
1092
DSPI Transmit FIFO Registers (Spix_Txfrn)
1093
DSPI Receive FIFO Registers (Spix_Rxfrn)
1094
Functional Description
1094
Start and Stop of DSPI Transfers
1095
Serial Peripheral Interface (SPI) Configuration
1096
DSPI Baud Rate and Clock Delay Generation
1100
Transfer Formats
1103
Continuous Serial Communications Clock
1108
Slave Mode Operation Constraints
1110
Interrupts/Dma Requests
1111
Power Saving Features
1113
Initialization/Application Information
1114
How to Manage DSPI Queues
1114
Switching Master and Slave Mode
1115
Baud Rate Settings
1115
Delay Settings
1116
Calculation of FIFO Pointer Addresses
1117
Inter-Integrated Circuit (I2C)
1121
Introduction
1121
Features
1121
Modes of Operation
1122
Block Diagram
1122
I2C Signal Descriptions
1123
Memory Map and Register Descriptions
1123
I2C Address Register 1 (I2Cx_A1)
1125
I2C Frequency Divider Register (I2Cx_F)
1125
I2C Control Register 1 (I2Cx_C1)
1126
I2C Status Register (I2Cx_S)
1128
I2C Data I/O Register (I2Cx_D)
1130
I2C Control Register 2 (I2Cx_C2)
1131
I2C Programmable Input Glitch Filter Register (I2Cx_Flt)
1132
I2C Range Address Register (I2Cx_Ra)
1132
I2C Smbus Control and Status Register (I2Cx_Smb)
1133
I2C Address Register 2 (I2Cx_A2)
1134
I2C SCL Low Timeout Register High (I2Cx_Slth)
1135
I2C SCL Low Timeout Register Low (I2Cx_Sltl)
1135
Functional Description
1136
I2C Protocol
1136
10-Bit Address
1141
Address Matching
1142
System Management Bus Specification
1143
Resets
1146
Interrupts
1146
Programmable Input Glitch Filter
1148
Address Matching Wakeup
1148
DMA Support
1149
Initialization/Application Information
1149
Universal Asynchronous Receiver/Transmitter (UART)
1153
Introduction
1153
Features
1153
Modes of Operation
1155
UART Signal Descriptions
1156
Detailed Signal Descriptions
1156
Memory Map and Registers
1157
UART Baud Rate Registers:high (Uartx_Bdh)
1164
UART Baud Rate Registers: Low (Uartx_Bdl)
1165
UART Control Register 1 (Uartx_C1)
1166
UART Control Register 2 (Uartx_C2)
1167
UART Status Register 1 (Uartx_S1)
1169
UART Status Register 2 (Uartx_S2)
1172
UART Control Register 3 (Uartx_C3)
1174
UART Data Register (Uartx_D)
1176
UART Match Address Registers 1 (Uartx_Ma1)
1177
UART Match Address Registers 2 (Uartx_Ma2)
1178
UART Control Register 4 (Uartx_C4)
1178
UART Control Register 5 (Uartx_C5)
1179
UART Extended Data Register (Uartx_Ed)
1180
UART Modem Register (Uartx_Modem)
1181
UART Infrared Register (Uartx_Ir)
1183
UART FIFO Parameters (Uartx_Pfifo)
1184
UART FIFO Control Register (Uartx_Cfifo)
1185
UART FIFO Status Register (Uartx_Sfifo)
1186
UART FIFO Transmit Watermark (Uartx_Twfifo)
1188
UART FIFO Transmit Count (Uartx_Tcfifo)
1188
UART FIFO Receive Watermark (Uartx_Rwfifo)
1189
UART FIFO Receive Count (Uartx_Rcfifo)
1190
UART 7816 Control Register (Uartx_C7816)
1190
UART 7816 Interrupt Enable Register (Uartx_Ie7816)
1192
UART 7816 Interrupt Status Register (Uartx_Is7816)
1193
UART 7816 Wait Parameter Register (Uartx_Wp7816T0)
1195
UART 7816 Wait Parameter Register (Uartx_Wp7816T1)
1195
UART 7816 Wait N Register (Uartx_Wn7816)
1196
UART 7816 Wait FD Register (Uartx_Wf7816)
1197
UART 7816 Error Threshold Register (Uartx_Et7816)
1197
UART 7816 Transmit Length Register (Uartx_Tl7816)
1198
Functional Description
1199
Transmitter
1199
Receiver
1204
Baud Rate Generation
1218
Data Format (Non ISO-7816)
1220
Single-Wire Operation
1223
Loop Operation
1224
Smartcard Support
1224
Infrared Interface
1229
Reset
1230
System Level Interrupt Sources
1230
RXEDGIF Description
1231
DMA Operation
1232
Application Information
1232
Transmit/Receive Data Buffer Operation
1232
Initialization Sequence
1233
Initialization Sequence (Non ISO-7816)
1235
Overrun (OR) Flag Implications
1236
Overrun NACK Considerations
1237
Match Address Registers
1238
Modem Feature
1238
Irda Minimum Pulse Width
1239
Clearing 7816 Wait Timer (WT, BWT, CWT) Interrupts
1239
Legacy and Reverse Compatibility Considerations
1240
Secured Digital Host Controller (SDHC)
1241
Introduction
1241
Overview
1241
Supported Types of Cards
1241
SDHC Block Diagram
1242
Features
1243
Modes and Operations
1244
SDHC Signal Descriptions
1245
Memory Map and Register Definition
1246
DMA System Address Register (SDHC_DSADDR)
1247
Block Attributes Register (SDHC_BLKATTR)
1248
Command Argument Register (SDHC_CMDARG)
1249
Transfer Type Register (SDHC_XFERTYP)
1250
Command Response 0 (SDHC_CMDRSP0)
1254
Command Response 1 (SDHC_CMDRSP1)
1255
Command Response 2 (SDHC_CMDRSP2)
1255
Command Response 3 (SDHC_CMDRSP3)
1255
Buffer Data Port Register (SDHC_DATPORT)
1257
Present State Register (SDHC_PRSSTAT)
1257
Protocol Control Register (SDHC_PROCTL)
1262
System Control Register (SDHC_SYSCTL)
1266
Interrupt Status Register (SDHC_IRQSTAT)
1269
Interrupt Status Enable Register (SDHC_IRQSTATEN)
1275
Interrupt Signal Enable Register (SDHC_IRQSIGEN)
1278
Auto CMD12 Error Status Register (SDHC_AC12ERR)
1280
Host Controller Capabilities (SDHC_HTCAPBLT)
1283
Watermark Level Register (SDHC_WML)
1285
Force Event Register (SDHC_FEVT)
1285
ADMA Error Status Register (SDHC_ADMAES)
1288
ADMA System Address Register (SDHC_ADSADDR)
1290
Vendor Specific Register (SDHC_VENDOR)
1290
MMC Boot Register (SDHC_MMCBOOT)
1292
Host Controller Version (SDHC_HOSTVER)
1293
Functional Description
1294
Data Buffer
1294
DMA Crossbar Switch Interface
1300
SD Protocol Unit
1306
Clock & Reset Manager
1308
Clock Generator
1309
SDIO Card Interrupt
1309
Card Insertion and Removal Detection
1311
Power Management and Wakeup Events
1312
MMC Fast Boot
1313
Initialization/Application of SDHC
1315
Command Send and Response Receive Basic Operation
1315
Card Identification Mode
1316
Card Access
1321
Switch Function
1332
ADMA Operation
1334
Fast Boot Operation
1335
Commands for MMC/SD/SDIO/CE-ATA
1339
Software Restrictions
1345
Initialization Active
1345
Software Polling Procedure
1346
Suspend Operation
1346
Data Length Setting
1346
A)DMA Address Setting
1346
Data Port Access
1347
Change Clock Frequency
1347
Multi-Block Read
1347
Integrated Interchip Sound (I2S)
1349
Introduction
1349
Block Diagram
1350
Features
1350
Modes of Operation
1351
I2S Signal Descriptions
1353
Memory Map/Register Definition
1357
S Transmit Data Registers 0 (I2Sx_Tx0)
1359
S Transmit Data Registers 1 (I2Sx_Tx1)
1359
S Receive Data Registers 0 (I2Sx_Rx0)
1360
S Receive Data Registers 1 (I2Sx_Rx1)
1360
S Control Register (I2Sx_Cr)
1361
S Interrupt Status Register (I2Sx_Isr)
1364
S Interrupt Enable Register (I2Sx_Ier)
1369
S Transmit Configuration Register (I2Sx_Tcr)
1373
S Receive Configuration Register (I2Sx_Rcr)
1375
S Transmit Clock Control Registers (I2Sx_Tccr)
1377
S Receive Clock Control Registers (I2Sx_Rccr)
1379
S FIFO Control/Status Register (I2Sx_Fcsr)
1380
S AC97 Control Register (I2Sx_Acnt)
1386
S AC97 Command Address Register (I2Sx_Acadd)
1387
S AC97 Command Data Register (I2Sx_Acdat)
1388
S AC97 Tag Register (I2Sx_Atag)
1388
S Transmit Time Slot Mask Register (I2Sx_Tmsk)
1389
S Receive Time Slot Mask Register (I2Sx_Rmsk)
1389
S AC97 Channel Status Register (I2Sx_Accst)
1390
S AC97 Channel Enable Register (I2Sx_Accen)
1390
I 2 S AC97 Channel Disable Register (I2Sx_Accdis)
1391
Functional Description
1391
Detailed Operating Mode Descriptions
1391
I2S Clocking
1407
External Frame and Clock Operation
1412
Receive Interrupt Enable Bit Description
1414
Transmit Interrupt Enable Bit Description
1415
Internal Frame and Clock Shutdown
1416
Reset
1417
Initialization/Application Information
1417
Introduction
1421
Features
1421
Modes of Operation
1421
GPIO Signal Descriptions
1422
Memory Map and Register Definition
1423
Port Data Output Register (Gpiox_Pdor)
1426
Port Set Output Register (Gpiox_Psor)
1426
Port Clear Output Register (Gpiox_Pcor)
1427
Port Toggle Output Register (Gpiox_Ptor)
1427
Port Data Input Register (Gpiox_Pdir)
1428
Port Data Direction Register (Gpiox_Pddr)
1428
Functional Description
1429
General Purpose Input
1429
General Purpose Output
1429
Touch Sense Input (TSI)
1431
Introduction
1431
Features
1431
Overview
1432
Electrode Capacitance Measurement Unit
1432
Electrode Scan Unit
1433
Touch Detection Unit
1434
Modes of Operation
1434
TSI Disabled Mode
1434
TSI Active Mode
1434
TSI Low Power Mode
1435
Block Diagram
1435
TSI Signal Descriptions
1436
Tsi_In[15:0]
1436
Memory Map and Register Definition
1436
General Control and Status Register (Tsix_Gencs)
1438
SCAN Control Register (Tsix_Scanc)
1441
Pin Enable Register (Tsix_Pen)
1444
Status Register (Tsix_Status)
1447
Counter Register (Tsix_Cntrn)
1450
Channel N Threshold Register (Tsix_Threshldn)
1451
Functional Descriptions
1451
Capacitance Measurement
1451
TSI Measurement Result
1454
Electrode Scan Unit
1455
Touch Detection Unit
1458
Application Information
1459
TSI Module Sensitivity
1459
LCD Controller (SLCD)
1461
Introduction
1461
Features
1461
Modes of Operation
1462
Block Diagram
1463
LCD Signal Descriptions
1464
Lcd_P[63:0]
1465
Vll1, Vll2, Vll3
1465
Vcap1, Vcap2
1465
Memory Map and Register Definition
1465
LCD General Control Register (LCD_GCR)
1467
LCD Auxiliary Register (LCD_AR)
1471
LCD Fault Detect Control Register (LCD_FDCR)
1473
LCD Fault Detect Status Register (LCD_FDSR)
1474
LCD Pin Enable Register (Lcd_Penn)
1475
LCD Backplane Enable Register (Lcd_Bpenn)
1476
LCD Waveform Register (LCD_WF3TO0)
1477
LCD Waveform Register (LCD_WF7TO4)
1478
LCD Waveform Register (LCD_WF11TO8)
1478
LCD Waveform Register (LCD_WF15TO12)
1479
LCD Waveform Register (LCD_WF19TO16)
1480
LCD Waveform Register (LCD_WF23TO20)
1480
LCD Waveform Register (LCD_WF27TO24)
1481
LCD Waveform Register (LCD_WF31TO28)
1482
LCD Waveform Register (LCD_WF35TO32)
1482
LCD Waveform Register (LCD_WF39TO36)
1483
LCD Waveform Register (LCD_WF43TO40)
1484
LCD Waveform Register (LCD_WF47TO44)
1484
LCD Waveform Register (LCD_WF51TO48)
1485
LCD Waveform Register (LCD_WF55TO52)
1485
LCD Waveform Register (LCD_WF59TO56)
1486
LCD Waveform Register (LCD_WF63TO60)
1487
Functional Description
1487
LCD Controller Driver Description
1488
Wfytox Registers
1498
LCD Display Modes
1498
LCD Charge Pump and Power Supply Operation
1500
Resets
1505
Interrupts
1505
LCD Display Fault Detect Circuit
1506
Initialization Section
1513
Initialization Sequence
1513
Initialization Examples
1514
Application Information
1520
LCD Seven Segment Example Description
1521
LCD Contrast Control
1524
JTAG Controller (JTAGC)
1527
Introduction
1527
Block Diagram
1527
Features
1528
Modes of Operation
1528
External Signal Description
1530
TCK-Test Clock Input
1530
TDI-Test Data Input
1530
TDO-Test Data Output
1530
TMS-Test Mode Select
1530
Register Description
1531
Instruction Register
1531
Bypass Register
1531
Device Identification Register
1531
Boundary Scan Register
1532
Functional Description
1533
JTAGC Reset Configuration
1533
IEEE 1149.1-2001 (JTAG) Test Access Port
1533
TAP Controller State Machine
1533
JTAGC Block Instructions
1535
Boundary Scan
1538
Initialization/Application Information
1538

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