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Manuals and User Guides for Nuvoton NuMicro M0A23OC1AC. We have
1
Nuvoton NuMicro M0A23OC1AC manual available for free PDF download: Technical Reference Manual
Nuvoton NuMicro M0A23OC1AC Technical Reference Manual (746 pages)
Arm Cortex -M0-based Microcontroller
Brand:
Nuvoton
| Category:
Microcontrollers
| Size: 9 MB
Table of Contents
Table of Contents
2
General Description
17
Table 1-1 Numicro ® M0A21/M0A23 Series Key Features Table
17
Features
18
Parts Information
26
Package Type
26
Numicro M0A21/M0A23 Series Selection Guide
27
Numicro ® M0A21 Series
27
Numicro ® M0A23 Series
27
Numicro ® M0A21/M0A23 Selection Code
28
Pin Configuration
29
M0A21 Series Pin Diagram
29
Figure 4.1-1 M0A21 Series SSOP 20-Pin Diagram
29
M0A21 Series Function Pin Table
30
Figure 4.1-2 M0A21 Series TSSOP 28-Pin Diagram
30
M0A23 Series Pin Diagram
38
Figure 4.1-3 M0A23 Series SSOP 20-Pin Diagram
38
Figure 4.1-4 M0A23 Series TSSOP 28-Pin Diagram
39
M0A23 Series Function Pin Table
40
Pin Description
44
M0A21/M0A23 Series Pin Description
44
M0A21/M0A23 Series Multi-Function Summary Table
62
M0A21/M0A23 Series Multi-Function Summary Table Sorted by GPIO
80
Block Diagram
98
Figure 4.2-1 Numicro M0A21/M0A23 Block Diagram
98
Functional Description
99
Arm ® Cortex ® -M0 Core
99
Figure 6.1-1 Functional Block Diagram
99
System Manager
101
Overview
101
System Reset
101
Figure 6.2-1 System Reset Sources
102
Table 6.2-1 Reset Value of Registers
103
Figure 6.2-2 Nreset Reset Waveform
104
Figure 6.2-3 Nreset Reset Mode Enable Control Waveform
104
Figure 6.2-4 Power-On Reset (POR) Waveform
105
Figure 6.2-5 Low Voltage Reset (LVR) Waveform
105
Figure 6.2-6 Brown-Out Detector (BOD) Waveform
106
System Power Distribution
107
Power Modes and Wake-Up Sources
107
Figure 6.2-7 Numicro
107
Table 6.2-2 Power Mode Table
108
Table 6.2-3 Power Mode Difference Table
108
Table 6.2-4 Power Mode Difference Table
108
Figure 6.2-8 Power Mode State Machine
109
Table 6.2-5 Clocks in Power Modes
110
System Memory Map
111
Table 6.2-6 Condition of Entering Power-Down Mode Again
111
Table 6.2-7 Address Space Assignments for On-Chip Controllers
112
SRAM Memory Orginization
113
Figure 6.2-9 SRAM Memory Organization
113
Chip Bus Matrix
114
IRC Auto Trim
114
Figure 6.2-10 Numicro M0A21/M0A23 Bus Matrix Diagram
114
Register Lock Control
115
UART0_TXD/USCI0_DAT0 Modulation with PWM
115
Register Map
116
Register Description
118
System Timer (Systick)
151
Nested Vectored Interrupt Controller (NVIC)
156
Table 6.2-8 Exception Model
157
Table 6.2-9 Interrupt Number Table
158
System Control Register
172
Table 6.2-10 Priority Grouping
177
Clock Controller
182
Overview
182
Clock Generator
183
Figure 6.3-1 Clock Generator Global View Diagram
183
Figure 6.3-2 Clock Generator Block Diagram
184
System Clock and Systick Clock
185
Figure 6.3-3 System Clock Block Diagram
185
Peripherals Clock
186
Power-Down Mode Clock
186
Figure 6.3-4 HXT Stop Protect Procedure
186
Figure 6.3-5 Systick Clock Control Block Diagram
186
Clock Output
187
Figure 6.3-6 Clock Output Block Diagram
187
Register Map
188
Register Description
189
Flash Memory Controller (FMC)
208
Overview
208
Features
208
Block Diagram
208
Figure 6.4-116/32 KB Flash Memory Control Block Diagram
209
Functional Description
210
Figure 6.4-2 Data Flash Shared with APROM
210
Figure 6.4-3 16/32 Kbytes Flash Memory Map
216
Figure 6.4-4 16/32 Kbytes Flash System Memory Map with IAP Mode
217
Figure 6.4-5 LDROM with IAP Mode
218
Figure 6.4-6 APROM with IAP Mode
218
Figure 6.4-7 16/32 Kbytes Flash System Memory Map Without IAP Mode
219
Figure 6.4-8 Boot Source Selection
220
Table 6.4-1 Vector Mapping Support
220
Table 6.4-2 ISP Command List
221
Figure 6.4-9 ISP Procedure Example
222
Figure 6.4-10 Example for Accelerating Interrupt by VECMAP
223
Table 6.4-3 FMC Control Registers for Flash Programming
223
Figure 6.4-11 ISP 32-Bit Programming Procedure
224
Figure 6.4-12 CRC-32 Checksum Calculation
225
Figure 6.4-13 CRC-32 Checksum Calculation Flow
226
Register Map
227
Register Description
228
General Purpose I/O (GPIO)
237
Overview
237
Features
237
Block Diagram
238
Basic Configuration
238
Functional Description
238
Figure 6.5-1 GPIO Controller Block Diagram
238
Figure 6.5-2 Input Mode
239
Figure 6.5-3 Push-Pull Output
239
Figure 6.5-4 Open-Drain Output
240
Figure 6.5-5 Quasi-Bidirectional I/O Mode
240
Figure 6.5-6 GPIO Rising Edge Trigger Interrupt
241
Figure 6.5-7 GPIO Falling Edge Trigger Interrupt
242
Register Map
243
Register Description
245
PDMA Controller (PDMA)
259
Overview
259
Features
259
Block Diagram
259
Basic Configuration
259
Figure 6.6-1 PDMA Controller Block Diagram
259
Functional Description
260
Figure 6.6-2 Descriptor Table Entry Structure
260
Figure 6.6-3 Basic Mode Finite State Machine
261
Table 6.6-1 Channel Priority Table
261
Figure 6.6-4 Descriptor Table Link List Structure
262
Figure 6.6-5 Scatter-Gather Mode Finite State Machine
263
Figure 6.6-6 Example of Single Transfer Type and Burst Transfer Type in Basic Mode
264
Figure 6.6-7 Example of PDMA Channel 0 Time-Out Counter Operation
265
Register Map
266
Register Description
267
Timer Controller (TMR)
294
Overview
294
Features
294
Block Diagram
295
Figure 6.7-1 Timer Controller Block Diagram
295
Basic Configuration
296
Figure 6.7-2 Clock Source of Timer Controller
296
Functional Description
297
Table 6.7-1 Timer0 ~ Timer3 MFP Table
297
Figure 6.7-3 Continuous Counting Mode
298
Figure 6.7-4 External Capture Mode
299
Figure 6.7-5 Reset Counter Mode
300
Figure 6.7-6 Internal Timer Trigger
301
Figure 6.7-7 Inter-Timer Trigger Capture Timing
302
Register Map
304
Register Description
306
Watchdog Timer (WDT)
317
Overview
317
Features
317
Block Diagram
317
Basic Configuration
317
Figure 6.8-1 Watchdog Timer Block Diagram
317
Functional Description
318
Figure 6.8-2 Watchdog Timer Clock Control
318
Figure 6.8-3 Watchdog Timer Time-Out Interval and Reset Period Timing
319
Table 6.8-1 Watchdog Timer Time-Out Interval Period Selection
319
Register Map
321
Register Description
322
Window Watchdog Timer (WWDT)
326
Overview
326
Features
326
Block Diagram
326
Basic Configuration
326
Figure 6.9-1 WWDT Block Diagram
326
Figure 6.9-2 WWDT Clock Control
326
Functional Description
327
Table 6.9-1 WWDT Prescaler Value Selection
327
Figure 6.9-3 WWDT Reset and Reload Behavior
328
Figure 6.9-4 WWDT Reload Counter When CNTDAT > CMPDAT
328
Figure 6.9-5 WWDT Reload Counter When WWDT_CNT < WINCMP
329
Figure 6.9-6 WWDT Interrupt and Reset Signals
329
Table 6.9-2 CMPDAT Setting Limitation
330
Register Map
331
Register Description
332
PWM Generator and Capture Timer (PWM)
337
Overview
337
Features
337
Block Diagram
338
Figure 6.10-1 PWM Generator Overview Block Diagram
338
Figure 6.10-2 PWM System Clock Source Control
338
Table 6.10-1 PWM Clock Source Control Registers Setting Table
339
Figure 6.10-3 PWM Clock Source Control
340
Figure 6.10-4 PWM Independent Mode Architecture Diagram
340
Basic Configuration
341
Figure 6.10-5 PWM Complementary Mode Architecture Diagram
341
Functional Description
343
Figure 6.10-6 PWM0_CH0 Prescaler Waveform in up Counter Type
344
Figure 6.10-7 Pwmx Counter Waveform When Setting Clear Counter
344
Figure 6.10-8 PWM up Counter Type
345
Figure 6.10-9 PWM down Counter Type
345
Figure 6.10-10 PWM Up-Down Counter Type
346
Figure 6.10-11 PWM Compared Point Events in Up-Down Counter Type
347
Figure 6.10-12 PWM Double Buffering Illustration
348
Figure 6.10-13 Period Loading in Up-Count Mode
348
Figure 6.10-14 Immediately Loading in Up-Count Mode
349
Figure 6.10-15 Center Loading in Up-Down-Count Mode
350
Figure 6.10-16 PWM Pulse Generation
351
Figure 6.10-17 PWM 0% to 100% Pulse Generation
351
Table 6.10-2 PWM Pulse Generation Event Priority for Up-Counter
351
Figure 6.10-18 PWM Independent Mode Waveform
352
Table 6.10-3 PWM Pulse Generation Event Priority for Down-Counter
352
Table 6.10-4 PWM Pulse Generation Event Priority for Up-Down-Counter
352
Figure 6.10-19 PWM Complementary Mode Waveform
353
Figure 6.10-20 Pwmx_Ch0 Output Control in Independent Mode
353
Figure 6.10-21 Pwmx_Ch0 and Pwmx_Ch1 Output Control in Complementary Mode
354
Figure 6.10-22 Dead-Time Insertion
354
Figure 6.10-23 Illustration of Mask Control Waveform
355
Figure 6.10-24 Brake Noise Filter Block Diagram
355
Figure 6.10-25 Brake Block Diagram for Pwmx_Ch0 and Pwmx_Ch1 Pair
356
Figure 6.10-26 Edge Detector Waveform for Pwmx_Ch0 and Pwmx_Ch1 Pair
357
Figure 6.10-27 Level Detector Waveform for Pwmx_Ch0 and Pwmx_Ch1 Pair
357
Figure 6.10-28 Brake Source Block Diagram
358
Figure 6.10-29 Brake System Fail Block Diagram
358
Figure 6.10-30 Initial State and Polarity Control with Rising Edge Dead-Time Insertion
359
Figure 6.10-31 PWM_CH0 and PWM_CH1 Pair Interrupt Architecture Diagram
360
Figure 6.10-32 Pwmx_Ch0 and Pwmx_Ch1 Pair Trigger ADC Block Diagram
361
Figure 6.10-33 PWM Trigger ADC in Up-Down Counter Type Timing Waveform
361
Figure 6.10-34 PWM_CH0 Capture Block Diagram
362
Figure 6.10-35 Capture Operation Waveform
363
Figure 6.10-36 Capture PDMA Operation Waveform of Channel 0
364
Register Map
365
Register Description
368
UART Interface Controller (UART)
416
Overview
416
Features
416
Block Diagram
417
Table 6.11-1 Numicro M0A21/M0A23 Series UART Features
417
Figure 6.11-1 UART Clock Control Diagram
418
Figure 6.11-2 UART Block Diagram
419
Basic Configuration
420
Table 6.11-2 UART Interrupt
420
Functional Description
421
Table 6.11-3 UART Interface Controller Pin
421
Table 6.11-4 UART Controller Baud Rate Equation Table
422
Table 6.11-5 UART Controller Baud Rate Parameter Setting Example Table
422
Table 6.11-6 UART Controller Baud Rate Register Setting Example Table
423
Table 6.11-7 Baud Rate Compensation Example Table 1
423
Table 6.11-8 Baud Rate Compensation Example Table 2
424
Figure 6.11-3 Auto-Baud Rate Measurement
425
Figure 6.11-4 Transmit Delay Time Operation
425
Figure 6.11-5 UART Ncts Wake-Up Case1
426
Figure 6.11-6 UART Ncts Wake-Up Case2
426
Figure 6.11-7 UART Data Wake-Up
427
Figure 6.11-8 UART Received Data FIFO Reached Threshold Wake-Up
427
Figure 6.11-9 UART RS-485 AAD Mode Address Match Wake-Up
428
Figure 6.11-10 UART Received Data FIFO Threshold Time-Out Wake-Up
428
Table 6.11-9 UART Controller Interrupt Source and Flag List
430
Table 6.11-10 UART Line Control of Word and Stop Length Setting
431
Table 6.11-11 UART Line Control of Parity Bit Setting
431
Figure 6.11-11 Auto-Flow Control Block Diagram
432
Figure 6.11-12 UART Ncts Auto-Flow Control Enabled
432
Figure 6.11-13 UART Nrts Auto-Flow Control Enabled
433
Figure 6.11-14 UART Nrts Auto-Flow with Software Control
433
Figure 6.11-15 Irda Control Block Diagram
434
Figure 6.11-16 Irda TX/RX Timing Diagram
435
Figure 6.11-17 Structure of LIN Frame
435
Figure 6.11-18 Structure of LIN Byte
436
Table 6.11-12 LIN Header Selection in Master Mode
436
Figure 6.11-19 Break Detection in LIN Mode
438
Figure 6.11-20 LIN Frame ID and Parity Format
438
Figure 6.11-21 LIN Sync Field Measurement
440
Figure 6.11-22 UART_BAUD Update Sequence in AR Mode if SLVDUEN Is 1
441
Figure 6.11-23 UART_BAUD Update Sequence in AR Mode if SLVDUEN Is 0
441
Figure 6.11-24 RS-485 Nrts Driving Level in Auto Direction Mode
443
Figure 6.11-25 RS-485 Nrts Driving Level with Software Control
444
Figure 6.11-26 Structure of RS-485 Frame
444
Register Map
446
Register Description
448
USCI - Universal Serial Control Interface Controller (USCI)
485
Overview
485
Features
485
Block Diagram
485
Functional Description
485
Figure 6.12-1 USCI Block Diagram
485
Figure 6.12-2 Input Conditioning for Uscix_Dat[1:0] and Uscix_Ctl[1:0]
486
Table 6.12-1 Input Signals for Different Protocols
486
Figure 6.12-3 Input Conditioning for Uscix_Clk
487
Table 6.12-2 Output Signals for Different Protocols
487
Figure 6.12-4 Block Diagram of Data Buffering
488
Figure 6.12-5 Data Access Structure
489
Figure 6.12-6 Transmit Data Path
489
Figure 6.12-7 Receive Data Path
490
Figure 6.12-8 Protocol-Relative Clock Generator
491
Figure 6.12-9 Basic Clock Divider Counter
492
Figure 6.12-10 Block of Timing Measurement Counter
492
Figure 6.12-11 Sample Time Counter
493
Figure 6.12-12 Event and Interrupt Structure
494
Table 6.12-3 Data Transfer Events and Interrupt Handling
494
Table 6.12-4 Protocol-Specific Events and Interrupt Handling
494
USCI - UART Mode
496
Overview
496
Features
496
Block Diagram
496
Basic Configuration
496
Figure 6.13-1 USCI-UART Mode Block Diagram
496
Functional Description
498
Figure 6.13-2 UART Signal Connection for Full-Duplex Communication
498
Figure 6.13-3 UART Standard Frame Format
499
Table 6.13-1 Input Signals for UART Protocol
499
Table 6.13-2 Output Signals for Different Protocol
499
Figure 6.13-4 UART Bit Timing (Data Sample Time)
501
Figure 6.13-5 UART Auto Baud Rate Control
503
Figure 6.13-6 Incoming Data Wake-Up
504
Figure 6.13-7 Ncts Wake-Up Case 1
504
Figure 6.13-8 Ncts Wake-Up Case 2
504
Register Map
507
Register Description
508
USCI - SPI Mode
529
Overview
529
Features
529
Figure 6.14-1 SPI Master Mode Application Block Diagram
529
Figure 6.14-2 SPI Slave Mode Application Block Diagram
529
Block Diagram
530
Basic Configuration
530
Figure 6.14-3 USCI SPI Mode Block Diagram
530
Functional Description
531
Figure 6.14-44-Wire Full-Duplex SPI Communication Signals (Master Mode)
532
Figure 6.14-54-Wire Full-Duplex SPI Communication Signals (Slave Mode)
532
Figure 6.14-6 SPI Communication with Different SPI Clock Configuration (Sclkmode=0X0)
533
Table 6.14-1 Serial Bus Clock Configuration
533
Figure 6.14-7 SPI Communication with Different SPI Clock Configuration (Sclkmode=0X1)
534
Figure 6.14-8 SPI Communication with Different SPI Clock Configuration (Sclkmode=0X2)
534
Figure 6.14-9 SPI Communication with Different SPI Clock Configuration (Sclkmode=0X3)
535
Figure 6.14-1016-Bit Data Length in One Word Transaction with MSB First Format
536
Figure 6.14-11 Word Suspend Interval between Two Transaction Words
536
Figure 6.14-12 Auto Slave Select (SUSPITV ≧ 0X3)
537
Figure 6.14-13 Auto Slave Select (SUSPITV < 0X3)
537
Figure 6.14-14 One Output Data Channel Half-Duplex (SPI Master Mode)
538
Figure 6.14-15 One Input Data Channel Half-Duplex (SPI Master Mode)
539
Figure 6.14-16 SPI Timing in Master Mode
540
Figure 6.14-17 SPI Timing in Master Mode (Alternate Phase of Serial Bus Clock)
541
Figure 6.14-18 SPI Timing in Slave Mode
541
Figure 6.14-19 SPI Timing in Slave Mode (Alternate Phase of Serial Bus Clock)
542
Register Map
543
Register Description
545
USCI - I 2 C Mode
567
Overview
567
Features
567
Figure 6.15-1 I 2 C Bus Timing
567
Block Diagram
568
Basic Configuration
568
Figure 6.15-2 USCI I²C Mode Block Diagram
568
START or Repeated START Signal
569
Figure 6.15-3 I 2 C Protocol
569
Figure 6.15-4 START and STOP Conditions
570
Figure 6.15-5 Bit Transfer on the I C Bus
571
Figure 6.15-6 Acknowledge on the I 2 C Bus
571
Figure 6.15-7 Arbitration Lost
572
Figure 6.15-8 Control I
575
Figure 6.15-9 Master Transmits Data to Slave with a 7-Bit Address
575
Figure 6.15-10 Master Reads Data from Slave with a 7-Bit Address
575
Figure 6.15-11 Master Transmits Data to Slave by 10-Bit Address
575
Figure 6.15-12 Master Reads Data from Slave by 10-Bit Address
576
Figure 6.15-13 Master Transmitter Mode Control Flow with 7-Bit Address
576
Figure 6.15-14 Master Receiver Mode Control Flow with 7-Bit Address
577
Figure 6.15-15 Master Transmitter Mode Control Flow with 10-Bit Address
578
Figure 6.15-16 Master Recevier Mode Control Flow with 10-Bit Address
579
Figure 6.15-17 Save Mode Control Flow with 7-Bit Address
580
Figure 6.15-18 Save Mode Control Flow with 10-Bit Address
581
Figure 6.15-19 GC Mode with 7-Bit Address
582
Figure 6.15-20 Setup Time Wrong Adjustment
584
Figure 6.15-21 Hold Time Wrong Adjustment
584
Table 6.15-1 Relationship between I
584
Figure 6.15-22 I 2 C Time-Out Count Block Diagram
585
Figure 6.15-23 EEPROM Random Read
586
Figure 6.15-24 Protocol of EEPROM Random Read
586
Register Map
587
Register Description
588
Controller Area Network (CAN)
607
Overview
607
Features
607
Block Diagram
607
Basic Configuration
608
Figure 6.16-1 CAN Peripheral Block Diagram
608
Functional Description
609
Test Mode
610
Figure 6.16-2 CAN Core in Silent Mode
610
Figure 6.16-3 CAN Core in Loop Back Mode
611
Figure 6.16-4 CAN Core in Loop Back Mode Combined with Silent Mode
611
CAN Communications
612
Figure 6.16-5 Data Transfer between Ifn Registers and Message
613
Table 6.16-1 Initialization of a Transmit Object
615
Table 6.16-2 Initialization of a Receive Object
616
Figure 6.16-6 Application Software Handling of a FIFO Buffer
618
Figure 6.16-7 Bit Timing
620
Table 6.16-3 CAN Bit Time Parameters
620
Figure 6.16-8 Propagation Time Segment
621
Figure 6.16-9 Synchronization on "Late" and "Early" Edges
622
Figure 6.16-10 Filtering of Short Dominant Spikes
623
Figure 6.16-11 Structure of the CAN Core's CAN Protocol Controller
624
Register Map
628
Table 6.16-4 CAN Register Map for each Bit Function
632
Register Description
633
Table 6.16-5 Last Error Code
635
Table 6.16-6 Source of Interrupts
639
Table 6.16-7 IF1 and IF2 Message Interface Register
642
Table 6.16-8 Structure of a Message Object in the Message Memory
656
CRC Controller (CRC)
667
Overview
667
Features
667
Block Diagram
667
Basic Configuration
667
Figure 6.17-1 CRC Generator Block Diagram
667
Functional Description
668
Figure 6.17-2 CHECKSUM Bit Order Reverse Functional Block
668
Figure 6.17-3 Write Data Bit Order Reverse Functional Block
669
Register Map
670
Register Description
671
Hardware Divider (HDIV)
676
Overview
676
Features
676
Basic Configuration
676
Functional Description
676
Figure 6.18-1 Hardware Divider Operation Flow
676
Register Map
677
Register Description
678
Analog-To-Digital Converter (ADC)
683
Overview
683
Features
683
Block Diagram
684
Basic Configuration
684
Functional Description
684
Figure 6.19-1 AD Controller Block Diagram
684
Figure 6.19-2 ADC Peripheral Clock Control
685
Figure 6.19-3 Single Mode Conversion Timing Diagram
686
Figure 6.19-4 Burst Mode Conversion Timing Diagram
687
Figure 6.19-5 Single-Cycle Scan Mode on Enabled Channels Timing Diagram
688
Figure 6.19-6 Continuous Scan Mode on Enabled Channels Timing Diagram
689
Figure 6.19-7 A/D Conversion Result Monitor Logic Diagram
690
Figure 6.19-8 A/D Controller Interrupt
691
Register Map
692
Register Description
694
Figure 6.19-9 Conversion Result Mapping Diagram of ADC Single-End Input
695
Figure 6.19-10 Conversion Result Mapping Diagram of ADC Differential Input
696
Digital to Analog Converter (DAC)
708
Overview
708
Features
708
Block Diagram
708
Figure 6.20-1 Digital-To-Analog Converter Block Diagram
708
Basic Configuration
709
Functional Description
709
Figure 6.20-2 DAC Conversion Started by Software Write Trigger
709
Figure 6.20-3 DAC Conversion Started by Hardware Trigger Event
710
Figure 6.20-4 DAC PDMA Underrun Condition Example
711
Figure 6.20-5 DAC Continuous Conversion with Software PDMA Mode
711
Figure 6.20-6 DAC Interrupt Source
712
Register Map
713
Register Description
714
Analog Comparator Controller (ACMP)
721
Overview
721
Features
721
Block Diagram
721
Basic Configuration
722
Figure 6.21-1 Analog Comparator Block Diagram
722
Functional Description
723
Figure 6.21-2 Comparator Hysteresis Function of ACMP0
723
Figure 6.21-3 Window Latch Mode
724
Figure 6.21-4 Filter Function Example
724
Figure 6.21-5 Comparator Controller Interrupt
725
Figure 6.21-6 Comparator Reference Voltage Block Diagram
725
Figure 6.21-7 Example of Window Compare Mode
726
Table 6.21-1 Truth Table of Window Compare Logic
726
Figure 6.21-8 Example of Window Compare Mode
727
Register Map
728
Register Description
729
Peripherals Interconnection
736
Overview
736
Peripherals Interconnect Matrix Table
736
Functional Description
736
Table 6.22-1 Peripherals Interconnect Matrix Table
736
Application Circuit
738
Power Supply Scheme
738
Peripheral Application Scheme
739
Electrical Characteristics
740
Package Dimensions
741
SSOP 20 (5.3X7.2X1.75 MM)
741
TSSOP 28 (4.4X9.7X1.0 MM)
742
Abbreviations
743
Table 10.1-1 List of Abbreviations
744
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