North Atlantic 68C3 Manuals

Manuals and User Guides for North Atlantic 68C3. We have 1 North Atlantic 68C3 manual available for free PDF download: Operation Manual

North Atlantic 68C3 Operation Manual (330 pages)

68C3 3U Open VPX MULTI-FUNCTION I/O CARD

Brand: North Atlantic | Category: I/O Systems | Size: 10.57 MB

Model 68C3

2
Openvpx, Multi-Function I/O Card

2
Features

2
Description

2
General Board Specification

3
- Available Function Modules
  3
Software Support

4
- Table of Contents
  5
Specifications

22
68C3 Address Configuration

48
Product Configuration and Memory Map

49
- 68C3 CARD-LEVEL MODULE CONFIGURATION and MEMORY MAPPING
  50
Arinc 429/575 Six Channel, Tx/Rx (Module A4)

51
- Features
  51
- ARINC 429/575 Overview
  51
- Functional Description
  51
- Receive Operation
  52
- Transmit Operation
  52
- Schedule Transmit Commands
  53
  - Message
    53
  - Gap
    53
  - Fixedgap
    53
  - Pause
    53
  - Interrupt
    54
  - Jump
    54
  - Stop
    54
  - Transient Protection
    54
  - Built-In-Test
    54
  - Loop-Back
    54
- Specifications
  54
- Module Factory Defaults
  55
- Registers and Delays
  55
- Tx (Transmit) Buffer (FIFO)
  56
- Rx (Receive) Buffer (FIFO)
  56
- Rx FIFO (Buffer) Threshold
  57
- Tx FIFO (Buffer) Threshold
  57
- Rx FIFO (Buffer) Level (Number of Rx Buffer Words)
  57
- Tx FIFO (Buffer) Level (Number of Tx Buffer Words)
  57
- Channel Control Low
  58
- Channel Control High
  59
- Channel Status
  60
- Interrupt Enable
  61
- Interrupt Status
  62
- Transmit FIFO Rate (Hi+Lo)
  62
- Mailbox (MBOX) Address Register
  63
- Mailbox (MBOX) Status Register
  63
- Mailbox (MBOX) Data Register
  64
- Receive Data Unbuffered Register
  64
- Transmit Trigger Register
  65
- Transmit Pause Register
  65
- Transmit Stop Register
  66
- Time Stamp Control Register
  66
- Timestamp Hi + lo Register
  67
- Module Reset Register
  67
- Memory Page Register
  67
- Memory
  68
- Tx Message Memory Format
  68
- Tx Schedule Program Memory Format
  68
- Rx Match Memory Layout
  69
- Async Tx Data (Hi + Lo)
  69
- BIT Status Register
  69
- DSP Compile Time
  70
- Interrupt Vector
  70
Module Pci Memory Map - 6 Channel Arinc Communications (A4)

71
1553 Communications (Modules N7 and N8)

72
- Features
  72
- Module Memory Map (Length=40000H)
  72
Canbus Control Area Network (Module P6, Pa)

73
Module (P6) Canbus Can A/B Pci Register Map

85
Module (Pa) Canbus J1939 Pci Register Map

86
Four Channel, Serial (Rs232/422/485) (Module P8) / Isolated Rs-422/Rs-485 (Module Pc)

87
- Serial Communications Specifications
  89
- Communication Module Factory Defaults: Registers and Delays
  90
- Transmit Buffer
  91
- Receive Buffer
  91
- Number of Words Tx Buffer
  91
- Number of Words Rx Buffer
  92
- Protocol
  92
- Clock Mode
  92
- Interface Levels
  93
- Tx-Rx Configuration Low
  94
- Tx-Rx Configuration High
  94
- Channel Control Low
  95
- Channel Control High
  95
- Channel Control Extended
  96
- Data Configuration
  96
- Baud Rate
  97
- Preamble
  97
- Tx Buffer Almost Empty
  97
- Rx Buffer Almost Full
  98
- Rx Buffer High Watermark
  98
- Rx Buffer Low Watermark
  99
- HDLC Rx Address/Sync Character
  99
- HDLC Tx Address/Sync Character
  100
- Termination Character
  100
- XON Character
  100
- XOFF Character
  101
- FIFO Status
  101
- Time out Value
  101
- Interrupt Enable
  102
- Interrupt Status
  103
- Interrupt Vector
  103
- Channel Status
  104
Four Channel Serial Communications (Module P8/Pc) Pci Memory Map

105
A/D (Modules C1, C2, C3, C4 & Ca)

106
- Principle of Operation
  106
- Built-In Test (BIT) / Diagnostic Capability
  106
- Data Read
  107
- Range & Polarity
  107
- Filter Break Frequency
  107
- Latch All A/Ds
  107
- D0 Test Range
  107
- D0 Test Voltage
  108
- Calibration Interval Delay
  108
- FIFO Buffer Operational Description
  108
  - FIFO Buffer Data (Per Channel)
    108
  - Words in FIFO (Per Channel)
    108
  - Hi-Threshold (Per Channel)
    108
  - Low-Threshold (Per Channel)
    108
  - Delay (Per Channel)
    108
  - FIFO Size (Per Channel)
    109
  - Sample Rate (Per Channel)
    109
  - Clear FIFO (Per Channel)
    109
  - Buffer Control (Per Channel)
    109
  - Trigger Control (Per Channel)
    110
  - FIFO Status (Per Channel)
    110
  - Interrupt Enable (Per Channel)
    110
  - Software Trigger (Per Channel)
    111
- Clock Rate Input
  111
- Test Enable
  112
- Test (D2) Verify
  112
- Active Channels
  112
- BIT Status
  112
- Open Status
  113
- BIT Status Interrupt Enable
  113
- Open Status Interrupt Enable
  113
- BIT Interrupt Vector
  113
- Open Interrupt Vector
  113
- FIFO Buffer Interrupt Vector
  113
- Interrupt and Status Register Operation/Clarification
  114
A/D (Modules C1, C2, C3 & C4) Pci Memory Map

115
I/O Digital Ttl/Cmos (Module D7)

116
- Principle of Operation
  116
- Automatic Background Built-In Test (Bit)/Diagnostic Capability
  116
- Write Output
  116
- Read Input or Output
  117
- External VCC Select
  117
- De-Bounce Time
  117
- De-Bounce LSB
  117
- Input/Output Format
  117
- Reset Over-Current
  118
- Status Indications
  118
- Interrupt Vectors
  118
- Interrupt and Status Register Operation/Clarification
  119
I/O Digital Ttl/Cmos (Module D7) Pci Memory Map

120
Differential Multi-Mode Transceivers (Module D8)

121
- Principle of Operation
  121
- Automatic Background Built-In Test (BIT) / Diagnostic Capability
  121
- Write Output
  121
- Read Input or Output
  121
- De-Bounce Time
  122
- De-Bounce LSB
  122
- Slew Rate Mode
  122
- Input Termination Control
  122
- Input/Output Format
  123
- Reset Over-Current
  123
- Status Indications
  123
- Interrupt Vectors
  124
- Interrupt and Status Register Operation/Clarification
  125
I/O (Module D8) Pci Memory Map

126
D/A (Modules F & J, Except J8)

127
- Principle of Operation
  127
- Built-In Test (BIT) / Diagnostic Capability
  127
- Data (Write D/A) Output (F1, F3, J3, J5 Modules)
  127
- Data (Write D/A) Output (F5 Module Only)
  127
- D/A Polarity
  128
- D/A Wrap Voltage
  128
- Filter Function
  128
- Current Reading
  128
- Output Data Trigger
  128
- Reset to Zero
  128
- Retry Overload
  128
- Reset Overload
  128
- Over Current Override
  129
- Power Sup. Ch 1 & 2, Ch 3 & 4
  129
- Single/Differential Mode Selector Ch 1 & 2, Ch 3 & 4 (for F5 Module Only)
  129
- Range Ch. 1 & 2, Ch. 3 & 4 (for F5 Module Only)
  129
- D/A FIFO Buffer Operational Description
  129
  - D/A Data
    129
  - Words in FIFO
    130
  - Hi-Threshold
    130
  - Lo-Threshold
    130
  - Delay
    130
  - Size
    130
  - Sample Rate
    131
  - Clear FIFO
    131
  - Buffer Control
    131
  - Trigger Control
    132
  - FIFO Status
    132
  - Interrupt Enable
    133
  - Software Trigger
    133
  - Clock Rate Input
    133
- Test Enable
  133
- D2 Test Verify
  133
- BIT Status
  133
- Over Current Status
  134
- BIT Status Interrupt Enable
  134
- Over Current Status Interrupt Enable
  134
- BIT Interrupt Vector
  134
- Channel X FIFO Interrupt Vector
  134
- Over-Current Interrupt Vector
  134
- Interrupt and Status Register Operation/Clarification
  135
D/A (Module F or J, Except J8) Pci Memory Map

136
High Voltage D/A (Module J8)

137
- Principle of Operation
  137
- Built-In-Test (BIT) / Diagnostic Capability
  137
- Data (Write D/A) Output
  137
- D/A Output Range
  138
- D/A Output Polarity
  138
- D/A Wrap-Around
  138
- Current Reading
  138
- Reset to Zero
  138
- Retry Overload
  138
- Reset Overload
  138
- Over Current Override
  139
- Test Enable
  139
- D2 Test Verify
  139
- BIT Status
  139
- Over Current Status
  139
- BIT Status Interrupt Enable
  140
- Over Current Status Interrupt Enable
  140
- BIT Interrupt Vector
  140
- Over-Current Interrupt Vector
  140
- Interrupt and Status Register Operation/Clarification
  141
D/A (Module J8) Pci Memory Map

142
Thermocouple Measurement (Module G3)

143
- Principle of Operation
  143
- Built-In-Test (BIT) / Diagnostic Capability
  143
- Temperature
  144
- Thermocouple Type
  144
- Operational Mode
  144
- ADC Data (RAW)
  145
- Thermocouple Voltage
  145
- External Compensation Temperature
  145
- Compensation Type
  146
- DPRAM Busy
  146
- Bit/Open Test Interval
  146
- Update Rate
  147
- Temperature Units
  147
- BIT Status
  147
- Open Detect Status
  147
- BIT Status Interrupt Enable
  148
- Open Status Interrupt Enable
  148
- BIT Interrupt Vector
  148
- Open Circuit Interrupt Vector
  148
- Interrupt and Status Register Operation/Clarification
  149
- Appendix A (IEEE 754 Format)
  
  150
  - IEEE 754 Binary Formats
    150
- Appendix B (G3 Optional External Isothermal Block Accessory)
  
  151
  - Isothermal Block Applications
    151
  - Optional Accessory NAI P/N ACC-ISO-THERM-BLK1
    152
Thermocouple (Module G3) Pci Memory Map

153
Rtd (Module G4)

154
- Principle of Operation
  154
- Built-In-Test (BIT) / Diagnostic Capability
  154
- Resistance
  155
- Range
  155
- Wire Mode
  155
- 2-Wire Lead Resistance Compensation
  156
- Busy
  156
- Bit/Open Interval
  156
- CAL Interval
  156
- BIT Status
  156
- Open Detection Status
  156
- BIT Status Interrupt Enable
  157
- Open Status Interrupt Enable
  157
- BIT Interrupt Vector
  157
- Open Circuit Interrupt Vector
  157
- Interrupt and Status Register Operation/Clarification
  158
Rtd (Module G4) Pci Module Register Map

159
Load/Strain (Module G5)

160
- Principles of Operation
  160
- Built-In Test (BIT) / Diagnostic Capability
  160
- Data 16
  161
- Data 24
  161
- Output Force
  161
- Output V/V
  161
- Range
  162
- Remote Sense Select
  162
- Excitation Select
  162
- Chop Enable
  163
- Excitation Voltage
  163
- Load Cell Sensitivity
  163
- Filter Configuration
  164
- Busy
  165
- BIT/OPEN Interval
  165
- CAL Interval
  165
- BIT Status
  165
- Open Detection Status
  165
- BIT Status Interrupt Enable
  165
- Open Status Interrupt Enable
  166
- BIT Interrupt Vector
  166
- Open Circuit Interrupt Vector
  166
- Interrupt and Status Register Operation/Clarification
  167
- Appendix (G5)
  
  168
Strain Gage (Module G5) Pci Module Memory Register Map

169
I/O Discrete

171
- Ver. 4 )
  171
- Description
  171
- Features
  171
- Continuous Background BIT Testing
  171
- Input/Output Format
  172
- Input/Output Interface
  172
- Fig 1
  172
- Threshold Programming
  173
- Max High Threshold
  173
- Upper Threshold
  174
- Lower Threshold
  174
- Min Low Threshold
  174
- De-Bounce Time
  174
- Read I/O
  175
- VCC Value
  175
- Pull-Up/Down Current Configuration
  175
- Current for Source/Sink
  176
- Write Output
  177
- Current Share Configuration
  177
- Read Output Voltage
  178
- Read Output Current
  178
- Reset Over-Current
  178
- Status Indications
  178
- Interrupt Enable
  178
- Interrupt Vectors
  179
- Interrupt and Status Register Operation/Clarification
  180
- I/O Discrete (Module K6) - Addendum a (PWM Enhanced Function)
  181
  - Description
    181
  - Features
    181
  - Operational Control Registers
    181
  - Operational Notes/Considerations
    181
  - Pwm/Timer Period
    183
  - PWM/TIMER Pulse Width
    183
  - PWM/TIMER Configuration (Polarity)
    184
  - PWM/TIMER Mode Select
    184
  - PWM/TIMER Mode Enable
    185
  - Register Summary
    185
  - Operational Notes (General)
    185
Discrete (Module K6 Ver. 4) Pci Module Memory Register Map

186
I/O Discrete (Module K7)

187
- Description
  187
- Features
  187
- Principles of Operation
  187
- Continuous Background Built-In-Test (BIT)
  187
- Input/Switch Interface
  188
- Switch Control
  188
- Threshold Programming
  188
- Max High Threshold
  189
- Upper Threshold
  189
- Lower Threshold
  189
- Min Low Threshold
  189
- De-Bounce Time
  189
- Read I/O
  190
- Read Output Voltage (Actual)
  190
- Read Output Voltage (Averaged)
  190
- Read Switch Current (Actual)
  190
- Read Switch Current (Average)
  191
- Reset Over-Current
  191
- Status Indications
  191
- Interrupt Enable
  191
- Interrupt Vectors
  192
- Interrupt and Status Register Operation/Clarification
  193
Discrete (Module K7) Pci Module Memory Register Map

194
I/O Relay (Module Kn, Kl)

195
- Principle of Operation
  195
- Automatic Background Built-In Test (BIT) Diagnostic Capability
  195
- Write Output
  195
- Read State
  195
- Status, BIT Fault
  196
- Interrupt Enable, BIT Fault
  196
- Interrupt Vector, BIT Fault
  196
- Interrupt and Status Register Operation/Clarification
  197
I/O Relay (Module Kn, Kl) Pci Memory Map

198
Discrete/Analog to Digital Combination (Module Ka)

199
- Principle of Operation
  199
  - Discrete I/O
    199
  - Analog to Digital Conversion (A/D)
    199
- Built-In Test (BIT) / Diagnostic Capability
  199
- KA Module A/D Specific Functions
  200
  - Data Read
    200
  - A/D Range
    200
  - BIT Status
    200
  - BIT Status Interrupt Enable
    200
- KA Module Discrete I/O Specific Functions
  201
  - Write Output
    201
  - Read I/O
    201
  - Threshold Programming
    201
  - Hysteresis
    201
  - Max High Threshold
    202
  - Upper Threshold
    202
  - Lower Threshold
    202
  - Min Low Threshold
    202
  - De-Bounce Time
    203
  - Input/Output Interface
    203
  - Input/Output Format
    203
  - Reset Over-Current
    204
  - Status Indications
    204
  - Status Interrupt Enable
    205
- Interrupt and Status Register Operation/Clarification
  206
Discrete / A-D Combination (Module Ka) Pci Memory Map

207
Lvdt Measurement (Module L*)

209
- Principle of Operation (LVDT)
  209
- Interfacing LVDT to Converter
  209
- 2-Wire System
  209
- Built-In Test (BIT) / Diagnostic Capability
  209
  - The On-Line D2 Test
    209
  - The Off-Line D3 Test
    209
  - The Off-Line D0 Test
    209
- Various LVDT Configurations
  210
  - 2-Wire LVDT Connections
    210
- Position Data
  210
- Bandwidth (BW)
  211
- Bandwidth Select
  211
- Active Channels
  211
- Latch (Track/Hold)
  211
- Test (D2) Verify
  211
- Test Enable
  212
- Test Position
  212
- 2-Wire/4-Wire Select
  212
- Input Reference Frequency Measurement
  213
- Input Signal Voltage
  213
  - L-L ) Measurement
    213
- Input Reference Voltage (VREF) Measurement
  213
- Signal Loss Threshold
  213
- Reference Loss Threshold
  213
- Signal Status
  213
- Reference Status
  214
- Signal Status Interrupt Enable
  214
- Reference Status Interrupt Enable
  214
- BIT Status Interrupt Enable
  214
- OSC (Onboard) Excitation Set Frequency
  215
- OSC (Onboard) Excitation Set Voltage
  215
- Interrupt Vector
  216
- LVDT FIFO Buffer Operational Description
  216
  - LVDT Data
    216
  - Words in FIFO
    216
  - FIFO Status
    216
  - Hi-Threshold
    217
  - Low-Threshold
    217
  - Delay
    217
  - Size
    217
  - Sample Rate
    217
  - Clear FIFO
    217
  - Buffer Data Type
    218
  - Trigger Mode
    218
  - Software Trigger
    218
- Status, BIT Fail
  219
- Interrupt and Status Register Operation/Clarification
  220
Lvdt (Module L) Pci Memory Map

221
Synchro/Resolver Measurement (Module S*)

222
- S/D (Module S*)
  222
- Principle of Operation
  222
- Built-In Test (BIT) / Diagnostic Capability
  222
- Data
  223
- Velocity
  223
- Bandwidth (BW)
  223
- Bandwidth Select
  224
- Ratio
  224
- Active Channels
  224
- Latch (Track/Hold)
  224
- Test (D2) Verify
  225
- Test Enable
  225
- Test Angle
  225
- Synchro/Resolver Select
  225
- Angle Δ
  226
- Angle Δ INIT
  226
- Input Reference Frequency Measurement
  226
- Input Signal Voltage
  226
  - L-L ) Measurement
    226
- Input Reference Voltage (VREF) Measurement
  226
- A & B Resolution
  227
- Signal Loss Threshold
  227
- Reference Loss Threshold
  227
- Velocity Scale
  227
- Signal Status
  228
- Reference Status
  228
- S/D Lock Loss Status (Two Speed Lock-Loss)
  228
- S/D Angle Change Status (Angle Δ Alert)
  228
- Signal Status Interrupt Enable
  229
- Reference Status Interrupt Enable
  229
- BIT Status Interrupt Enable
  229
- S/D Lock Loss Status Interrupt Enable
  229
- S/D Angle Change (Angle Δ Alert) Interrupt Enable
  230
- OSC (Optional Onboard Reference Supply) Set Frequency
  230
- OSC (Optional Onboard Reference Supply) Set Voltage
  230
- Interrupt Vector
  231
- S/D FIFO Buffer Operational Description
  231
  - S/D Data
    231
  - Words in FIFO (Count)
    231
  - FIFO Status
    231
  - Hi-Threshold
    231
  - Low-Threshold
    232
  - Delay
    232
  - Size
    232
  - Sample Rate
    232
  - Clear FIFO
    232
  - Buffer Data Type
    232
  - Trigger Mode
    233
  - Interrupt
    233
  - Software Trigger
    233
- Status, BIT Fail
  233
- Interrupt and Status Register Operation/Clarification
  234
S/D (Module S) Pci Memory Map

235
D/S Three Channel (Module 6*)

237
- Principle of Operation
  237
- Built-In Test (BIT) / Diagnostic Capability
  237
- Wrap S/D Angle Read
  237
- Input Reference Voltage Measurement
  237
- Input Signal Voltage (VL-L) Measurement
  237
- Signal Loss Threshold
  238
- Reference Loss Threshold
  238
- D/S Channel Frequency
  238
- D/S Status, Signal Loss
  238
- D/S Write Angle - Single Speed
  238
- D/S Write Angle - Two Speed
  239
- D/S Stop Angle
  239
- D/S Rotation
  239
- D/S Rotation Rate
  239
- D/S Rotation Mode, Continuous or Start/Stop
  239
- Start Rotation
  239
- Stop Rotation
  239
- D/S Rotation Status
  240
- D/S Set Reference Voltage
  240
- D/S Set Signal Voltage
  240
- D/S Test Enable
  240
- Test (D2) Verify
  240
- D/S Ratio 1/2
  241
- D/S Output Mode
  241
- D/S Synchro / Resolver Select
  241
- D/S Trigger Source Select
  241
- D/S Trigger Slope Select
  241
- D/S Module Power Enable
  242
- D/S Active Channels
  242
- D/S Status, Reference Loss
  242
- D/S Status, Phase Lock Loss
  243
- D/S Set Phase Offset
  243
- D/S Status, BIT Test
  243
- Reference Loss Interrupt Enable
  244
- Signal Loss Interrupt Enable
  244
- BIT Test Fail Interrupt Enable
  244
- Phase Lock Loss Interrupt Enable
  244
- OSC (Optional Onboard Reference Supply) Set Frequency
  244
- OSC (Optional Onboard Reference Supply) Set Voltage
  245
- Interrupt Vector
  245
- Interrupt and Status Register Operation/Clarification
  246
D/S 3 Channel (6*) Pci Module Memory Map

247
Dlv 3 Channel (Module 5*)

248
- Principle of Operation
  248
- Built-In Test/Diagnostic Capability
  248
- Wrap LVDT Position (Read)
  248
- DLV Channel Excitation Voltage
  248
- DLV Channel Signal Voltage
  249
- Signal Loss Threshold
  249
- Excitation Loss Threshold
  249
- DLV Write Position
  249
- DLV Response / Filter Time
  249
- Status, Signal Loss
  250
- DLV Channel Frequency
  250
- DLV Set Channel Excitation Voltage
  250
- DLV Set Channel Signal Voltage
  250
- DLV Test Enable
  250
- Test (D2) Verify
  251
- DLV Output Mode
  251
- DLV 2-Wire or 3/4-Wire Select
  251
- DLV Module Power Enable
  252
- DLV Current
  252
- DLV Active Channels
  252
- DLV Status, Excitation
  253
- DLV Status, Phase Lock Loss
  253
- DLV Set Phase Offset
  253
- DLV Current Threshold
  253
- OSC (Onboard) Excitation Set Frequency
  254
- OSC (Onboard) Excitation Set Voltage
  254
- DLV Status, BIT Test
  255
- Excitation Loss Interrupt Enable
  255
- Signal Loss Interrupt Enable
  255
- BIT Test Fail Interrupt Enable
  255
- Phase Lock Loss Interrupt Enable
  256
- Interrupt Vector
  256
- Interrupt and Status Register Operation/Clarification
  257
Ch Dlv (5*) (Pci) Module Memory Map

258
Ssi / Encoder / Quadrature Counter (Module E7)

259
- Principles of Operation
  259
- Channel Inputs
  260
- SSI Mode
  260
- Description
  260
- Standard SSI Interface Controller Mode
  261
- SSI Standard Mode Selection
  261
- Listen Only Mode
  262
- SSI Listen Only Mode Selection
  262
- Parity
  263
- Control Register 0
  264
- Control Register 1
  265
- SSI Received Data High
  265
- SSI Received Data Low
  265
- SSI Received ZB, Parity
  265
- SSI Status
  266
- Counter Modes
  267
  - Counter Match Register
    267
  - Counter Preload Register
    267
  - Counter Latch Register
    267
  - Counter Control Register
    267
- Index Control Modes (ICM)
  268
- No I-Control
  268
- Load on I
  268
- Latch on I
  268
- Gate on I
  269
- Reset on I
  269
- Special Count Mode
  269
- Special Count Modes
  269
- Divide-By-N
  269
- Single Cycle
  269
- Internal Clock Prescaler
  270
  - Clkdiv
    270
  - Counter Input Mode (CIM)
    270
- Counter Status Register
  271
- Timer Mode
  271
- Direction Count
  271
- Up/Down Count
  272
- Quadrature Mode
  272
- Counter Command Register
  272
- Interval Timer
  272
- Interval Timer Control
  273
- Interval Timer Clock Periods
  273
- Global Control Registers
  274
  - Global Control Register High
    274
- Multiple Channel Read
  275
- Interrupt
  277
- Interrupt Vector Registers
  277
- Interrupt Enable Register
  278
- De-Bounce, Digital Input Filter
  278
- De-Bounce Register High [15:0]
  278
- De-Bounce Register Low [0]
  278
- CPLD (Module Configuration Registers)
  279
  - CPLD Register High
    279
  - CPLD Register Low
    280
- Differential (DE) / Single-Ended (SE) Selection
  281
- CPLD Status
  281
- Appendix A - Quadrature (A-Quad-B) Discussion
  
  282
  - Quadrature Count
    282
- Appendix B - Operation Mode Signal Details
  
  285
  - Four Channel Ssi/Encoder (Module E7) Pci Memory Map
    287
Isolated ±15V DC/DC Converter (Module V1, V2)

289
- Description
  289
- Features
  289
- Principles of Operation
  289
- Continuous Background Built-In-Testing (BIT)
  289
- Registers
  290
- On/Off
  290
- Output Voltage (V+)
  290
- Output Current (V+)
  290
- Output Current (V-)
  291
- Fault
  291
- Clear Fault
  291
- Interrupt and Status Register Operation/Clarification
  292
Module (V*), Dual ±15V DC/DC Converter, Pci Memory Register Map

293
Reference (Module W*)

294
- Principle of Operation
  294
- Reference Frequency
  294
- Reference Voltage
  295
- Reference Module Power Enable
  295
- Reference Overcurrent 1
  295
Reference (Module W*) Pci Memory Map

296
Module Identification

297
- Module Design Version
  297
- Module Design Revision
  297
- Module DSP Revision
  297
- Module FPGA Revision
  298
- Module ID
  298
General Use Register Memory Map

299
- Common User Register Memory Map (PCI)
  299
- Part Number
  299
- Serial Number
  299
- Platform
  300
- Model
  300
- Generation
  300
- Special Spec
  300
- Date Code
  301
- Module ID
  301
- Revision Level, Interface FPGA
  301
- Revision Level, Interface DSP
  301
- Board Ready
  302
- Watchdog Timer
  302
- Soft Reset
  302
- Interrupt Level (Not Used)
  302
- Design Version
  303
- Interrupt Status
  303
- Customer Defined Register Allocation
  
  304
  - Ethernet Configuration Registers
    304
Ethernet

305
- Ethernet Socket Protocol, Version 1
  305
- Type Codes Summary
  306
- Error Codes
  306
68C3 Connector/Pin-Out Information

307
Part Number Designation

323
- Part Number Notes
  324
- Channel D/S Module Code Table
  325
- Channel DLV Module Code Table
  326
Revision Page

327

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North Atlantic 68C3 Operation Manual (330 pages)

Table of Contents

Model 68C3

Openvpx, Multi-Function I/O Card

Features

Description

General Board Specification

Software Support

Specifications

68C3 Address Configuration

Product Configuration and Memory Map

Arinc 429/575 Six Channel, Tx/Rx (Module A4)

Module Pci Memory Map - 6 Channel Arinc Communications (A4)

1553 Communications (Modules N7 and N8)

Canbus Control Area Network (Module P6, Pa)

Module (P6) Canbus Can A/B Pci Register Map

Module (Pa) Canbus J1939 Pci Register Map

Four Channel, Serial (Rs232/422/485) (Module P8) / Isolated Rs-422/Rs-485 (Module Pc)

Four Channel Serial Communications (Module P8/Pc) Pci Memory Map

A/D (Modules C1, C2, C3, C4 & Ca)

A/D (Modules C1, C2, C3 & C4) Pci Memory Map

I/O Digital Ttl/Cmos (Module D7)

I/O Digital Ttl/Cmos (Module D7) Pci Memory Map

Differential Multi-Mode Transceivers (Module D8)

I/O (Module D8) Pci Memory Map

D/A (Modules F & J, Except J8)

D/A (Module F or J, Except J8) Pci Memory Map

High Voltage D/A (Module J8)

D/A (Module J8) Pci Memory Map

Thermocouple Measurement (Module G3)

Appendix A (IEEE 754 Format)

Appendix B (G3 Optional External Isothermal Block Accessory)

Thermocouple (Module G3) Pci Memory Map

Rtd (Module G4)

Rtd (Module G4) Pci Module Register Map

Load/Strain (Module G5)

Appendix (G5)

Strain Gage (Module G5) Pci Module Memory Register Map

I/O Discrete

Discrete (Module K6 Ver. 4) Pci Module Memory Register Map

I/O Discrete (Module K7)

Discrete (Module K7) Pci Module Memory Register Map

I/O Relay (Module Kn, Kl)

I/O Relay (Module Kn, Kl) Pci Memory Map

Discrete/Analog to Digital Combination (Module Ka)

Discrete / A-D Combination (Module Ka) Pci Memory Map

Lvdt Measurement (Module L*)

Lvdt (Module L) Pci Memory Map

Synchro/Resolver Measurement (Module S*)

S/D (Module S) Pci Memory Map

D/S Three Channel (Module 6*)

D/S 3 Channel (6*) Pci Module Memory Map

Dlv 3 Channel (Module 5*)

Ch Dlv (5*) (Pci) Module Memory Map

Ssi / Encoder / Quadrature Counter (Module E7)

Appendix A - Quadrature (A-Quad-B) Discussion

Appendix B - Operation Mode Signal Details

Isolated ±15V DC/DC Converter (Module V1, V2)

Module (V*), Dual ±15V DC/DC Converter, Pci Memory Register Map

Reference (Module W*)

Reference (Module W*) Pci Memory Map

Module Identification

General Use Register Memory Map

Customer Defined Register Allocation

Ethernet

68C3 Connector/Pin-Out Information

Part Number Designation

Revision Page

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