1. Manuals
  2. Brands
  3. North Atlantic Manuals
  4. I/O Systems
  5. 68C3
  6. Operation manual

North Atlantic 68C3 Operation Manual

68c3 3u open vpx multi-function i/o card
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
68C3 3U Open VPX
MULTI-FUNCTION I/O CARD
OPERATIONS MANUAL
68C3 Operations Manual
North Atlantic Industries, Inc.
12/19/2014
Rev: 2014-12-19-0947
www.naii.com
Page 1 of 330

Advertisement

Table of Contents
loading

Summary of Contents for North Atlantic 68C3

  • Page 1 68C3 3U Open VPX MULTI-FUNCTION I/O CARD OPERATIONS MANUAL 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 1 of 330...

  • Page 2: Model 68C3

    Proudly made in the USA Description The 68C3 is a single slot, 3U, OpenVPX (0.8” pitch) multi-function I/O and serial communications card. Gigabit Ethernet (Gig-E) and High Speed PCI Express (PCIe) or Serial RapidIO (sRIO) control interface selections enable users to confidently take advantage of the OpenVPX form-factor, offering higher speed switched fabric communication options.

  • Page 3: General Board Specification

    47 Hz – 20 KHz 2 – 28 Vrms 5 VA (max) (v9) Reference  5% 47 Hz – 2 KHz 115 Vrms 5 VA (max) (Slot 3 only) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 3 of 330...

  • Page 4: Software Support

    A Quick-Start Software Manual is also available for download where the SSK contents are detailed, Quick-Start Instructions provided and GUI applications are described therein. For other operating system support, contact factory. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 5: Table Of Contents

    TABLE OF CONTENTS ....................................1 MODEL 68C3 ................................2 3U, OPENVPX, MULTI-FUNCTION I/O CARD ......................2 FEATURES ................................2 DESCRIPTION ................................2 GENERAL BOARD SPECIFICATION ........................3 Available Function Modules ..............................3 SOFTWARE SUPPORT .............................4 SPECIFICATIONS ..............................22 General – For the Motherboard ............................. 22 ARINC 429/575 (Module A4) – Six RX/TX Channels, Configurable ..................22 MIL-STD-1553 (Module N7) –...
  • Page 6 Reference (Module W*) – AC Source, Isolated, Programmable .................... 47 68C3 ADDRESS CONFIGURATION ........................48 PRODUCT CONFIGURATION AND MEMORY MAP .................... 49 68C3 CARD-LEVEL MODULE CONFIGURATION and MEMORY MAPPING ..............50 ARINC 429/575 SIX CHANNEL, TX/RX (MODULE A4) ..................51 Features ....................................51 ARINC 429/575 Overview ..............................
  • Page 7 Last Error Code for Channel X (Global) ..........................80 Comm Status for Channel X (Global) ..........................81 Ch X Baud / Bit Timing Register (Global) ......................... 82 Ch X Baud Rate Prescaler Extension Reg (Global) ......................83 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...
  • Page 8 FOUR CHANNEL SERIAL COMMUNICATIONS (MODULE P8/PC) PCI MEMORY MAP ......... 105 A/D (MODULES C1, C2, C3, C4 & CA) ........................ 106 Principle of Operation ................................106 Built-In Test (BIT) / Diagnostic Capability ..........................106 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...
  • Page 9 I/O DIGITAL TTL/CMOS (MODULE D7) PCI MEMORY MAP ................120 DIFFERENTIAL MULTI-MODE TRANSCEIVERS (MODULE D8) ..............121 Principle of Operation ................................121 Automatic Background Built-In Test (BIT) / Diagnostic capability ..................121 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...
  • Page 10 Over Current Status ................................134 BIT Status Interrupt Enable ..............................134 Over Current Status Interrupt Enable ..........................134 BIT Interrupt Vector ................................134 Channel X FIFO Interrupt Vector ............................134 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...
  • Page 11 Appendix A (IEEE 754 Format) ............................150 IEEE 754 Binary Formats ............................... 150 Appendix B (G3 Optional External Isothermal Block Accessory) ..................151 Isothermal Block Applications ............................151 Optional Accessory NAI P/N ACC-ISO-THERM-BLK1 ....................152 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...
  • Page 12 I/O DISCRETE (MODULE K6 ) ........................171 Description ..................................171 FEATURES ..................................171 Continuous Background BIT Testing ........................... 171 Input/Output Format ................................172 Input/Output Interface ................................172 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 12 of 330...
  • Page 13 Read Output Voltage (Actual) .............................. 190 Read Output Voltage (Averaged) ............................190 Read Switch Current (Actual) .............................. 190 Read Switch Current (Average) ............................191 Reset Over-Current ................................191 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 13 of 330...
  • Page 14 Interfacing LVDT to Converter ............................. 209 2-Wire System ..................................209 3/4-Wire System .................................. 209 Built-In Test (BIT) / Diagnostic Capability ..........................209 The On-line D2 Test ............................... 209 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 14 of 330...
  • Page 15 Principle of Operation ................................222 Built-In Test (BIT) / Diagnostic capability ..........................222 Data ..................................... 223 Velocity ....................................223 Bandwidth (BW)................................... 223 Bandwidth Select ................................. 224 Ratio ....................................224 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 15 of 330...
  • Page 16 Wrap S/D Angle Read ................................. 237 Input Reference Voltage Measurement ..........................237 Input Signal Voltage (VL-L) Measurement ........................... 237 Signal Loss Threshold ................................. 238 Reference Loss Threshold ..............................238 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...
  • Page 17 DLV Set Channel Excitation Voltage ........................... 250 DLV Set Channel Signal Voltage ............................250 DLV Test Enable ................................. 250 Test (D2) Verify ................................... 251 DLV Output Mode ................................251 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...
  • Page 18 Special Count Modes ................................269 Divide-by-N ..................................269 Single Cycle ..................................269 Internal Clock Prescaler ..............................270 CLKDIV ................................... 270 Counter Input Mode (CIM) .............................. 270 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 18 of 330...
  • Page 19 Reference Module Power Enable ............................295 Reference Overcurrent ............................... 295 REFERENCE (MODULE W*) PCI MEMORY MAP ....................296 MODULE IDENTIFICATION ..........................297 Module Design Version ............................... 297 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 19 of 330...
  • Page 20 ETHERNET ................................305 Ethernet Socket Protocol, Version 1 ............................ 305 Type Codes Summary ................................. 306 Error Codes ..................................306 68C3 CONNECTOR/PIN-OUT INFORMATION ....................307 Front and Rear Panel Connectors ............................307 General Notes: ..................................307 Optional Onboard Reference ............................... 307 Trigger Input ..................................
  • Page 21 PART NUMBER DESIGNATION .......................... 323 Part Number Notes ................................324 3 Channel D/S Module Code Table ............................. 325 3 Channel DLV Module Code Table ............................ 326 REVISION PAGE ..............................327 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 22: Specifications

    28 Vp-p, as per 1553 standard Power: +5 VDC @ 1.6 A max at 100% duty cycle (2 channels) Ground: Bus signals isolated from system ground Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 22 of 330...

  • Page 23: Canbus (Module P6, Pa) - Four Canbus Interfaces

    32 KB for each Receive and Transmit buffer. 16 bit data word format only +5 VDC @ 0.2 A per module (typical/average – all channels operating) Power: Ground: Ground return is to system ground Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 23 of 330...

  • Page 24: Rs-422/485 (Module Pc) - Isolated, Four High Speed Rs-422 / 485 Serial Communications

    (RS422/485) Registers CLK (-) 32 KB TX TX(+) TX(-) 32 KB RX Data Buffers Isolated RX(+) RX(-) Transceiver Control CLK (+) (RS422/485) Registers CLK (-) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 24 of 330...

  • Page 25: A/D (Module C1) - Ten A/D Channels (1.25 To 10.0 Vdc Fs) Uni Or Bipolar

    60 ns) Power: +5 VDC @ 500mA typical, 750mA max. Ground: Channel inputs are differential, but referenced to system ground. Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 25 of 330...

  • Page 26: A/D (Module C2) - Ten A/D Channels (5.0 To 40.0 Vdc Fs) Uni Or Bipolar

    60 ns) Power: +5 VDC @ 500mA typical, 750mA max. Ground: Channel inputs are differential, but referenced to system ground. Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 26 of 330...

  • Page 27: A/D (Module C3) - Ten A/D Channels (4-25Ma)

    60 ns) Power: +5 VDC @ 500mA typical, 750mA max. Ground: Channel inputs are differential, but referenced to system ground. Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 27 of 330...

  • Page 28: A/D (Module C4) - Ten A/D Channels (6.25 To 50.0 Vdc Fs) Uni Or Bipolar

    60 ns) Power: +5 VDC @ 500mA typical, 750mA max. Ground: Channel inputs are differential, but referenced to system ground. Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 28 of 330...

  • Page 29: A/D Combo (Module Ca) - Six Channels (±40Vdc) & Four Channels (4-25Ma)

    60 ns) Power: +5 VDC @ 500 mA typical, 750mA max. Ground: Channel inputs are differential, but referenced to system ground. Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 29 of 330...

  • Page 30: I/O (Module D7) - Sixteen Ttl Channels- Programmable For I/O

    +5VDC @ 200 mA, 360 mA fully loaded (54Ω load per channel) Power (Per 11 Channel Module): Ground: All grounds are common and connected to system ground Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 30 of 330...

  • Page 31: D/A (Module F1) − Ten D/A Outputs (  10 Vdc)

    +5 VDC @ 300 mA typical; add 2 mA per 1 mA load per channel Ground: All grounds are common, but are isolated from system ground Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 32: D/A (Module F5) − Four D/A High Current Outputs (  20Vdc At 100 Ma)

    +5 VDC @ 300 mA typical; add 2 mA per 1 mA load per channel Ground: All grounds are common, but are isolated from system ground Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 33: D/A (Module J5) − Ten D/A Outputs (  2.5 Vdc)

    Channel 1 and 2 share a common return. Channel 3 and 4 share a common return. The returns for all four channels are isolated from system ground Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 34: Thermocouple (Module G3) - Six Channel, Thermocouple Measurement Module

    (4 KV transient with a peak current of 7.5A and a Tc of approximately 60 ns) Power: +5 VDC @ 310 mA typical (est.) Ground: Independent channels, isolated from system ground Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 34 of 330...

  • Page 35: Rtd (Module G4) - Six Channel Rtd Measurement

    60 ns Power: +5 VDC @ 100 mA typical Ground: All channel returns are common but are isolated from system ground Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 35 of 330...

  • Page 36: Load/Strain (Module G5) - Four Channel, Load Cell / Strain Gage Module

    Isolated Power Supply EXC-LO 4-Arm Strain Gage/Bridge +5V system (External – item to be measured) G5 Strain Gage (4 CH isolated) Single Channel Example Block 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 36 of 330...

  • Page 37: Discrete (Module K6) (Ver. 4) - Sixteen (16) Programmable Discrete I/O Channel

    Four (4) ground pins per module (one for each bank of 4 channels). All grounds are common within the module but are isolated from system ground Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 38: Discrete (Module K7) - Isolated, Progammable, Bi-Directional I/O Switch

    Data OUT V Sense System Control Data IN I/O B I Sense Isolated Power and Ground ISOLATED GALVANIC ISOLATION POWER SUPPLY System Power and Ground 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 38 of 330...

  • Page 39: Relay (Module Kn, Kl) - Isolated, Four Independent Relay Channels

    The relays utilized on the KL module utilize magnetic latching to assure that once a relay channel is ‘set’ or ‘reset’, even if power is removed from the card/module, the channel will remain at the last commanded position. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 40: Combo (Module Ka) - 4 A/D Channels, 28 Discrete I/O Channels

    ±12 VDC @ 80 mA max. GND: A/Ds have common A/D Reference return (system/power GND referenced) Discretes are referenced to system (power) GND Weight: 0.85 oz. (24 g.) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 40 of 330...

  • Page 41: Lvdt (Module L*) - Four Isolated Lvdt Measurement Channels (2, 3 Or 4 Wire)

    + 5 VDC @ 400 mA Ground: Isolated signal and reference. Channels individually isolated from each other and from system ground Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 41 of 330...

  • Page 42: D/S (Module 6*) -Three Isolated Digital-To-Syn/Rsl Ch, 0.25 Va Power Output

    (Add 13mA of ±12VDC for every 0.1 VA of output load per channel) Ground: Isolated signal and reference. Channels individually isolated from each other and from system ground Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 42 of 330...

  • Page 43: Dlv (Module 5*) - Three Isolated Dlv Stimulus Channels, Lvdt Or Rvdt Outputs

    (Add 0.013 A of ±12 VDC for every 0.1 VA of output load per channel Ground: Isolated signal and excitation. Channels individually isolated from each other and from system ground Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 43 of 330...

  • Page 44: Encoder (Module E7) - Four (4) Isolated Ssi, A-Quad-B Encoder / General Counter

    500 V (between channels and each channel to system GND) Power +5 VDC @ 1 A (max) (Per 4 Channel Module) Weight: 1 oz. (28g) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 44 of 330...

  • Page 45: Dc Power Supply (Module V*) - Isolated ±15V Dc/Dc Converter

    Rear I/O Motherboard Current Shunt SYS_VCC ISO_VCC FPGA/DSP Data Control Galvanic Isolation Offset & scaling Offset & scaling 8 bit A/D Block diagram: (1) Channel example 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 45 of 330...

  • Page 46: Ac Reference (Module W6, W7) - Optional, Isolated, On-Board Reference Supply

    (Power derates linearly to 0.84 VA @ 2.0 Vrms) 12 - 27.9 420 to 192 5 VA @ 26.0 Vrms (Power constant to 12.0 Vrms) 5 VA @ 115 Vrms (fixed) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 47: Reference (Module W*) - Ac Source, Isolated, Programmable

    508 to 231 6 VA @ 26.0 Vrms (Power constant to 12.0 Vrms) 28 - 115 6 VA @ 115 Vrms (Power derates linearly to 1.4 VA @ 28.0 Vrms) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 48: 68C3 Address Configuration

    68C3 Address Configuration 68C3 ADDRESS CONFIGURATION This section provides programmers the information needed for developing drivers other than those supplied. The following information resides in the PCIe configuration registers: Device ID = 6893 (hex) Vendor ID = 15AC (hex) = 01 (hex)

  • Page 49: Product Configuration And Memory Map

    Address = Base + Module 1 Offset 800 + Digital I/O register 810 = Base + 810 hex Address = Base + Module 2 Offset 1000 + Discrete I/O register 022 = Base + 1022 hex (See following page for memory map pictorial) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 50: 68C3 Card-Level Module Configuration And Memory Mapping

    Product Configuration and Memory Map 68C3 CARD-LEVEL MODULE CONFIGURATION and MEMORY MAPPING General Use (Board Level)… 0000 0002 0004 General Use 0006 Offset 000 0008 03FC 03FE 400 + 400 + Len(M1) + 0400 Module 1 Function Registers… Len(M1) Module 2 Function Registers…...

  • Page 51: Arinc 429/575 Six Channel, Tx/Rx (Module A4)

    The AR429 module provides up to six programmable ARINC-429 channels. Each channel is software selectable for transmit and/or receive, Hi or Lo speed, and odd or no parity. Thus the module can support multiple ARINC429 and 575 channels simultaneously. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 52: Receive Operation

    Gap command to disable async transmissions during the schedule gap time. Gap and Fixed-gap commands can both be used when building the transmit schedule. Each transmit channel is double buffered to prevent transmission of partially written 32-bit ARINC words. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 53: Schedule Transmit Commands

    This command causes the transmitter to pause execution of the schedule after transmitting the current word. Either a Transmit Trigger command is issued to resume execution or a Transmit Stop command is issued to halt execution. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 54: Interrupt

    -17V to +17V Receiver Input Resistance (Ohms) Module Supply current, no load (nom): 0.8A@+5V; 0.05A@+12V; 0.05A@-12V Module Supply current, no load (peak): 1.0A@+5V; 0.1A@+12V; 0.1A@-12V 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 54 of 330...

  • Page 55: Module Factory Defaults

     Reset/Clear Commands in Channel Control High register  Reset Module command  There can be a delay of up to 1 sec after the Interrupt Vector register is written before they take effect 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 56: Tx (Transmit) Buffer (Fifo)

    A10 – A1 Lower 10 bits of the ARINC data word where A8 is the msb of the Label and A1 is the lsb. A10 and A9 are the SDI bits. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 57: Rx Fifo (Buffer) Threshold

    FIFO. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION NUM WORDS TX BUFFER D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 57 of 330...

  • Page 58: Channel Control Low

    Notes: 1. Transmit modes: (D4:D3) ( 0:0 ) = Immediate FIFO mode ( 0:1 ) = Schedule mode ( 1:0 ) = Triggered FIFO mode ( 1:1 ) = Invalid mode 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 59: Channel Control High

    0 MATCH MEMORY CLEAR 0 CHANNEL RESET 0 RESERVED 0 SCHEDULE INTR. CLEAR Note: 1. Firmware will clear bit. Allow 100us for command to complete. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 59 of 330...

  • Page 60: Channel Status

    TX FIFO EMPTY TX FIFO ALMOST EMPTY TX FIFO FULL PARITY ERROR RECEIVE ERROR BUILT-IN-TEST ERROR SCHEDULE INTERRUPT ASYNC DATA AVAILABLE TX RUN TX PAUSE RESERVED RESERVED 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 60 of 330...

  • Page 61: Interrupt Enable

    RX FIFO OVERFLOW TX FIFO EMPTY TX FIFO ALMOST EMPTY RESERVED PARITY ERROR RECEIVE ERROR BUILT-IN-TEST ERROR SCHEDULE INTERRUPT ASYNC DATA SENT TX COMPLETE RESERVED RESERVED RESERVED 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 61 of 330...

  • Page 62: Interrupt Status

    D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D1 D0 X X X X X X X 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 63: Mailbox (Mbox) Address Register

    ‘1’ Message has not been read yet N = New message Note* : If Time stamping enabled. Note: This register must be read first before retrieving valid data from the MBOX Data register. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 64: Mailbox (Mbox) Data Register

    Receive Data Unbuffered CHANNEL 1 RX SIGNAL CHANNEL 2 RX SIGNAL CHANNEL 3 RX SIGNAL CHANNEL 4 RX SIGNAL CHANNEL 5 RX SIGNAL CHANNEL 6 RX SIGNAL 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 64 of 330...

  • Page 65: Transmit Trigger Register

    D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION TRANSMIT PAUSE PAUSE CH1 PAUSE CH2 PAUSE CH3 PAUSE CH4 PAUSE CH5 PAUSE CH6 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 65 of 330...

  • Page 66: Transmit Stop Register

    Note: 2: (D2) = Bit write only Note: 3: (P1:P0) = Count of how many times PLL lost lock, resets to 0 on read. Read only. For internal test use. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 67: Timestamp Hi + Lo Register

    Normally accessed via receive FIFO or receive mbox registers. P10 - P0 = Desired memory page. Each page is 128 x16 in size. A17 - A7= Desired RCV memory page. 2048 pages of 128 x 16. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 68: Memory

    X SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 RESERVED RESERVED Note 1: MA7-MA0 = Address of Tx Message memory organized as 256x32. Note 2: SA8-SA0 = Address of Tx Schedule memory organized as 512x16. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 69: Rx Match Memory Layout

    D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION BIT STATUS BUILT-IN-TEST ERROR CH1 BUILT-IN-TEST ERROR CH2 BUILT-IN-TEST ERROR CH3 BUILT-IN-TEST ERROR CH4 BUILT-IN-TEST ERROR CH5 BUILT-IN-TEST ERROR CH6 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 69 of 330...

  • Page 70: Dsp Compile Time

    1 sec after the Interrupt Vector register is written before it takes effect. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION INTERRUPT VECTOR D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 70 of 330...

  • Page 71: Module Pci Memory Map - 6 Channel Arinc Communications (A4)

    Ch 6 R/W 100 MBOX StatusWd Ch3 R 220 MBOX StatusWd Ch 6 R 104 MBOX DataWd Ch 3 R 224 MBOX DataWd Ch 6 R 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 71 of 330...

  • Page 72: 1553 Communications (Modules N7 And N8)

    Operating Mode Registers* Channel 2 * Register assignments are based on Operational Mode. (See Actel Handbook.) and 1553 Module (Nx) Programmer's Reference Guide for detailed API function/register descriptions. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 72 of 330...

  • Page 73: Canbus Control Area Network (Module P6, Pa)

    ISO 11898 International Standard. Both CAN A & B (P6 module) and J1939 (PA module) protocols are supported. The CAN protocol was developed by Robert Bosch GmbH and is recognized and protected by patents and licensed by Bosch. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 74: Features

    CANBus – this termination is expected for proper operation and must be provided or applied externally to the P6 or PA module channel(s). (Below fig. – example of expected/proper CANBus termination). 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 75: P6 Specific Can A/B Register Descriptions

    The thirteen most significant bits of a 29-bit Identifier. The MSB of the Identifier is D12. 0=The corresponding bit in the Acceptance Code Register cannot inhibit the match in the acceptance filtering. 1=The corresponding bit in the Acceptance Code Register is used for acceptance filtering. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 76: Acceptance Mask Lo (Set Per Channel) (P6 - Can A/B Only)

    D13: Message Identifier type. Equals 1 if message type is Can A. Equals 0 if message is Can B. For CAN-A Messages (11-bit Identifiers) D13-D5: Unused. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 76 of 330...

  • Page 77: Msg_Id3

    For CAN-A Messages (11-bit Identifiers) D13-D0 Unused, but must be present. For CAN-B Messages (29-bit Identifiers) D13-D8: Unused D7-D0: The 8 through 1 bits of a 29-bit Identifier 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 77 of 330...

  • Page 78: Data Size

    End of Message Flag. Equals 1 if this is the last byte of CAN data. D13-D8: Unused D7-D0: Byte of data to put in the CAN message payload 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 78 of 330...

  • Page 79: Pa Specific J1939 Register Descriptions

    Receive Filter Ch X Dest/Src Address (PA - J1939 only) The Destination and Source address that can be used as receive filters. Register FUNCTION Dest./Src. Addr. D=DATA BIT D15-D8: Destination address D7-D0: Source address 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 79 of 330...

  • Page 80: P6 (Can A/B) Or Pa (J1939) Global Register Descriptions

    NoChange : Any read access to the Status Register re initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Status Register. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 81: Comm Status For Channel X (Global)

    1= Since this bit was last reset by a read access of the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted. This bit will be reset by reading the Status Register. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 82: Ch X Baud / Bit Timing Register (Global)

    The Sync_Seq is defined by the specification as 1(quantum), so, to center sample the CAN bit, the center would be at 4(quantum): 4(quantum) = 1(quantum) + TSeg1 or TSeg1 = 3(quantum). 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 83: Ch X Baud Rate Prescaler Extension Reg (Global)

    When an Interface Slot is configured to receive and a message comes in, a message will be loaded into the IFx_FIFO. The message will be constructed as follows: PGN_HI PGN_LO Source Dest. Addr Data Size Data1 Data250 Addr Or Priority 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 83 of 330...

  • Page 84: Pgn_Hi (Global)

    Program the value of the vector assignment (typically a unique number/identifier) for the associated channel (used in conjunction with enabled interrupt mechanism) that the Interrupt Service Routine (ISR)) will utilize. Register FUNCTION CHx Vector Addr. D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 84 of 330...

  • Page 85: Module (P6) Canbus Can A/B Pci Register Map

    Ch 2 Error Counter Ch 4 Error Counter Module ID CH1 Interrupt Vector Addr. CH2 Interrupt Vector Addr. CH3 Interrupt Vector Addr. CH4 Interrupt Vector Addr. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 85 of 330...

  • Page 86: Module (Pa) Canbus J1939 Pci Register Map

    Ch 2 Error Counter Ch 4 Error Counter Module ID CH1 Interrupt Vector Addr. CH2 Interrupt Vector Addr. CH3 Interrupt Vector Addr. CH4 Interrupt Vector Addr. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 86 of 330...

  • Page 87: Four Channel, Serial (Rs232/422/485) (Module P8) / Isolated Rs-422/Rs-485 (Module Pc)

    Tx and Rx lines are tied in parallel, any transmitted characters will appear in the Rx buffer. If suppression of the echoed transmitted characters is desired, set the Rx Buffer Suppression bit “D7” of the Tx-Rx Configuration High register to “1” (added function 9/2013). 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...
  • Page 88 (default), and channel is set for RS-422 (asynchronous), CTS (+/-) will be available as an input. Alternatively, if bit D14 is set, RTS is available as a GPIO differential output on these lines. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 89: Serial Communications Specifications

    32 KB TX TX(+) TX(-) 32 KB RX Data Buffers Isolated RX(+) RX(-) Transceiver Control CLK (+) (RS422/485) Registers CLK (-) (PC) module block diagram 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 89 of 330...

  • Page 90: Communication Module Factory Defaults: Registers And Delays

    Channel Control Extended: Data Configuration: Preamble: RX Buffer High Watermark: 0x7F9Bh RX Buffer Low Watermark: 0x0800h XON: 0x0011h XOFF: 0x0013h XON/XOFF: Disabled Time Out Value: 0x9C40h 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 90 of 330...

  • Page 91: Transmit Buffer

    REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION NUM WORDS TX BUFFER D D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 91 of 330...

  • Page 92: Number Of Words Rx Buffer

    D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION CLOCK MODE Internal External INVERT Tx Clock INVERT Rx Clock Functionality added DOM 1/1/2013 and later 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 92 of 330...

  • Page 93: Interface Levels

    CTS/RTS lines (in lieu of multiplexed CTS/RTS with CLK+/-). If set to “0”, RTS/CTS are multiplexed with CLK+/- (legacy and GEN2 platforms) (retro DOM 7/2012 or later). 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 94: Tx-Rx Configuration Low

    Rx buffer) (feature added on platforms DOM 9/2013 or later; Earliest Acceptable Revision (EAR) module DSP rev. 56 / FPGA rev. 20). 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 95: Channel Control Low

    Firmware will clear bit when all data from TX Buffer is transmitted. Use for applications desiring pre-load of TxBuffer and then command/control/trigger transmission. When Tx ALWAYS is set to “1”, transmission will occur as soon as data is placed in Tx Buffer 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 96: Channel Control Extended

    EVEN PARITY MARK PARITY 1 STOP BIT 2 STOP BITS NRZ DATA ENCODING NRZI DATA ENCODING FM0 DATA ENCODING FM1 DATA ENCODING 0 MANCHESTER DATA ENCODING 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 96 of 330...

  • Page 97: Baud Rate

    SYSTEM interrupt will be generated. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Tx BUFFER AE VALUE D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 97 of 330...

  • Page 98: Rx Buffer Almost Full

    Register). When the High Watermark is reached, an interrupt request will be generated, when enabled. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION HI WATERMARK VALUE D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 98 of 330...

  • Page 99: Rx Buffer Low Watermark

    16-bit, high byte sent before low byte. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION HDLC RX/SYNC CHAR D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 99 of 330...

  • Page 100: Hdlc Tx Address/Sync Character

    This register bit field specifies the XON character for in-band flow control in Async mode. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION XON CHAR D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 100 of 330...

  • Page 101: Xoff Character

    Interrupt Status Register, bit D10. LSB is 25µs. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION TIME OUT VALUE D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 101 of 330...

  • Page 102: Interrupt Enable

    SYNC CHAR DETECTED CTS HIGH Detect (rise) CTS LOW Detect (fall) Note: Added function 6/1/10; When and as selected, CTS (rise and/or fall) can be set as an interruptible condition. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 103: Interrupt Status

    This register contains the interrupt vector, or address to the interrupt service routine. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION INTERRUPT VECTOR D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 103 of 330...

  • Page 104: Channel Status

    SYNC CHAR DETECTED CTS HIGH Detect (rise) 1 CTS LOW Detect (fall) 1 Note: Added function 6/1/10; When and as selected, CTS (rise and/or fall) can be monitored as an event status. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 105: Four Channel Serial Communications (Module P8/Pc) Pci Memory Map

    0E8 Channel 3 Control Low R/W 1E8 Termination Character Ch. 3 R/W 778 Module ID 0EC Channel 3 Control High R/W 1EC Termination Character Ch. 4 R/W 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 105 of 330...

  • Page 106: A/D (Modules C1, C2, C3, C4 & Ca)

    D0 Test Voltage and D0 Test Range registers. The outputs from the A/D channels are monitored by an internal D/A for proper conversion. External reference voltage is not required. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 107: Data Read

    6.25 V 5.00 V 5.00 V  2.50 V  1.25 V  For bipolar/uni-polar selection, program D4 as “0” for unipolar and “1” for bipolar. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 107 of 330...

  • Page 108: D0 Test Voltage

    Delay (per channel): Set the number of delay samples before the actual FIFO data collection begins. The data collected during the delay period will be discarded. Data Range: (0x0000-0xFFFF) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 109: Fifo Size (Per Channel)

    FIFO buffer. When an overflow condition occurs, any un-stored data will be lost. Set the bits for Buffer Control REGISTER Buffer Control Description Buffer Ctrl.(16-bit hex) Buf. Ctrl. in ch1-10 Data Range: B0-B4 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 109 of 330...

  • Page 110: Trigger Control (Per Channel)

    (to reset) and then the High Limit Threshold is crossed (set). REGISTER Interrupt Enable Description Interrupt Enable(16-bit hex) Interrupt Enable CH1-10 Data Range: B0-B4 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 110 of 330...

  • Page 111: Software Trigger (Per Channel)

    D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION CLK Rate Input (LO) LSB=1Hz=DATA BIT=D NOTE: Base Sample Rate Range (combined 32-bit word) 2000 to 200,000. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 112: Test Enable

    BIT Status Ch.10 Ch.9 Ch.8 Ch.7 Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 112 of 330...

  • Page 113: Open Status

    (per channel). REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION FIFO Buffer Interrupt Vector D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 113 of 330...

  • Page 114: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 115: A/D (Modules C1, C2, C3 & C4) Pci Memory Map

    CH5 FIFO Buffer Hi-Threshold CH6 FIFO Buffer Control Module FPGA CH6 FIFO Buffer Hi-Threshold CH7 Buffer Control Module ID CH7 FIFO Buffer Hi-Threshold CH8 Buffer Control 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 115 of 330...

  • Page 116: I/O Digital Ttl/Cmos (Module D7)

    Each bit corresponds to one of 16 channels. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Channel WRITE OUTPUT D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 116 of 330...

  • Page 117: Read Input Or Output

    Ch.06 Ch.05 Ch.04 Ch.03 Ch.02 Ch.01 Channel INPUT/OUTPUT CH 09-16 Ch.16 Ch.15 Ch.14 Ch.13 Ch.12 Ch.11 Ch.10 Ch.09 Channel INPUT/OUTPUT D=DATA BIT Integer Input Output 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 117 of 330...

  • Page 118: Reset Over-Current

    Interrupt Vector Lo-Hi Transition D D=DATA BIT Interrupt Vector Hi-Lo Transition D D=DATA BIT Interrupt Vector BIT D D=DATA BIT D D=DATA BIT Interrupt Vector Over-current 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 118 of 330...

  • Page 119: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 120: I/O Digital Ttl/Cmos (Module D7) Pci Memory Map

    0CC De-bounce Time Ch.10 1B8 Status Lo-Hi Transition Ch.01-16 R 7C0 Interrupt Vector Bit 0E0 De-bounce Time Ch.11 1BC Status Hi-Lo Transition Ch.01-16 R 7C4 Interrupt Vector Over-Current 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 120 of 330...

  • Page 121: Differential Multi-Mode Transceivers (Module D8)

    11 (16) channels. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Channel READ I/O D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 121 of 330...

  • Page 122: De-Bounce Time

    120Ω for each channel. Default is @ 12KΩ REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Channel INPUT TERMINATION D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 122 of 330...

  • Page 123: Input/Output Format

    Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 Ch.16 Ch.15 Ch.14 Ch.13 Ch.12 Ch.11 Ch.10 Ch.9 Ch.8 Ch.7 Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 Interrupt Hi-Lo Enable 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 123 of 330...

  • Page 124: Interrupt Vectors

    Interrupt Vector Lo-Hi Transition D D=DATA BIT Interrupt Vector Hi-Lo Transition D D=DATA BIT Interrupt Vector BIT D D=DATA BIT Interrupt Vector Over-current D D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 124 of 330...

  • Page 125: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 126: I/O (Module D8) Pci Memory Map

    Interrupt Over Current Enable Ch.1-16 Interrupt Vector Over Current De-bounce Time Ch.12 De-bounce Time Ch.13 11C De-bounce Time Ch.14 De-bounce Time Ch.15 De-bounce Time Ch.16 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 126 of 330...

  • Page 127: D/A (Modules F & J, Except J8)

    (channel 1 is paired with channel 2, and channel 3 is paired with channel 4) will go to 7FFFh - (Data register / 2). Channel 2 and channel 4's Data registers aren't used in this configuration. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 128: D/A Polarity

    User writes a '0' to disable retry. Reset Overload Write a '1' to clear any over-current conditions and module will clear this register when any over current conditions are removed and all outputs are enabled. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 129: Over Current Override

    For bipolar mode; 7FFFh=+FS, 8,000h=-FS. For unipolar mode, range is from 0h to FFFFh = FS. Description D/A Data (16-bit hex) Data ch1-10 Data Range: (0x0000-0xFFFF) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 129 of 330...

  • Page 130: Words In Fifo

    “fed” to the buffer. Otherwise, if data in the buffer empties, the channel will output the last value. Note: It is recommended that Size be set as part of an initialization. It is not recommended to change Size while there are words in the buffer. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 131: Sample Rate

    B6 = Reserved B7 = Reserved Set the bits for Buffer Control REGISTER Buffer Control Description Buffer Ctrl.(16-bit hex) Buf. Ctrl. in ch1-10 Data Range: B0-B1 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 131 of 330...

  • Page 132: Trigger Control

    When “Words In FIFO” register = “Size”, B4=1; otherwise B4 =0. B4 = Sample Done. Description FIFO Status (16-bit hex) FIFO Status in ch1-10 Data Range: B0-B4 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 132 of 330...

  • Page 133: Interrupt Enable

    BIT Status is part of background testing and the status register may be checked or polled at any given time. REGISTER BIT Status Ch.10 Ch.9 Ch.8 Ch.7 Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 133 of 330...

  • Page 134: Over Current Status

    REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Over-Current Interrupt Vector D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 134 of 330...

  • Page 135: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 136: D/A (Module F Or J, Except J8) Pci Memory Map

    Range Ch 1 & 2 360 CH9 FIFO size R/W 4E0 CH9 Interrupt Enable Range Ch 3 & 4 364 CH10 FIFO size R/W 4E4 CH10 Interrupt Enable 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 136 of 330...

  • Page 137: High Voltage D/A (Module J8)

    0 volts. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION DATA OUTPUT D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 137 of 330...

  • Page 138: D/A Output Range

    Write a '0' to disable retry. Reset Overload Write a '1' to clear any over-current conditions and module will clear this register when any over current conditions are removed and all outputs are enabled. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 139: Over Current Override

    Retry Overload or Reset Overload registers can re-enable outputs. Over Current Status is part of background testing and the status register may be checked or polled at any given time. Over Current Status Ch.4 Ch.3 Ch.2 Ch.1 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 139 of 330...

  • Page 140: Bit Status Interrupt Enable

    REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Over-Current Interrupt Vector D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 140 of 330...

  • Page 141: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 142: D/A (Module J8) Pci Memory Map

    Reset Overload Polarity Ch.4 Over Current Override BIT Interrupt Vector Over Current Interrupt Vector Wrap Around Ch.1 Test Enable Wrap Around Ch.2 D2 Test Verify 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 142 of 330...

  • Page 143: Thermocouple Measurement (Module G3)

    The testing is totally transparent to the user, requires no external programming and has no effect on the operation of this card. It can be enabled or disabled. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 144: Temperature

    (Module-level, applied to all channels). REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Operational Mode D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 144 of 330...

  • Page 145: Adc Data (Raw)

    D=DATA BIT REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Ext. Comp. Temp. Low D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 145 of 330...

  • Page 146: Compensation Type

    @ 239.8 ms). Writing ‘0’ to this register disables BIT/OPEN detection. During BIT/Open Interval operation, actual measured data will be “unavailable” and qualified with DPRAM Busy bit being set in the DPRAM Busy register. REGISTER BIT/OPEN Test Interval 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 147: Update Rate

    Reading any status bit will cause that bit to be unlatched. Open Detection Status is part of background testing and the status register may be checked or polled at any given time. REGISTER Open Detection Status Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 147 of 330...

  • Page 148: Bit Status Interrupt Enable

    (Interrupt Service Routine (ISR)). REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Oven Circuit Interrupt Vector D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 148 of 330...

  • Page 149: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 150: Appendix A (Ieee 754 Format)

    In order to maximize the quantity of representable numbers, floating-point numbers are typically stored in normalized form. This puts the radix point after the first non-zero digit. In normalized form, five is represented as 5.0 × 100. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 151: Appendix B (G3 Optional External Isothermal Block Accessory)

    CH5_IN+ +3.3V 3.3V CH5_IN- To module Regulator/ SYS GND/REF (PWR/GND) Protection CH6_IN+ CH6_IN- External Thermo-block Interface (provides thermocouple wire junction temperature measurement for automatic compensation) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 151 of 330...

  • Page 152: Optional Accessory Nai P/N Acc-Iso-Therm-Blk1

    Dimensions shown are inches Interface Details Module Interface Connector: 25-pin DSUB-Male, AMP 747238-4 (or equivalent) / w/ Jackposts Thermocouple wire terminal: 2-position terminal block, internal, screw-secure, Tyco, 282834-2 (or equivalent) (6 total) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 153: Thermocouple (Module G3) Pci Memory Map

    054 Operational Mode Ch. 4 7C4 Open Detect Interrupt Vector 14C Thermocouple Volt. – Lo Ch. 6 058 Operational Mode Ch. 5 05C Operational Mode Ch. 6 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 153 of 330...

  • Page 154: Rtd (Module G4)

    The testing is totally transparent to the user, requires no external programming and has no effect on the operation of this card. It can be enabled or disabled. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 155: Resistance

    Initialized Value: 4 There are three (3) RTD wire configurations to choose from: Write ‘2’ for 2-wire configuration. Write ‘3’ for 3-wire configuration. Write ‘4’ for 4-wire configuration. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 155 of 330...

  • Page 156: 2-Wire Lead Resistance Compensation

    Reading any status bit will cause that bit to be unlatched. Open Detection Status is part of background testing and the status register may be checked or polled at any given time. REGISTER Open Detection Status Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 156 of 330...

  • Page 157: Bit Status Interrupt Enable

    REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Oven Circuit Interrupt Vector D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 157 of 330...

  • Page 158: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 159: Rtd (Module G4) Pci Module Register Map

    R/W 058 2-Wire Lead Res Ch.5 Module DSP Range 6 R/W 05C 2-Wire Lead Res Ch.6 Module FPGA Module ID Note: 1. Default is 4-Wire Mode 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 159 of 330...

  • Page 160: Load/Strain (Module G5)

    The testing is transparent to the user, requires no external programming and has no effect on the operation of this card. It can be enabled or disabled. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 161: Data 16

    0d27 d26 D25 d24 d23 d22 d21 d20 d19 d18 d17 d16 D=DATA BIT Data V/V low D15 D14 D13 D12 D11 D10 D9 FUNCTION Data D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 161 of 330...

  • Page 162: Range

    A/D is ac excited, this bit must be set to 1. Filter Configuration D15 D14 D13 D12 D11 D10 D9 FUNCTION Data d15 d14 d13 d12 d11 d10 d9 D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 162 of 330...

  • Page 163: Chop Enable

    D25 d24 d23 d22 d21 d20 d19 d18 d17 d16 D=DATA BIT Output force low D15 D14 D13 D12 D11 D10 D9 FUNCTION Data d15 d14 d13 d12 d11 d10 d9 D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 163 of 330...

  • Page 164: Filter Configuration

    With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is the order of the SINC filter. The SINC filter’s first notch frequency is equal to N × output data rate. The chopping introduces notches at odd integer multiples of (output data rate/2). 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 165: Busy

    Set the bit to enable interrupts for the corresponding channel. When enabled, a non-compliant channel will trigger an interrupt. Default is 00h to disable all channels. REGISTER BIT Status Interrupt Enable Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 165 of 330...

  • Page 166: Open Status Interrupt Enable

    When an Over-Current Interrupt is enabled and occurs, the contents of Over-Current Interrupt Vector register is the value that is reported to the user. REGISTER D15 D14 D13 D12 D11 D10 D9 FUNCTION Open Circuit Interrupt Vector D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 166 of 330...

  • Page 167: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 168: Appendix (G5)

    In order to maximize the quantity of representable numbers, floating-point numbers are typically stored in normalized form. This puts the radix point after the first non-zero digit. In normalized form, five is represented as 5.0 × 100. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 169: Strain Gage (Module G5) Pci Module Memory Register Map

    Excitation Voltage Load cell sensitivity lo Load cell sensitivity hi Load cell sensitivity lo Load cell sensitivity hi Load cell sensitivity lo Load cell sensitivity hi 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 169 of 330...
  • Page 170 Strain Gage (Module G5) PCI Module Memory Register Load cell sensitivity lo Load cell sensitivity hi 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 170 of 330...

  • Page 171: I/O Discrete

    Associated status register(s) can be checked or polled at any given time. To Enable Interrupts, within any interrupt enable register, set the appropriate channel bits to “1”. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 172: Input/Output Format

    0.5 mA Source 0.5 mA current. Threshold input levels accordingly. I/O Pin Note: LOAD I/O Pin Zin = 1 mΩ Fig 1 Fig 2 Fig 3 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 172 of 330...

  • Page 173: Threshold Programming

    D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 51.2 25.6 12.8 6.4 3.2 1.6 0.8 0.4 0.2 0.1 value in Volts (LSB=100mV) MAX HIGH THRESHOLD D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 173 of 330...

  • Page 174: Upper Threshold

    Value is 15 bits (MSB=don’t care). De-bounce defaults to “0” upon reset. Enter a value of “0” to disable De- bounce filtering. CONTACT SENSE VOLTAGE SENSE Upper Threshold Input Signal Input Signal Debounce Time Debounce Time Output Output 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 174 of 330...

  • Page 175: Read I/O

    D1 configures bank 2, channels 5-8 of that module. Configure Ch.05-08 D2 configures bank 3, channels 9-12 of that module. Configure Ch.09-12 D3 configures bank 4, channels 13-16 of that module. Configure Ch.13-16 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 175 of 330...

  • Page 176: Current For Source/Sink

    = 0.156 volts. closed Program Minimum Lower Threshold T 20% less than V open < 0.8 V < 0.8 x 0.13 = 0.1 volts. closed 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 176 of 330...

  • Page 177: Write Output

    Channels 1 - 2 and Channels 3 - 4 shared 1010 Channels 1 - 3 shared (Channel 4 individual) 0110 Channels 1 - 4 shared (NO channels individual) 1111 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 177 of 330...

  • Page 178: Read Output Voltage

    Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 Interrupt Hi-Lo Enable Ch.16 Ch.15 Ch.14 Ch.13 Ch.12 Ch.11 Ch.10 Ch.9 Ch.8 Ch.7 Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 178 of 330...

  • Page 179: Interrupt Vectors

    D=DATA BIT Mid Range Threshold Interrupt Vector D=DATA BIT Over-current Interrupt Vector D=DATA BIT Interrupt Vector Lo-Hi Transition D=DATA BIT Interrupt Vector Hi-Lo Transition D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 179 of 330...

  • Page 180: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 181: I/O Discrete (Module K6) - Addendum A (Pwm Enhanced Function)

    “0” (default) the pulse width will be defined as low-going. When the polarity bit is set to “1” the pulse width will be defined as high-going. This function is also related to “PWM/Timer Period and Pulse Width”. (Reference figure (1.), Timing Diagram). 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...
  • Page 182 Pulses will be contiguous/repetative until changed/ stopped (disabled). In conjunction w/ (PWM/Timer Configuration – POLARITY) PWM/Timer Period 40.96 us to 1.34 sec. Figure 1. (Timing Diagram) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 182 of 330...

  • Page 183: Pwm/Timer Period

    0x0000 0x01B8 PWM/TIMER Pulse Width, CH13 0x0000 0x01BA PWM/TIMER Pulse Width, CH14 0x0000 0x01BC PWM/TIMER Pulse Width, CH15 0x0000 0x01BE PWM/TIMER Pulse Width, CH16 0x0000 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 183 of 330...

  • Page 184: Pwm/Timer Configuration (Polarity)

    Ch.10 Ch.9 Ch.8 Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 Select Register Offset Description Type Power On / Reset Default Remarks 0x01E0 PWM/Timer Mode Select 0x0000 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 184 of 330...

  • Page 185: Pwm/Timer Mode Enable

    If changing to a larger pulse width, ensure the time period is not exceeded. PWM/Timer Period and Pulse Width are ‘buffered’, meaning that run time programming changes can be effectively managed and will take effect at the end of the previous/current programmed period. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 186: Discrete (Module K6 Ver. 4) Pci Module Memory Register Map

    Min Low Threshold Ch.11 Interrupt Lo-Hi Transition Enable Ch.01-16 De-bounce Time Ch.11 Interrupt Hi-Lo Transition Enable Ch.01-16 Note: Highlighted functionality available on K6 ver. 4 or later. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 186 of 330...

  • Page 187: I/O Discrete (Module K7)

    Additionally, each output is continually checked for over-current. Over-current is controlled by firmware and set by design at 600ma. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 188: Input/Switch Interface

    Conversely, the same is Logic High “1” true as the signal changes from low to high, or high to low. Logic Low “0” Logic State 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 188 of 330...

  • Page 189: Max High Threshold

    Enter time in 20.48 s increments, up to (approx) 1.34 seconds. (LSB = approximately 20 s). Value is 15 bits (MSB = don’t care). De-bounce defaults to “0” upon reset. Enter a value of “0” to disable de-bounce filtering. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 190: Read I/O

    19C (2s complement) =0X0064 (100d) REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Switch Current (signed) D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 190 of 330...

  • Page 191: Read Switch Current (Average)

    Ch.12 Ch.11 Ch.10 Ch.9 Ch.8 Ch.7 Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 Interrupt Hi-Lo Enable Ch.16 Ch.15 Ch.14 Ch.13 Ch.12 Ch.11 Ch.10 Ch.9 Ch.8 Ch.7 Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 191 of 330...

  • Page 192: Interrupt Vectors

    Mid Range Threshold Interrupt Vector D D=DATA BIT Over-current Interrupt Vector D D=DATA BIT Interrupt Vector Lo-Hi Transition D D=DATA BIT Interrupt Vector Hi-Lo Transition D D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 192 of 330...

  • Page 193: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 194: Discrete (Module K7) Pci Module Memory Register Map

    Mid Range Threshold Interrupt Vector Current Reading (Sampled) Ch.12 Current Reading (Sampled) Ch.13 Current Reading (Sampled) Ch.14 Current Reading (Sampled) Ch.15 Current Reading (Sampled) Ch.16 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 194 of 330...

  • Page 195: I/O Relay (Module Kn, Kl)

    Read logic state High (“0”) or Low (“1”) as defined by relay state “OPEN” (reset) or “CLOSED” (set) respectively. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Channel READ I/O D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 195 of 330...

  • Page 196: Status, Bit Fault

    REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Vector, Interrupt D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 196 of 330...

  • Page 197: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 198: I/O Relay (Module Kn, Kl) Pci Memory Map

    Ch.1-4 76C Module Design Revision 770 Module DSP 774 Module FPGA 778 Module ID 1D0 BIT Fault, Intrpt. Enable Ch.1-4 R/W 7C0 Vector, BIT Interrupt 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 198 of 330...

  • Page 199: Discrete/Analog To Digital Combination (Module Ka)

    Associated status register(s) can be checked or polled at any given time. Enable Interrupts, within any interrupt enable register, by setting the appropriate channel bits to “1”. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 200: Ka Module A/D Specific Functions

    Set the bit to enable interrupts for the corresponding channel. When enabled, a non-compliant channel will trigger an interrupt. Default is 00h to disable all channels. BIT Status Interrupt Ch.10 Ch.9 Ch.8 Ch.7 Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 Enable 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 200 of 330...

  • Page 201: Ka Module Discrete I/O Specific Functions

    Conversely, the same is Logic High “1” true as the signal changes from low to high, or high to low. Logic Low “0” Logic State 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 201 of 330...

  • Page 202: Max High Threshold

    D8 D7 D6 D5 D4 D3 FUNCTION 20.48 10.24 5.12 2.56 1.28 .64 .32 .16 0.08 0.04 0.02 0.01 Value in Volts (LSB~10mV) MIN LOW THRESHOLD D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 202 of 330...

  • Page 203: De-Bounce Time

    D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION INPUT/OUTPUT CH 13-16 Ch.16 Ch.15 Ch.14 Ch.13 Ch.12 Ch.11 Ch.10 Ch.09 Channel INPUT/OUTPUT D=DATA BIT Integer 0 Input 1 Output, Low-side switched, 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 203 of 330...

  • Page 204: Reset Over-Current

    Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 Interrupt Hi-Lo Enable Ch.16 Ch.15 Ch.14 Ch.13 Ch.12 Ch.11 Ch.10 Ch.9 Ch.8 Ch.7 Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 204 of 330...

  • Page 205: Status Interrupt Enable

    Ch.8 Ch.7 Ch.6 Ch.5 Ch.4 Ch.3 Ch.2 Ch.1 Note: For channel registers 17-28, substitute bit mapping for 1-12, respectively (bit mapped from D0 – D11) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 205 of 330...

  • Page 206: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 207: Discrete / A-D Combination (Module Ka) Pci Memory Map

    Ch.19 R/W 790 Vector, Interrupt, Hi-Lo Transition Ch.01-16 4B4 Min Low Threshold Ch.05 5CC Min Low Threshold Ch.19 R/W 794 Vector, Interrupt, Hi-Lo Transition Ch.17-28 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 207 of 330...
  • Page 208 770 Module DSP Min Low Threshold Ch.08 608 Min Low Threshold Ch.22 R/W 774 Module FPGA De-bounce time Ch.08 60C De-bounce time Ch.22 R/W 778 Module ID 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 208 of 330...

  • Page 209: Lvdt Measurement (Module L*)

    All channels are disconnected from the outside world (offline), allowing user to write any number of input positions to the card and then read the data from the interface. External excitation is not required. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 210: Various Lvdt Configurations

    7FFF, 0 = 0, and max. negative excursion is 8000. Data format (3/4-wire): The output data is (A-B) / (A+B) and represents %FS. Format is two's complement. Max. positive excursion is 7FFF, 0 = 0, and max. negative excursion is 8000. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 211: Bandwidth (Bw)

    Card will write 55h at Test (D2) Verification register when (D2) is enabled, approximately every one second. User can clear to 00h and then read again, after approximately one second, to verify that background bit testing is activated. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 212: Test Enable

     4-Wire=01  2-Wire=10 REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION LVDT2W/LVDT4W CHANNEL BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 212 of 330...

  • Page 213: Input Reference Frequency Measurement

    D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION SIGNAL STATUS X Ch4 Ch3 Ch2 Ch1 CHANNEL STATUS BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 213 of 330...

  • Page 214: Reference Status

    Read/Write: R/W Initialized Value: 0 Set the bit to enable interrupts for the corresponding channel. When enabled, a non-compliant channel will trigger an interrupt. Default is 0 to disable all channels. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 215: Osc (Onboard) Excitation Set Frequency

    REGISTER D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION approximate value REF VOLTAGE HI D=DATA BIT (V) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 215 of 330...

  • Page 216: Interrupt Vector

    FIFO Status (16-bit hex) Status in ch1-4 Data Range: B0-B4 Pending (To be determined) Description FIFO Status (16-bit hex) Status in ch1-4 Data Range: 0x0-0xFFFF 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 216 of 330...

  • Page 217: Hi-Threshold

    Whenever the Clear memory is set or reset for the individual channel, it initializes the “Words in FIFO” to zero. A read to the “L(R)VDT Data” register gives aged data. Description Clear FIFO (16-bit hex) Clear in ch1-4 Data Range: (0x0000-0xFFFF) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 217 of 330...

  • Page 218: Buffer Data Type

    “Trigger Ctrl” register must be set up properly. Setting or resetting the “Software Trigger” will start FIFO data collection for ALL channels. Description Software Trigger (16-bit hex) Software Trigger Data Range: 0x0-0xFFFF 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 218 of 330...

  • Page 219: Status, Bit Fail

    D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION BIT STATUS X Ch4 Ch3 Ch2 Ch1 CHANNEL STATUS BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 219 of 330...

  • Page 220: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 221: Lvdt (Module L) Pci Memory Map

    76C Module Design Revision 618 Data Buffer FIFO Count CH3 770 Module DSP Rev 61C Data Buffer FIFO Count CH4 774 Module FPGA Rev 778 Module ID 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 221 of 330...

  • Page 222: Synchro/Resolver Measurement (Module S*)

    The off-line (D0) Test is used to check the card and the system interface. All channels are disconnected from the outside world, allowing the user to write any angle to all channels on the card and then to read the data from the interface. External reference is not required. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 223: Data

    028h. When the bandwidth select register is set for “automatic mode”, the automatic bandwidth (as calculated and set by the card algorithm) can be read. The minimum BW is 10 Hz, and the maximum BW is 100 Hz. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 224: Bandwidth Select

    Writing a “0” to this register will disengage latch on all channels. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION LATCH D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 224 of 330...

  • Page 225: Test (D2) Verify

    Synchro=11 Resolver=00. REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION SYNCHRO / RESOLVER CHANNEL BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 225 of 330...

  • Page 226: Angle Δ

    The input voltage is reported to a resolution of 10 mv rms. The output is in integer decimal format. For example, if channel 1 input signal voltage is 11.8 V , the output measurement word from the corresponding register would be 1180. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 227: A & B Resolution

    (11.9209 rps / 32,767) x 360/rps = 0.1310 /sec (lowest setting) REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION VELOCITY SCALE D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 227 of 330...

  • Page 228: Signal Status

    Angle Δ Alert Status Interrupt Vector in the General Use Memory Map. REGISTER D15 D14 D13 D12 D11 D10 D9 FUNCTION ANGLE Δ CHANNEL STATUS Ch4 Ch3 Ch2 Ch1 ALERT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 228 of 330...

  • Page 229: Signal Status Interrupt Enable

    REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION CHANNEL PAIR S/D LOCK LOSS INTR ENABLE 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 229 of 330...

  • Page 230: S/D Angle Change (Angle Δ Alert) Interrupt Enable

    REGISTER D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION approximate value REF VOLTAGE HI D=DATA BIT (V) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 230 of 330...

  • Page 231: Interrupt Vector

    (B2) of the channel status register will be reset. = “logic 1” Reset = “logic 0” Description Hi-Threshold (16-bit hex) Hi-Threshold in Ch1-4 Data Range: (0x0000-0xFFFF) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 231 of 330...

  • Page 232: Low-Threshold

    Size and Buffer Control register could cause an overflow to the FIFO buffer. When an overflow condition occurs, any un- stored data will be lost. Time 8-bit Lo 16-bit Hi Stamp Description Buffer Ctrl.(16-bit hex) Buf. Ctrl. in ch1-4 Data Range: B0-B4 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 232 of 330...

  • Page 233: Trigger Mode

    D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION BIT STATUS X Ch4 Ch3 Ch2 Ch1 CHANNEL STATUS BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 233 of 330...

  • Page 234: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 235: S/D (Module S) Pci Memory Map

    604 Data Buffer FIFO Value Ch.2 76C Module Design Revision 0BC SD4 Measured Ref Freq HI 608 Data Buffer FIFO Value Ch.3 770 Module DSP Rev 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 235 of 330...
  • Page 236 614 Data Buffer FIFO Count Ch.2 0C8 SD3 Measured VL-L 618 Data Buffer FIFO Count Ch.3 0CC SD4 Measured VL-L 61C Data Buffer FIFO Count Ch.4 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 236 of 330...

  • Page 237: D/S Three Channel (Module 6*)

    The output voltage is reported to a resolution of 10 mv rms. The output is in integer decimal format. For example, if channel 1 output signal voltage is 11.8 V , the output measurement word from the corresponding register would be 1180. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 238: Signal Loss Threshold

    .00274 .00137 .00068 .00034 .00017 .00008 .00004 .00002 () Lo Note: Writing to an Input Angle Register will stop any rotation initiated on that channel 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 238 of 330...

  • Page 239: D/S Write Angle - Two Speed

    Channel will remain at the stopped angle until new input angles are set, or rotation is again initiated. Note: An in-process rotation can also be stopped by commanding a new angle (D/S Write Angle). 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 240: D/S Rotation Status

    Card will write 55h at Test (D2) Verification register when (D2) is enabled, approximately every one second. User can clear to 00h and then read again, after approximately one second, to verify that background bit testing is activated. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 241: D/S Ratio 1/2

    D/S Trigger Slope Select For positive slope, set the corresponding channel bit to "0" in the Trigger Slope Select Mode Register. For negative slope, set the bit to “1”. Trigger Slope Select 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 242: D/S Module Power Enable

    Channels that are inactive are also set to “0”. (Reference loss is detected after 2 seconds). Reference monitoring is always enabled. Any D/S reference loss detection, transient or intermittent, will latch the D/S Reference Status Register. Reading will unlatch register. D/S Status, Reference Loss 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 243: D/S Status, Phase Lock Loss

    Note: When D/S Wrap Select External/Internal register is set for “external”, the BIT wrap will be read from the external amplifier wrap input signals (See pin-out). Also, the BIT tolerance will be adjusted for the amplifier accuracy specification. D/S Status, BIT Test 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 244: Reference Loss Interrupt Enable

    REGISTER D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION approximate value REF FREQUENCY LO D=DATA BIT (Hz) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 244 of 330...

  • Page 245: Osc (Optional Onboard Reference Supply) Set Voltage

    The BIT interrupt vector will be serviced when the Bit (failure) status is set and the interrupt has been enabled. The Lock Loss interrupt vector will be serviced when the Lock Loss status is set and the interrupt has been enabled. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 246: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 247: D/S 3 Channel (6*) Pci Module Memory Map

    CH1 W/R 1AC D/S Trigger Slope Select 0E8 D/S Stop Angle CH2 W/R 1C0 D/S Module Power Enable 0EC D/S Stop Angle CH3 W/R 1C8 D/S Active Channel Select 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 248: Dlv 3 Channel (Module 5*)

    The input voltage is reported to a resolution of 10 mv rms. The output is in integer decimal format. For example, if channel 1 input signal voltage is 11.8 V , the output measurement word from the corresponding register would be 1180. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 249: Dlv Channel Signal Voltage

    Vb = Excitation Voltage * TR * [ 1 – ( Position/2 + 0.5 ) ] The Output voltage in 2-wire mode is related to the position by: V = Excitation Input * TR * Position DLV Response / Filter Time (Pending) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 250: Status, Signal Loss

    72 different positions to an accuracy of 0.2% FS. External excitation is required and outputs must be ON. The DLV Status bits will be set to indicate an accuracy problem. Results are available in the DLV North Atlantic Industries, Inc. 68C3 Operations Manual...

  • Page 251: Test (D2) Verify

    Where applicable, write an “01” or “10” (4-Wire = 01; 2-Wire = 10) to each corresponding channel bit pair, representing a channel commanded output format, of the DLV 2-Wire or 3/4 Wire Select Register. DLV 2-Wire or 3/4 –Wire Select 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 252: Dlv Module Power Enable

    Active Channel Register for the particular DLV channel. “1” = Active; “0” = not used. IMPORTANT: Omitting this step will produce false alarms because unused channels will set faults. Active Channels 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 253: Dlv Status, Excitation

    16 (10h). If channel 1 output signal is to lag the reference signal by 1.6 degrees, program the corresponding channel phase register to -16 (FFF0h). Phase shift range is -90 <= x <= 90. DLV Current Threshold (Pending) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 254: Osc (Onboard) Excitation Set Frequency

    REGISTER D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION approximate value REF VOLTAGE HI D=DATA BIT (V) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 254 of 330...

  • Page 255: Dlv Status, Bit Test

    BIT Test) will trigger an interrupt. Default is “0” to disable interrupt on all channels. When Status Interrupt is enabled, Status Interrupt is reported through the BIT Test Loss Interrupt Vector. BIT Test Fail Interrupt Enable 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 256: Phase Lock Loss Interrupt Enable

    The BIT interrupt vector will be serviced when the Bit (failure) status is set and the interrupt has been enabled.  The Lock Loss interrupt vector will be serviced when the Lock Loss status is set and the interrupt has been enabled. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 257: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 258: Ch Dlv (5*) (Pci) Module Memory Map

    0A0 Channel 3 Frequency 1EC DLV Set Phase Offset W/R 774 Module FPGA Revision 0B0 Status, Signal Loss DLV Set Phase Offset W/R 778 Module ID Revision 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 258 of 330...

  • Page 259: Ssi / Encoder / Quadrature Counter (Module E7)

    High, Upper, Lower, Min Low) are programmed to user defined high and low voltage levels. All four threshold levels must be set for each Input or Output channel to validate BIT testing. Interrupts can also be generated on a change of state or transition. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 260: Channel Inputs

    After all bits are transmitted #, the absolute encoder holds the data line low for 10-30µs (recovery time tm). After that the absolute encoder is ready for a new transmission $. A new transmission must not be started before $. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 261: Standard Ssi Interface Controller Mode

    If enabled, an interrupt is asserted and the positional data can then be read in the Data Register. In this mode the read error status bit is always read zero (0). 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 262: Listen Only Mode

    Note: In this mode the clock rate setting in the Control Register is ignored; the Clock Rate will be detected automatically. Writes to the Data Register are also ignored for channels in this mode. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 263: Parity

    Data Register or a Multiple External SSI Interface Controller Start Channel Read Register access definitions: r=read, w=write, r/c=clear (0) on read action; n/u=not used 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 263 of 330...

  • Page 264: Control Register 0

    0 = Do Not Detect Parity Errors / No Parity Bit [4:0] BC[4:0] Number of Data Bits Bits are used to program the number of bits of the serial Valid range ^1d to ^d31. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 264 of 330...

  • Page 265: Control Register 1

    Received SSI Data Register H [15:0] SSI Received ZB, Parity Symbol Description Access Reset Value [15:2] Received Zero Bit (Should be Zero) Received Parity Bit 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 265 of 330...

  • Page 266: Ssi Status

    Encoder With Parity - If Encoder Provides a Parity Bit: 1 = Detect Parity Errors 0 = Do Not Detect Parity Errors / No Parity Bit Overflow N-Data New Data 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 266 of 330...

  • Page 267: Counter Modes

    [15:13] [12:10] ICM[2:0] Index Control Mode [9:7] POL[2:0] A,B,I Polarity [6:5] SCM[1:0] Special Count Mode [4:3] CLKDIV[1:0] Internal Clock Prescaler [2:0] CIM[2:0] Counter Input Mode 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 267 of 330...

  • Page 268: Index Control Modes (Icm)

    Register Lock DRL bit is still active, the data in the Counter Latch register will be retained and the Data Register Lock Overflow (OVFL) will be set to indicate that last latch on I counter value was lost. This control mode can be used to capture a position in a mechanical system. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 269: Gate On I

    A manual counter preload in the Global Control Register  A control mode event in .Load on I. or .Reset on I. mode The counter will stop when it creates a borrow or a carry. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 270: Internal Clock Prescaler

    Quadrature B Quadrature Count 2x Input A & Input B Quadrature A Quadrature B Quadrature Count 4x Input A & Input B Quadrature A Quadrature B 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 270 of 330...

  • Page 271: Counter Status Register

    The counter acts as up/down counter. Counting pulses are generated when a transition from low to high of the A- input is detected. The B-input determines the count direction. B Input Count Direction Down 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 272: Up/Down Count

    Counter Command register bit, LCNT, and RCNT. Writing a one to these register bits either reset, or preloads the counter. Please note: use of these bits is exclusive. Interval Timer Symbol Description Access Reset Value [15:0] ITPRE Interval Timer Preload Register 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 272 of 330...

  • Page 273: Interval Timer Control

    Interval Time = Value of Interval Timer Preload Register * Clock period Interval Timer Clock Periods The interval timer can be used as a reference timer in closed loop applications or as a trigger for a multiple channel read. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 274: Global Control Registers

    Counter Preload Registers must be loaded with valid data Prl[3] Manual Counter Preload Channel [3] Prl[2] Manual Counter Preload Channel [2] Prl[1] Manual Counter Preload Channel [1] 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 274 of 330...

  • Page 275: Multiple Channel Read

    MCRTR trigger, or on the Interval Timer terminal count, which has an interrupt. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...
  • Page 276 01 SSI Mode 10 Counter Mode 11 Channel Disabled [5:4] IC3[1:0] Interface Control Channel 3 [3:2] IC2[1:0] Interface Control Channel [1:0] IC1[1:0] Interface Control Channel 1 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 276 of 330...

  • Page 277: Interrupt

    SSI Interrupts – CH4 SSI_CH4 SSI Interrupts – CH3 SSI_CH3 SSI Interrupts – CH2 SSI_CH2 SSI Interrupts – CH1 SSI_CH1 -Not Used- (Read as Zero) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 277 of 330...

  • Page 278: Interrupt Enable Register

    Symbol Description Access Reset Value [15:1] Bypass 0 = De-bounce Circuit Bypassed (Disabled) 1= The Input Signal is Filtered According to the Filter Counter Value 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 278 of 330...

  • Page 279: Cpld (Module Configuration Registers)

    (1). Although it is possible to set the Driver enable and Termination enable bit on, there operation should be considered mutually exclusive. The 120 ohm termination should be enable when the channel is in receive mode, and disabled for transmit. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 280: Cpld Register Low

    7.5K resistor between the grounded input pins and the voltage output of the DAC. The termination enables (te_idx te_b, and te_a) bits must be zero. There is no differential termination in single ended mode. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 281: Differential (De) / Single-Ended (Se) Selection

    1= Error On Received Index Pulse. A one indicates a difference on the LT2854 received data and the AM28LV32E receivers for more than 1usec. 0 = Normal Operation Always Zero (0) Always Zero (1) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 281 of 330...

  • Page 282: Appendix A - Quadrature (A-Quad-B) Discussion

    5000 revolutions per minute (rpm) results in a frequency of 166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can determine the velocity of the motor. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...
  • Page 283 Equation 1 is the conventional approach to velocity estimation and it requires a time base to provide unit time event for velocity calculation. Unit time is basically the inverse of the velocity calculation rate. 68C3 Operations Manual North Atlantic Industries, Inc.
  • Page 284 For systems with a large speed range (that is, speed estimation is needed at both low and high speeds), one approach is to use Equation 2 at low speed and have the DSP software switch over to Equation 1 when the motor speed rises above some specified threshold. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 285: Appendix B - Operation Mode Signal Details

    300 ns De-Bounce: Programmable per bit from 0 to 343 s. LSB= programmable. Output Driver Output Voltage: Driver Output Signal Level Driver Output Signal Level 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 285 of 330...
  • Page 286 300 ns De-Bounce: Programmable per bit from 0 to 343 s. LSB= programmable. Output Driver Output Voltage: Driver Output Signal Level Driver Output Signal Level 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 286 of 330...

  • Page 287: Four Channel Ssi/Encoder (Module E7) Pci Memory Map

    SSI Interrupt Vector Global Control Register High Counter Command Register SSI Interrupt Vector Global Control Register Low Counter Status Register Counter Match Interrupt Vector Interrupt Enable Register 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 287 of 330...
  • Page 288 IN_B De-bounce High DSP Version Match Data High IN_B De-bounce Low FPGA Version Match Data Low IN_INDX De-bounce High Module ID Counter Preload High IN_INDX De-bounce Low 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 288 of 330...

  • Page 289: Isolated ±15V Dc/Dc Converter (Module V1, V2)

    Dependent upon the configuration, BIT verifies that the output agrees with the test data, or a possible fault is indicated. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 290: Registers

    Output Current (+) register is an unsigned 16-bit number where the LSB is 1mA. REGISTER D15 D14 D13 D12 D11 D10 D7 D6 D3 D2 D1 D0 FUNCTION 128 64 value in mA Threshold D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 290 of 330...

  • Page 291: Output Current (V-)

    0x0001 to this address. Reading this register location always returns zero (0x0000). REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION RESET OVER-CURRENT 0 D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 292: Interrupt And Status Register Operation/Clarification

    “latch” the Status Register(s) – so, a subsequent read to the Status Register after the write operation should be performed to ensure the Status Register is unlatched, clear and ready to trigger on next event. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 293: Module (V*), Dual ±15V Dc/Dc Converter, Pci Memory Register Map

    (reserved) (reserved) (skipped) (reserved) Module Design Version Module Design Revision DSP Version FPGA Version Module ID Note: For V1 module, only CH1 applies (where applicable). 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 293 of 330...

  • Page 294: Reference (Module W*)

    REGISTER D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION approximate value REF FREQUENCY HI D=DATA BIT (Hz) 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 294 of 330...

  • Page 295: Reference Voltage

    Reference Overcurrent register will be set to “1”. To re-enable the output stage and re-engage the automatic 10 second overcurrent protection circuit, write a “0” to the Reference Overcurrent register. D/S Module Power Enable Note1: Reference Overcurrent feature added for DOM 8/2010 and later. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 296: Reference (Module W*) Pci Memory Map

    76C Module Design Revision 770 Module DSP 774 Module FPGA 778 Module ID 1C0 Power On Note1: Reference over-current added for DOM 8/2010 and later. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 296 of 330...

  • Page 297: Module Identification

    Read register as 16 bit binary word to determine Module DSP revision. For example, 0x000B is revision 12. Module DSP Revision D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 298: Module Fpga Revision

    Module ID D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION D=DATA BIT ASCII “C” ASCII “1” 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 298 of 330...

  • Page 299: General Use Register Memory Map

    This register contains the board serial number. As of date of manufacture (DOM) 7/2014: read as a (2)16-bit binary words (HI, LO concatenated). REGISTER D15 D14 D13 D12 D11 D10 D9 FUNCTION SERIAL NUMBER D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 299 of 330...

  • Page 300: Platform

    “ ” is in lower byte. REGISTER D15 D14 D13 D12 D11 D10 D9 FUNCTION SPECIAL SPEC D=DATA BIT ASCII “ ” ASCII “ ” 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 300 of 330...

  • Page 301: Date Code

    Read register to determine module processor firmware revision number. There is one register for each module slot (1 through REGISTER D15 D14 D13 D12 D11 D10 D9 FUNCTION PROCESSOR REVISION D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 301 of 330...

  • Page 302: Board Ready

    This register is used to define the Interrupt Priority Level. Enter 0 to disable interrupts. Enter in priority level 0 through 7 otherwise. REGISTER D15 D14 D13 D12 D11 D10 D9 FUNCTION INTERRUPT LEVEL D=DATA BIT 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 302 of 330...

  • Page 303: Design Version

    When the application interrupt callback is called by the driver, the vector should be removed from the queue and passed as a calling parameter. The application must not access the Interrupt Status register directly. 68C3 Operations Manual North Atlantic Industries, Inc.

  • Page 304: Customer Defined Register Allocation

    Subnet Mask IP Address Subnet Mask 192.168.1.5 255.255.255.0 192.168.2.5 255.255.255.0 Good 192.168.1.5 255.255.0.0 192.168.2.5 255.255.0.0 Conflict 192.168.1.5 255.255.0.0 192.168.2.5 255.255.255.0 Conflict 10.0.0.15 255.0.0.0 192.168.1.5 255.255.255.0 Good 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 304 of 330...

  • Page 305: Ethernet

    This limitation exists because every log out causes resources on the unit to linger for 40 seconds to catch any delayed packets (which is required for TCP). For reasons of performance speed, the unit is limited to approximately 1000 lingered sockets. 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 306: Type Codes Summary

    0x10 – Unknown type code error 0x11 – Address out of range error 0x12 – Address fell on odd boundary (all SYSTEM addresses must end in even numbers) 0x80 – Disconnecting port deliberately 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 307: 68C3 Connector/Pin-Out Information

    68C3 CONNECTOR/PIN-OUT INFORMATION Front and Rear Panel Connectors The 68C3 3U OpenVPX multi-function I/O board follows the OpenVPX “Payload Slot Profile” configured as: SLT3-PAY-2F2T-14.2.5 Full user I/O is available through the (J1, J2) front panel connectors when card is configured with front panel I/O and through the OpenVPX user defined rear I/O connectors P1, P2 (see part number and pin-out information).

  • Page 308: Front Panel (J1, J2) (Connector Placement And Orientation)

    68C3 Connector/Pin-Out Information Front Panel (J1, J2) (Connector Placement and Orientation): Front Panel LEDs [normal operation] ** Illuminated** ** Extinguished ** [Module(s) config OK] Module(s) config Fail [Card Access] [No Card Access] NOTE: LED on power-up does not necessarily indicate any fault.

  • Page 309: Rear I/O Vpx Connectors P0 - P2

    68C3 Connector/Pin-Out Information Rear I/O VPX Connectors P0 – P2: The 68C3 follows the OpenVPX defined rear I/O connectors (Tyco MultiGig RT-2) as per “Bridge Slot Profile” SLT3-PAY-2F2T-14.2.5 Note: Maximum ratings for the Tyco MultiGig RT-2 type connector are as follows (per Tyco 108-2072): 50 V peak or 50 VDC (I/O module signals must be constrained if rear I/O utilized).

  • Page 310: Rear I/O Utility Plane (P0)

    Rear I/O Data/Control Planes (P1) The 68C3 has the configuration option for specifying one of two high speed serial interface fabric bus connections – PCIe (x1) or SRIO (1x) (contact factory) as well as dual port Gig-E. As defined in the OpenVPX bridge or payload slot specifications, the 68C3 requires only one ‘ultra thin pipe’...

  • Page 311: Rear I/O Data/Control Planes (P1 Continued)

    The following pages contain the ‘user defined’ I/O data area front and rear panel pin-outs with their respective signal designations for all module types currently offered/configured for the 68C3 platform. The card is designed to route the function module I/O signals to the front and rear I/O connector. The following I/O connector pin-out is based upon the function module designated in the particular module slot.

  • Page 312: Rear I/O Summary

    68C3 Connector/Pin-Out Information Rear I/O Summary: P0 - Utility plane. Contains the following signal definitions: Power: Primary +5V, +/- 12V and System GND Geographical Address Pins: GA0# - GA4#, GAP# Card reset: SYSRST# signal P1 - Defined as primarily Data/Control Planes (User defined I/O secondary) High Speed Switched Fabric Interface: One ultra-thin pipe option (PCIe (x1) or SRIO (1x)).

  • Page 313: Slot 1 - Analog And Digital I/O Modules (User Defined I/O Pin-Outs)

    68C3 Connector/Pin-Out Information SLOT 1 – Analog and Digital I/O Modules (User Defined I/O Pin-Outs) Front I/O Rear I/O D/A HI-CURR Strain Gage (Slot 1 – DC Power Supply (C*) (F*/J*) D/A HI-V (J8) (F5) (G4) (G5) (V1, V2) -15V CH1...

  • Page 314: Slot 1 -Digital I/O Modules (User Defined I/O Pin-Outs)

    68C3 Connector/Pin-Out Information SLOT 1 –Digital I/O Modules (User Defined I/O Pin-Outs) Front I/O Isolated Rear I/O Diff. Discrete & TTL Discrete Relay (Slot 1 – (D8) (K6/D7) (K7) (KN / KL) CH1-COM J1-2 P2-B16 Ch01 H Ch01 Ch01-P J1-24...

  • Page 315: Slot 1 - Position/Motion Control I/O Modules (User Defined I/O Pin-Outs)

    68C3 Connector/Pin-Out Information SLOT 1 – Position/Motion Control I/O Modules (User Defined I/O Pin-Outs) Front I/O Note 1: TRIG1 and TRIG2 are Rear I/O 3 CH D/S 3CH DLV LVDT Reference (Slot 1 – module function dependent Encoder (E7) (S*)

  • Page 316: Slot 1 - Communications I/O Modules (User Defined I/O Pin-Outs)

    68C3 Connector/Pin-Out Information SLOT 1 – Communications I/O Modules (User Defined I/O Pin-Outs) Paired Flow Control Paired Flow Paired Flow (CH1,2 & Control (CH1,2 Control (CH3,4 Front I/O ARINC CH3,4) only) only) Rear I/O CANBus RS232 MIL-STD-1553 (Slot 1 –...

  • Page 317: Slot 2 - Analog I/O Modules (User Defined I/O Pin-Outs)

    68C3 Connector/Pin-Out Information SLOT 2 – Analog I/O Modules (User Defined I/O Pin-Outs) Front I/O Rear I/O D/A HI-CURR Strain Gage (Slot 2 – D/A HI-V DC Power Supply (C*) (F*/J*) (J8) (F5) (G4) (G5) (V1, V2) -15V CH1 J2-2...

  • Page 318: Slot 2 -Digital I/O Modules (User Defined I/O Pin-Outs)

    68C3 Connector/Pin-Out Information SLOT 2 –Digital I/O Modules (User Defined I/O Pin-Outs) Front I/O Isolated Rear I/O Diff. Discrete & TTL Discrete Relay (Slot 2 – (D8) (K6/D7) (K7) (KN / KL) CH1-COM J2-2 P2-B10 Ch01 H Ch01 Ch01-P J2-24...

  • Page 319: Slot 2 - Position/Motion Control I/O Modules (User Defined I/O Pin-Outs)

    68C3 Connector/Pin-Out Information SLOT 2 – Position/Motion Control I/O Modules (User Defined I/O Pin-Outs) Front I/O Rear I/O 3 CH D/S 3CH DLV LVDT Reference (Slot 2 – Encoder (E7) (S*) (6*) (5*) (L*) (W*) J2-2 P2-B10 AHI-CH1 Ch01 S1...

  • Page 320: Slot 2 - Communications Modules (User Defined I/O Pin-Outs)

    68C3 Connector/Pin-Out Information SLOT 2 – Communications Modules (User Defined I/O Pin-Outs) Paired Flow Control Paired Flow Paired Flow (CH1,2 & Control Control Front I/O ARINC CH3,4 (CH1,2 only) (CH3,4 only) Rear I/O CANBus RS232 MIL-STD-1553 (Slot 2 – 429/575...

  • Page 321: Slot 3 - Onboard Reference Or Multi-Function Combo (User Defined I/O Pin-Outs)

    68C3 Connector/Pin-Out Information SLOT 3 – Onboard Reference or Multi-Function Combo (User Defined I/O Pin-Outs) A/D, I/O DT Front I/O Rear I/O Onboard REF Combo (Slot 2 – J2) P1, P2 (W6, W7) (KA) P1-B12 IN-CH1 P1-C12 IN-CH2 P1-E12 IN-CH3...

  • Page 322: Connector Signal/Pin-Out Notes

    68C3 Connector/Pin-Out Information Connector Signal/Pin-Out Notes NAI Synchro/Resolver Naming Convention Signal Resolver Synchro SIN(-) COS(+) SIN(+) COS(-) No connect Pin-Out Notes Note: KA module channels 1-12 output only, channels 13-16 input/output programmable, channels 17-28 input only. KA module DT-I/O VCC pin for transient protection only – apply source VCC to DT-I/O VCC pin for voltage clamping purposes.

  • Page 323: Part Number Designation

    Part Number Designation PART NUMBER DESIGNATION 68C3 - XX XX XX X X X X X –XX Slot # MODULE (SLOT) 1&2 DEFINITION Reference the current “Available Function Modules” listing (i.e. Data Sheet/Specifications and/or Operations Manual). Enter Module Designation (i.e.C1) for each slot (1, 2). Enter ‘Z0’ if slot is not populated. Review the P/N Designation notes in the Operations Manual for valid combinations and application requirements as applied to specific modules/options selections.

  • Page 324: Part Number Notes

    Note: W1 only utilizes a mechanical relay for range switching. May not be suitable for some embedded system applications. Note 7: Following are the module designation selections for D/S and L/RVDT (DLV) simulation modules): 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 325: Channel D/S Module Code Table

    47 - 400 0.25 2 – 11.8 360 – 1K 10 – 115 0.25 *Consult factory for availability There is a +10% tolerance on the range limits 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 325 of 330...

  • Page 326: Channel Dlv Module Code Table

    5K – 7K 2 - 11.8 2-28 7K – 10K 2 - 11.8 2-28 * Consult factory for availability. ** +10% tolerance on the range limits 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com Page 326 of 330...

  • Page 327: Revision Page

    9) D/S description - remove inferance of 2s complement convention for angle data. 10) 75C5 and 75D4 platforms - initial Agile release (generic volume) Ops Manual/Specifications and 68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014 Rev: 2014-12-19-0947 www.naii.com...

  • Page 328: 68C3 Operations Manual

    Redefined/swapped Ethernet option (4) MB and U3 locations. 3) 76C2 Conn I/O Pinout - no content changes (Agile link only). 4) 67C3 Data Sheet/Spec/Manual: Added mech. option J and K; 67C3/68C3 P/N High Voltage operating warning note (P/N designation). 5) KA module correct/re-define discrete voltage thresholds from 100mV to 10mV lsb.

  • Page 329: 68C3 Operations Manual

    OF ALL DOCUMENTS 75C2: REFORMATTING OF ALL DOCUMENTS 76C2: REFORMATTING OF ALL DOCUMENTS 79C3: REFORMATTING OF ALL DOCUMENTS 67C3: REFORMATTING OF ALL DOCUMENTS Initial Agile release - 68C3 Data Sheet 64C2 Operations Manual/Specifications - BOM ammendment and filename revision removal for select sub-documents...
  • Page 330 The information provided in this manual is believed to be accurate. This document must be reviewed prior to use in the customers’ organizations. No responsibility is assumed by North Atlantic Industries for its use and no licenses or rights are granted by implication or otherwise in connection therewith.

Table of Contents