Norsk Data ND-100 Manuals

Manuals and User Guides for Norsk Data ND-100. We have 1 Norsk Data ND-100 manual available for free PDF download: Reference Manual

Norsk Data ND-100 Reference Manual

Norsk Data ND-100 Reference Manual (265 pages)

Brand: Norsk Data | Category: Desktop | Size: 8 MB

Table of Contents

Table of Contents
6
General Characteristics
14
- General
  16
ND- 700 Central Processing Unit (CPU) Module
18
CPU Characteristics
19
ND- 700 Architecture
20
General
20
ND-100 Configuration Examples
21
Multiprocessor Systems
22
Remote Operation
23
The Interrupt System
24
The Memory Management System
26
The Memory System
26
Main Memory
26
Cache Memory
26
The Input/Output System
27
- Programmed Input/Output - PIO
  27
Direct Memory Access - DMA
27
Nd- 700 Peripheral Equipment
28
Nd- 700 Software
29
- The Operating System
  29
Supporting Software
30
Distributed Data Processing
30
- System Description
  32
General
32
Central Processor
32
The Address Arithmetic
34
Instruction Fetch
34
Prefetch
34
Instruction Execution
35
Main Arithmetic
35
The Register File
37
Status Indicators
39
The Interrupt System
41
General
41
Functional Description
43
The External Interrupt System
45
The Internal Interrupt System
47
- Internal Hardware Status Interrupts
  49
- Reset of the IIC Register
  51
Programmming Control of the Interrupt System
52
The Memory Management System
56
General
56
Memory Management Architecture
57
The Paging System
59
The Shadow Memory
61
The
63
- Page Used and Written in Page
  65
- Page Table Selection
  65
Memory Protection System
66
- Page Protection System
  66
- Ring Protection System
  68
Privileged Instructions
70
Memory Management Control and Status
71
The SEX and REX Instructions
74
Memorysystem
75
General
75
ND- 700 Memory Architecture
77
- Local (Main) Memory
  78
- The Position Code
  78
- The Thumbwheel Setting
  79
  - Memory Error Correction
    81
  - Memory Control and Status
    83
- Error Correction Control Register (ECCR)
  83
- Memory Status Regsiters (PEA and PES)
  84
Multiport Memory
85
- Big Multiport Memory (BMPM)
  85
- Multiport Memory 4 (MPM4)
  85
Cache Memory
86
- Cache Memory Architecture
  86
- Cache Memory Organization
  87
- Cache Control and Status
  89
  - Cache Control
    89
  - 2.4.6.3.2 Cache Status Register
    90
Nd- 700 Input/ Output System
91
General
91
The ND-100 Bus
96
Programmed Input/Output - PIO
98
Direct Memory Access (DMA)
103
- General
  103
- DMA Controller Operation
  103
- Initialization
  104
- Transfer
  104
- Termination and Status Check
  104
  - General Considerations
    105
The I/O System and the Interrupt System
106
- General
  106
- Interrupt Level Usage
  106
- Device Interrupt Identification
  107
Programming Specifications for |/O Device on the CPU Board
107
- The Real-Time Clock
  108
- The Current Loop Interface
  108
General
110
Bus Extender Architecture
110
Nd-Ioo Instructions
112
General
112
Instruction and Data Formats
114
- Single Bit
  114
- Bit Byte
  115
- 16 Bit Word
  115
- 32 Bit Double Word
  116
  - 48 Bit Floating Point Word
    117
The Instruction Repertoire
120
Memory Reference Instructions
120
- Addressing Structure
  120
- Store Instructions
  129
- Load Instructions
  131
  - Arithmetical and Logical Instructions
    132
  - Sequencing Instructions
    135
  - Byte Instructions
    137
  - Extended BYTE-Instructions
    138
- Register Instructions
  141
  - Floating Point Conversion Instructions
    141
    
    Standard 48 Bit Floating Point Conversion
    141
    
    3.2.2.1.2 Optional 32 Bit Floating Point Conversion
    143
    
    Shift Instructions
    144
    
    Register Operations
    147
    
    ROP - Register Operation Instructions
    149
    
    Extended Register Operation Instructions
    156
    
    Skip Instructions
    158
    
    Argument Instructions
    161
    
    Bit Operation Instructions
    164
    
    Bit Skip Instructions
    165
Bit Set Instructions
165
- 3.2.2.6.3 One Bit Accumulator Instructions
  166
- System Control Instructions
  167
  - Monitor Call Instruction
    167
  - Inter-Level Register Instructions
    170
  - Input/Output Control Instructions
    174
    
    Extension of the Device Register Address
    175
  - System Control Instructions
    175
    
    Interrupt Control Instructions
    176
    
    Wait or Give up Priority
    181
  - Examine and Deposit
    182
  - Load Writeable Control Store
    183
    
    Format of Instructions
    185
    
    Addressing
    186
Instructions in the «Commercial Extended
187
- Decimal Instructions
  187
  - Data Formats for Decimal Instructions
    187
    
    Packed Decimal Number
    187
    
    ASCII Coded Decimal Number
    189
    
    The Decimal Instructions
    191
  - Stack Handling Instructions
    196
    
    Data Structure Operated Upon by the Instructions
    196
- Operator's Interaction
  198
Control Panel Push Buttons
198
- The Panel Lock Key
  200
- Status Indicators
  200
- General Considerations
  201
- Control Functions
  203
  - System Control
    203
    
    Master Clear
    203
    
    Stop
    203
    
    ALD Load
    204
    
    Continue Program
    205
    
    General Load
    205
    
    Leave MOPC
    205
    
    Program Execution
    205
    
    Start Program
    205
    
    Instruction Breakpoint
    206
    
    Manual Instruction
    206
    
    Single I/O Instruction Function
    206
    
    Singleinstruction
    206
  - Miscellaneous Functions
    207
    
    Current Location Counter
    207
    
    Delete Entry
    207
    
    Internal Memory Test
    207
Monitor Functions
208
- Memory Functions
  208
  - Physical Examine Mode
    208
  - Virtual Examine Mode
    208
  - Memory Examine
    209
  - Memory Deposit
    209
  - Deposit Rules
    210
  - Memory Dump
    210
  - Register Functions
    211
    
    Register Examine
    211
    
    Register Deposit
    212
    
    Register Dump Rd
    212
    
    Userregisteru
    212
    
    Operator Panel Switch Register - OPR
    213
    
    Internal Register Examine
    214
    
    Internal Register Functions
    214
    
    Internal Register Deposit
    215
- Display Functions
  217
  - Displayed Format
    217
  - Display Memory Bus
    218
  - Display Activity
    218
- Bootstrap Loaders
  219
  - Binary Format Load
    219
  - Mass Storage Load
    220
  - Automatic Load Descriptor
    221
- General
  222
- The Different Display Functions
  222
- Model 33 Asr/Ksr Teletype Code (Ascii) in Binary Form
  240
- Andident Codes
  242
- Internal Registers
  248
  - Switch Settings for the Different Nd-100 Modules
    250
  - Switches on the CPU Module (3002)
    250
  - ALD - Automatic Load Descriptor
    250
    
    Console: Speed Setting for Console Terminal
    251
  - Floppy Disk System
    252
  - Terminal Group
    252
  - Initial Baud Rate for Terminals
    253
- Survey
  260
Control Functions (Does Not Affect DISPLAY
260
Display Functions (Affects Only DISPLAY
260
- Nd-Ioo Technical Specifications
  262
Specifications
262

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